JPS62287647A - 半導体チツプの接続バンプ - Google Patents

半導体チツプの接続バンプ

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Publication number
JPS62287647A
JPS62287647A JP61132327A JP13232786A JPS62287647A JP S62287647 A JPS62287647 A JP S62287647A JP 61132327 A JP61132327 A JP 61132327A JP 13232786 A JP13232786 A JP 13232786A JP S62287647 A JPS62287647 A JP S62287647A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor chip
bump
alloy
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61132327A
Other languages
English (en)
Inventor
Hisako Mori
久子 森
Yoshihiro Bessho
芳宏 別所
Yasuhiko Horio
泰彦 堀尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61132327A priority Critical patent/JPS62287647A/ja
Publication of JPS62287647A publication Critical patent/JPS62287647A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/0554—External layer
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ３、発明の詳細な説明 産業上の利用分野 本発明は、半導体チップに代表される、チップ状の電子
部品を基板上の端子電極群に接続する際の半導体チップ
の接続バンブ（端子）に関するものである。
従来の技術 従来、電子部品の接続端子と基板上の回路パターン端子
との接続には半田付け（Ｐｂ　−Ｓｎ半田）がよく利用
されていたが、近年、例えばＩＣフラットパッケージ等
の小型化と、接続端子の増加により接続端子間、いわゆ
るピッチ間隔が次第に狭くなり、従来の半田付は技術で
対処することが困難になってきた。また最近では電卓、
電子時計あるいは液晶デバイス等にあっては、裸の半導
体チップをガラス基板上の透明電極にフェースダウンで
直付けして実装面積の効率的使用と配線の合理化を図ろ
うとする動きがあり、従来法に代わる有効かつ微細な電
気的接続手段が望まれている。裸の半導体チップをガラ
ス基板上の透明電極に電気的に接続する方法としては、
電子材料１９８５年９月号（Ｐ　４９）に示されている
様に異方導電性シートを使った圧接方式が知られている
。
半導体チップを直接実装する、いわゆるフリップチップ
実装においては、従来からＰｂ　−Ｓｎからなる半田バ
ンプを用いたのが一般的である。液晶デバイス等のガラ
ス基板上の透明電極上へのフリップチップ実装も種々検
討されているが、その主な方法の１つとしては、透明電
極上に端子電極としてＣｒ、　Ｃｕ等の電極を形成し、
この上にＰｂ　−Ｓｎの半田バンプが形成された半導体
チップを実装する方法がある。また他の例としてはＡｕ
バンプと異方導電性シートを使った方式がある。そこで
従来例として、異方導電性シートを使った圧接方式を図
４゜５を用いて説明する。第５図で示しである様に、半
導体チップのアルミニウムパッド上に、Ａｕバンプ１６
を形成し、これと対応する電極をパネル電極上に設け１
８、パネル電極とＡｕバンプ間に凸状のこの導電性シー
トを介在させ、押さえ金具１５で圧接した構成により半
導体チップをガラス基板の透明電極上に接続している。
発明が解決しようとする問題点 しかしながら斯かる方法にあっては異方導電性シートを
別工程で作り込む必要があり、工程が複雑になる。また
Ａｕバンプを使用する為コストアップの要因となる加え
て、その精度も問題となる。
また接続方式がパネル電極と回路基板との間にゼブラ状
の異方導電性シートを介在させ押さえ金具で圧接した間
接圧接方式である為、接触抵抗の増大、押さえ金具の絶
縁リークを考慮しなければならない。
本発明は上記問題点に鑑みて発明されたもので、その目
的とするところはガラス基板上に微細に形成された透明
電極と半導体チップの接続バンプを信頼性よく電気的接
続を行うことにある。
問題点を解決するための手段 上記問題点を解決するために、本発明の半導体チップの
接続バンプは、アルミニウムパッド上に中間金属層を介
してＩｎ　−Ｓｎ合金からなる突起電極を構成したこと
を特徴としている。
作用 本発明は上記した構成によって、従来法の様に異方導電
性シートを別工程で作るという様な、複雑な工程はなく
、Ｉｎ　−Ｓｎ合金の接続バンプ（端子）−もホトリソ
技術と蒸着法あるいはメッキ法によって構成できるので
工法も簡単で安価である。またこの接続バンプは金属材
料による合金接合であり、さらにＩｎ　−Ｓｎ合金は比
較的柔らかく熱疲労に強い為、接合部の信頼性が高くな
ると言える。加えて有機材料を使った場合に比べ接触抵
抗も低くなる。
又Ｉｎ　−Ｓｎ合金は低融点の合金である為、接着時に
過大な熱および圧力がかからないという特色も備えてい
る。
実施例 以下に本発明の半導体チ・ノブの接続バンプの一実施例
について図面を参照しながら説明する。第１図と第２図
は接続バンプ（端子）の構成された半導体チップの断面
図を示す。また第３図はこの接続バンプ（端子）を有す
る半導体チ・ノブをガラス基板上の透明端子電極上に実
装した時の断面図である。第４図は異方導電性シートを
用いた従来例の断面図、第５図は従来例の半導体チ・ノ
ブと異方導電性シートの断面図である。
ｌはシリコン基板、２はＡｌ電極、３は表面保護膜、４
は中間金属層、５はＳｎ層、６はＩｎＪｉｉ、７はＩｎ
　−Ｓｎ接続バンプ（端子）、１０はガラス基板、１１
は液晶、１２は透明電極、１３は半導体チップである。
本発明の接続ハンプ（端子）の構成法を説明する。１の
シリコン基板上にＡｌ電極２を形成し、ＳｉＯ□等の表
面保護層３を形成する。前記ＡＩ電極上にＣｒ、　Ｔｉ
等のへ１電極のバリア層とＣｕ、　Ａｕ等の密着強度強
化層からなる中間金属層４を蒸着とホトリソ技術により
形成する。次にメソキレシストをバターンニングし、Ａ
Ｉ電極上のみにＳｎメッキとＩｎメッキを行い約２０〜
３０μｍの高さのバンプを形成する。この時のメッキの
順序は適宜選択すればよい。
またこのバンプは蒸着法により形成してもよい。
続いてＩｎ　−Ｓｎ合金の溶融温度で加熱溶融すること
により第２図の様な半球状のＩｎ　−Ｓｎの合金バンプ
を形成する。尚Ｉｎ　−Ｓｎ合金の組成であるが、液晶
表示装置に用いる場合は１５０℃以下に液相温度をもつ
低融点の組成が適切であり、５２Ｉｎ　　４８Ｓｎの共
晶合金、あるいは５０Ｉｎ−５０Ｓｎ　（液相温度１２
５℃）５２Ｓｎ−４８Ｉｎ　（液相温度１３１℃）が適
切と言えるが、必要に応じその組成は選択すればよい。
前記の様にして形成された接続バンプを有する半導体チ
ップをガラス基板上の透明端子電極と位置合わせ後、適
切な加熱溶融法あるいは適切な加熱超音波法により電気
的接続と接着を同時に行う。
発明の効果 以上の様に本発明は、半導体チップのアルミニウムパッ
ド上に中間金属層を介してＩｎ　−Ｓｎ合金からなる突
起電極を構成したことを特徴とする特許体チップの接続
バンプであり、これにより従来法の様に異方導電性シー
トを別工程で作るという様な複雑な工程はなく、Ｉｎ　
−Ｓｎ合金の接続バンプ（＠子）もメッキ法あるいは蒸
着法により構成できるので工法も簡単で安価になる。ま
た接続バンプ（端子）は金属材料による合金接合であり
、さらにＩｎ　−Ｓｎ合金は比較的柔らか（熱疲労に強
い為、接合部の信頼性も高（なる。加えて有機材料を使
った場合に比べ接触抵抗も低くなる。Ｉｎ　−Ｓｎ合金
を低融点の合金材料である為、接着時に過大な熱および
圧力がからなくなると言える。
【図面の簡単な説明】
第１図と第２図は接続バンプ（端子）の形成された半導
体チップの断面図、第３図はこの接続バンプ（端子）を
有する半導体チップをガラス基板上の透明端子電極上に
実装した時の断面図、第４図は異方導電性シートを用い
た実装法の断面図、第５図は従来例の半導体チップと異
方導電性シートの断面図である。 １・・・・・・シリコン基板、２・・・・・・Ａ１電極
、３・・・・・・表面保護膜、４・・・・・・中間金属
層、５・・・・・・Ｓｎ層、６・・・・・・Ｉｎ層、７
・・・・・・Ｉｎ−５ｎ接続バンプ（端子）、１０・・
・・・・ガラス基板、１１・・・・・・液晶、１２・・
・・・・透明電極、１３・・・・・・半導体チップ、１
４・・・・・・異方導電性シート、１５・・・・・・押
さえ金具、１６・・・・・・Ａｕバンブ、１７・・・・
・・ポリイミド、１８・・・・・・導電性シリコン樹脂
。 代理人の氏名　弁理士　中尾敏男　ほか１名／−−−シ
１ｊコン邑坂 ２−−−Ａｌ電境 ５−−−３ｎＪＡ 第１　図　　　　　　　　　　６−−−エ７Ｌ１７−−
−エ几−３ｒＬオ逅Δ究ンくンフ℃咋Ｓ）第２図　　７ 第３図 ／２７　　　　／２／／　　　ｙ０ 第４図 ｉ　ｓ　ｖ　　　　　／３ ！ ／？″

Claims (1)

    【特許請求の範囲】
  1. 半導体チップのアルミニウムパッド上に中間金属層を介
    してＩｎ−Ｓｎ合金からなる突起電極を構成したことを
    特徴とする半導体チップの接続バンプ。
JP61132327A 1986-06-06 1986-06-06 半導体チツプの接続バンプ Pending JPS62287647A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61132327A JPS62287647A (ja) 1986-06-06 1986-06-06 半導体チツプの接続バンプ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61132327A JPS62287647A (ja) 1986-06-06 1986-06-06 半導体チツプの接続バンプ

Publications (1)

Publication Number Publication Date
JPS62287647A true JPS62287647A (ja) 1987-12-14

Family

ID=15078726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61132327A Pending JPS62287647A (ja) 1986-06-06 1986-06-06 半導体チツプの接続バンプ

Country Status (1)

Country Link
JP (1) JPS62287647A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068410A (ja) * 1998-08-20 2000-03-03 Nishihara Riko Kk Ｐｂに代わる接合材料で接合端子部にバンプメッキを施した ＢＧＡ又は ＣＳＰ等のＩＣパッケ−ジ
JP2004289113A (ja) * 2003-03-05 2004-10-14 Mitsubishi Electric Corp 金属電極とこれを用いた接合方法
JPWO2016056656A1 (ja) * 2014-10-10 2017-09-14 石原ケミカル株式会社 合金バンプの製造方法
WO2022050186A1 (ja) * 2020-09-04 2022-03-10 株式会社新菱 Ｓｎ－Ｉｎ系低融点接合部材およびその製造方法ならびに半導体電子回路およびその実装方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068410A (ja) * 1998-08-20 2000-03-03 Nishihara Riko Kk Ｐｂに代わる接合材料で接合端子部にバンプメッキを施した ＢＧＡ又は ＣＳＰ等のＩＣパッケ−ジ
JP2004289113A (ja) * 2003-03-05 2004-10-14 Mitsubishi Electric Corp 金属電極とこれを用いた接合方法
JPWO2016056656A1 (ja) * 2014-10-10 2017-09-14 石原ケミカル株式会社 合金バンプの製造方法
WO2022050186A1 (ja) * 2020-09-04 2022-03-10 株式会社新菱 Ｓｎ－Ｉｎ系低融点接合部材およびその製造方法ならびに半導体電子回路およびその実装方法

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