JPS62283676A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPS62283676A JPS62283676A JP12845986A JP12845986A JPS62283676A JP S62283676 A JPS62283676 A JP S62283676A JP 12845986 A JP12845986 A JP 12845986A JP 12845986 A JP12845986 A JP 12845986A JP S62283676 A JPS62283676 A JP S62283676A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- source
- effect transistor
- field effect
- vertical field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 230000003247 decreasing effect Effects 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 238000009826 distribution Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8122—Vertical transistors
Abstract
Description
【発明の詳細な説明】
発明の詳細な説明
〔産業上の利用分野〕
本発明は縦形電界効果トランジスタに関し、特に化合物
半導体を用いた高耐圧・高出力の縦形電界効果トランジ
スタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical field effect transistor, and more particularly to a high breakdown voltage, high output vertical field effect transistor using a compound semiconductor.
化合物半導体を用いた縦形電界効果ｌ・ランジスタは、
実効的なゲート長が容易に微細に形成でき、かつ大きな
チャネル電流がとれることから超高周波・高出力素子と
して極めて有望であり、各所で研究・開発が活発に行な
われている。第３図は従来構造の縦形電界効果トランジ
スタの一例を示す断面図で、半導体としてＧａＡｓを用
い、３１はＮ型半導体層であるＮ形動布層、３２．３３
はＮ＋コンタクト層、３４はソース電極、３５はドレイ
ン電極、３６は制御電極、３７は空乏層領域を示す。Vertical field effect l transistor using compound semiconductor is
Since the effective gate length can be easily formed to a fine size and a large channel current can be obtained, it is extremely promising as an ultra-high frequency/high output device, and research and development are being actively conducted in various places. FIG. 3 is a cross-sectional view showing an example of a vertical field effect transistor with a conventional structure, in which GaAs is used as the semiconductor, 31 is an N-type dynamic layer which is an N-type semiconductor layer, 32.33
34 is a source electrode, 35 is a drain electrode, 36 is a control electrode, and 37 is a depletion layer region.
前記構造の従来の縦形電界効果トランジスタを高耐圧・
高出力の超高周波トランジスタとして使用する場合、良
好な高周波性能を得るためにはソースと制御電極間の抵
抗を十分小さくし大きな相互コンダクタンスを得る必要
があり、この為にはＮ形半導体動作層の不純物濃度をあ
る程度大きくしなければならない。一方、ドレインにパ
イアスを印加した状態では制御電極からドレイン電極に
向って大きな電界が生じるために、この領域の不純物濃
度が大きいと降伏現象が生じて、ある程度以上の高耐圧
・高出力化が計れないという問題があった。The conventional vertical field effect transistor with the above structure has a high breakdown voltage.
When used as a high-power ultra-high frequency transistor, in order to obtain good high-frequency performance, it is necessary to sufficiently reduce the resistance between the source and control electrodes and obtain large mutual conductance. The impurity concentration must be increased to some extent. On the other hand, when a bias is applied to the drain, a large electric field is generated from the control electrode to the drain electrode, so if the impurity concentration in this region is large, a breakdown phenomenon will occur, making it difficult to achieve high breakdown voltage and high output beyond a certain level. The problem was that there was no.
本発明の目的は、この様な問題点を解消し、高耐圧・高
出力で超高周波特性の優れた縦形電界効果トランジスタ
な提供することにある。An object of the present invention is to solve these problems and provide a vertical field effect transistor that has high breakdown voltage, high output, and excellent ultra-high frequency characteristics.
本発明の縦形電界効果トランジスタは、Ｎ形半導体層を
挟んで上端及び下端にＮ＋コンタクト層が形成され、前
記Ｎ形半導体層中に制御電極が埋め込まれ、前記Ｎ＋コ
ンタクト層の一方にソース電極、他方にドレイン電極を
有する縦形電界効果トランジスタにおいて、前記Ｎ形半
導体層の不純物濃度をソースからドレインに向って連続
的に減少させたことを特徴として構成される。In the vertical field effect transistor of the present invention, N+ contact layers are formed at the upper and lower ends with an N-type semiconductor layer in between, a control electrode is embedded in the N-type semiconductor layer, a source electrode is provided in one of the N+ contact layers, and a control electrode is embedded in the N-type semiconductor layer. A vertical field effect transistor having a drain electrode on the other hand is characterized in that the impurity concentration of the N-type semiconductor layer is continuously decreased from the source to the drain.
し作用〕
次に、本発明の一実施例の図面を参照して作用を説明す
る。第１図は本発明による縦形電界効果トランジスタの
一実施例の断面図である。半導体材料はＧａＡｓで１１
はＮ形動作層、１２．１３はＮ＋コンタクト層、１４は
Ｎ＋基板、１５はソース電極、１６はドレイン電極、１
７は制御電極、１８は空乏層領域を示す。１１のＮ形動
作層の不純物濃度はソースからトレインに向って連続的
に減少させてあり、その分布の一例を第２図に示す。例
えば、第２図ではＮ形不純物濃度をソースからドレイン
に向って１ ｄ’ ｃｍ３ から３×１０１６Ｃ１１
−’まで連続的に変化させであるが、この様な構造では
ソース側では十分小さいソース抵抗、従って、大きな相
互コンダクタンスが実現でき、また高電界分布となるゲ
ートからドレイン方向へは小さな不純物濃度により降伏
電圧を大きくでき、従って、高耐圧・高出力の超高周波
縦形電界効果トランジスタが実現できる。Operation] Next, the operation of an embodiment of the present invention will be explained with reference to the drawings. FIG. 1 is a cross-sectional view of one embodiment of a vertical field effect transistor according to the present invention. The semiconductor material is GaAs and 11
is an N-type operating layer, 12.13 is an N+ contact layer, 14 is an N+ substrate, 15 is a source electrode, 16 is a drain electrode, 1
7 is a control electrode, and 18 is a depletion layer region. The impurity concentration of the N-type active layer No. 11 is continuously decreased from the source to the train, and an example of its distribution is shown in FIG. For example, in Figure 2, the N-type impurity concentration is increased from 1 d' cm3 to 3 x 1016C11 from the source to the drain.
-', but in this structure, a sufficiently small source resistance on the source side and therefore a large mutual conductance can be achieved, and a small impurity concentration in the direction from the gate to the drain, where there is a high electric field distribution, can be achieved. The breakdown voltage can be increased, and therefore an ultra-high frequency vertical field effect transistor with high breakdown voltage and high output can be realized.
次に、本発明の実施例について図面を参照して説明する
。第１図は本発明の一実施例の断面図であり、第１図を
用いてその製造方法を説明する。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of one embodiment of the present invention, and the manufacturing method thereof will be explained using FIG.
まず、Ｎ”ＧａＡｓ基板１４上に例えば有機金属気相成
長法（ＭＯＣＶＤ法）により不純物濃度１×し、さらに
第２図の分布に従ってＧａＡｓ Ｎ形動作層を０．７μ
ｍ成長する。次に、スパッタ法などによりタングステン
を０．１μｍ成長しパターンニング及びエツチングによ
り１７の制御電極を形成し、さらにＧａＡｓ動作層を０
．３μｍ成長する。次に、不純物濃度Ｉ Ｘ １０１８
ｃｒｒｒ３でＮ＋コンタクト層を０．５μｍ成長し、最
後に通常の方法により、ソース及びドレイン電極を形成
すれば、第１図に示すような縦形電界効果トランジスタ
、すなわちＮ形半導体層１１を挟んで上端及び下端にＮ
＋コンタクト層１２．１３が形成され、Ｎ形半導体層１
１中に制御電極１７が埋め込まれ、Ｎ＋コンタクト層の
一方にソース電極１５、他方にドレイン電極１６を有す
る縦形電界効果トランジスタにおいて、Ｎ形半導体層１
１の不純物濃度をソースからドレインに向って連続的に
減少させたことを特徴とする構造の本発明の一実施例が
得られる。First, an impurity concentration of 1× is formed on the N''GaAs substrate 14 by, for example, metal organic chemical vapor deposition (MOCVD), and then a GaAs N-type active layer is formed with a concentration of 0.7 μm according to the distribution shown in FIG.
m grow. Next, tungsten was grown to a thickness of 0.1 μm by sputtering or the like, and 17 control electrodes were formed by patterning and etching, and a GaAs active layer was grown to 0.1 μm.
．． Grows 3 μm. Next, the impurity concentration I x 1018
By growing an N+ contact layer of 0.5 μm using crrr3 and finally forming source and drain electrodes using the usual method, a vertical field effect transistor as shown in FIG. and N at the bottom end
+Contact layers 12 and 13 are formed, and N-type semiconductor layer 1
In a vertical field effect transistor having a control electrode 17 embedded in the N+ contact layer 1, a source electrode 15 on one side of the N+ contact layer, and a drain electrode 16 on the other side, the N-type semiconductor layer 1
An embodiment of the present invention is obtained having a structure characterized in that the impurity concentration of 1 is continuously decreased from the source to the drain.
なお、本実施例ではＧａＡｓ材料を用いた縦形電界効果
トランジスタについて説明したが、他の半導体材料につ
いても本発明による構造はすぐれた効果を提供すること
かできる。In this embodiment, a vertical field effect transistor using GaAs material has been described, but the structure according to the present invention can also provide excellent effects on other semiconductor materials.
以上の説明から明らかな様に、本発明によればＮ型半導
体層の不純物濃度をソースからドレインに向って連続的
に減少させることにより、マイクロ波・ミリ波領域で動
作する高性能の高耐圧・高出力の縦形電界効果トランジ
スタが実現でき、今後の通信・情報技術に寄与するとこ
ろが大である。As is clear from the above explanation, according to the present invention, by continuously decreasing the impurity concentration of the N-type semiconductor layer from the source to the drain, it is possible to achieve high performance and high breakdown voltage operation in the microwave and millimeter wave regions.・High-output vertical field-effect transistors can be realized, which will greatly contribute to future communications and information technology.
第１図は本発明による縦形電界効果トランジスタの一実
施例の断面図、第２図は本発明の一実施例のＮ形動作層
の不純物濃度分布図、第３図は従来技術による縦形電界
効果トランジスタの一例の断面図である。
１１．３１・・・Ｎ形動作層、１２．１３，３２゜３３
・・・Ｎ＋コンタクト層、１４・・・Ｎ＋基板、１５．
３４・・・ソース電極、１６．３５・・・ドレイン電極
、１７．３６・・・制御電極、１８．３７・・・空乏層
領域。
第 ７ 図
距 籠 ドレイン方句第 ２ 図FIG. 1 is a cross-sectional view of an embodiment of a vertical field effect transistor according to the present invention, FIG. 2 is an impurity concentration distribution diagram of an N-type active layer of an embodiment of the present invention, and FIG. 3 is a vertical field effect transistor according to the prior art. FIG. 2 is a cross-sectional view of an example of a transistor. 11.31...N-type operating layer, 12.13, 32°33
...N+ contact layer, 14...N+ substrate, 15.
34... Source electrode, 16.35... Drain electrode, 17.36... Control electrode, 18.37... Depletion layer region. Fig. 7 Drain phrase Fig. 2
Claims (1)
ト層が形成され、前記Ｎ形半導体層中に制御電極が埋め
込まれ、前記Ｎ＾＋コンタクト層の一方にソース電極、
他方にドレイン電極を有する縦形電界効果トランジスタ
において、前記Ｎ形半導体層の不純物濃度をソースから
ドレインに向って連続的に減少させたことを特徴とする
縦形電界効果トランジスタ。N^+ contact layers are formed at the upper and lower ends of the N-type semiconductor layer, a control electrode is embedded in the N-type semiconductor layer, and a source electrode is formed in one of the N^+ contact layers.
A vertical field effect transistor having a drain electrode on the other side, wherein the impurity concentration of the N-type semiconductor layer is continuously decreased from the source to the drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12845986A JPS62283676A (en) | 1986-06-02 | 1986-06-02 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12845986A JPS62283676A (en) | 1986-06-02 | 1986-06-02 | Vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62283676A true JPS62283676A (en) | 1987-12-09 |
Family
ID=14985233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12845986A Pending JPS62283676A (en) | 1986-06-02 | 1986-06-02 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62283676A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS524753B1 (en) * | 1966-10-19 | 1977-02-07 | ||
| JPS5363875A (en) * | 1976-11-18 | 1978-06-07 | Mitsubishi Electric Corp | Field effect semiconductor device |
| JPS5384570A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Field effect semiconductor device and its manufacture |
-
1986
- 1986-06-02 JP JP12845986A patent/JPS62283676A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS524753B1 (en) * | 1966-10-19 | 1977-02-07 | ||
| JPS5363875A (en) * | 1976-11-18 | 1978-06-07 | Mitsubishi Electric Corp | Field effect semiconductor device |
| JPS5384570A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Field effect semiconductor device and its manufacture |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10886393B2 (en) | High electron mobility transistor with tunable threshold voltage | |
| JP2001060684A (en) | Semiconductor device | |
| JPH10209178A (en) | Field-effect transistor and its manufacture | |
| US3804681A (en) | Method for making a schottky-barrier field effect transistor | |
| US4106044A (en) | Field effect transistor having unsaturated characteristics | |
| JPH06204253A (en) | Field-effect semiconductor device | |
| JPS62283676A (en) | Vertical field-effect transistor | |
| JPH08321515A (en) | Semiconductor device and its manufacture | |
| JPS63244779A (en) | Field effect transistor | |
| JPS62115781A (en) | Field-effect transistor | |
| JPH0855861A (en) | Field-effect transistor and its manufacture | |
| JPS62232969A (en) | Vertical field-effect transistor | |
| KR100303173B1 (en) | Pseudomorphic High Electron Mobility Transistor and method for manufacturing thereof | |
| KR100349368B1 (en) | Extremely high frequency semiconductor device and method of manufacturing the same | |
| JP3106747B2 (en) | Method for manufacturing compound semiconductor FET | |
| JPH11176839A (en) | Semiconductor device and its manufacture | |
| JP3073685B2 (en) | Method for manufacturing field effect transistor | |
| JPH039340Y2 (en) | ||
| JPS63281474A (en) | Semiconductor device | |
| JPH01179460A (en) | Field-effect transistor | |
| JPS6239076A (en) | Manufacture of field effect transistor | |
| JPS6394686A (en) | Manufacture of silicon thin film transistor | |
| JPH03133143A (en) | Field effect transistor and manufacture thereof | |
| JPS6323367A (en) | Schottky gate field-effect transistor and manufacture thereof | |
| JPH03141650A (en) | Manufacture of semiconductor device |