JPS62115781A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPS62115781A JPS62115781A JP25474185A JP25474185A JPS62115781A JP S62115781 A JPS62115781 A JP S62115781A JP 25474185 A JP25474185 A JP 25474185A JP 25474185 A JP25474185 A JP 25474185A JP S62115781 A JPS62115781 A JP S62115781A
- Authority
- JP
- Japan
- Prior art keywords
- active layer
- layer
- drain
- undoped
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はマイクロ波帯に用いる接合型電界効果トランジ
スタの構造に係り、特にアナログ素子に好適であり、高
出力用にドレイン耐圧を大幅に改善するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to the structure of a junction field effect transistor used in the microwave band, and is particularly suitable for analog devices, and greatly improves drain breakdown voltage for high output. It is something.
従来のマイクロ波帯で使用する高出力用電界効果トラン
ジスタは、ドレイン電圧を大きくするため、第1図(a
)に示すようなりセス形状型構造、第1図(b)に示す
ような、n十層オーミック領域7を埋込みした構造とな
っていた〔信号技報(電子通信学会)Vo 1.77、
Na212.ED77−80P19−25)、尚、図に
おいて、1は半導体基板、2はバッファ層、3は能動層
、4はソース電極、5はドレイン電極、6はゲート電極
である。しかしこれらの構造では高周波での素子内部利
得を大きくするとドレイン耐圧が小さくなる欠点があっ
た。その理由として、素子内部利得を大きくするために
、能1’ll1層となる半導体層の不純物濃度を高くす
る必要があり、このため半導体の不純物濃度の増大に伴
なって、ドレイン耐圧が小さくなる。Conventional high-output field effect transistors used in the microwave band are designed to increase the drain voltage as shown in Figure 1 (a).
) as shown in FIG. 1(b), and a structure in which n-ten layer ohmic regions 7 were buried as shown in FIG. 1(b) [Signal Technical Report (IEICE) Vo 1.77,
Na212. ED77-80P19-25), in the figure, 1 is a semiconductor substrate, 2 is a buffer layer, 3 is an active layer, 4 is a source electrode, 5 is a drain electrode, and 6 is a gate electrode. However, these structures have the disadvantage that when the internal gain of the element at high frequencies is increased, the drain breakdown voltage is reduced. The reason for this is that in order to increase the internal gain of the device, it is necessary to increase the impurity concentration of the semiconductor layer, which becomes the functional layer, and as a result, as the impurity concentration of the semiconductor increases, the drain breakdown voltage decreases. .
本発明の目的は上記欠点を解決した電界効果トランジス
タを提供することにある。すなわち、能動層の不純物濃
度を高くしても、ドレイン耐圧を劣化させないで、大き
くさせる電界効果トランジスタ構造を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a field effect transistor that overcomes the above-mentioned drawbacks. That is, the object of the present invention is to provide a field effect transistor structure in which the drain breakdown voltage is increased without deteriorating even when the impurity concentration of the active layer is increased.
上記目的を達成させるために1本発明は下記の骨子で構
成される。In order to achieve the above object, the present invention consists of the following main points.
(1)能動層には接合となるショット金属あるいはpn
接合を直接設ける。(1) The active layer has shot metal or pn
Provide a direct connection.
(2)ソース、ゲート間又はゲート、ドレイン間に少な
くとも能動層に用いている半導体よりも禁止帯幅が大き
い半導体層を設ける。(2) A semiconductor layer having a band gap larger than at least the semiconductor used for the active layer is provided between the source and the gate or between the gate and the drain.
(3)禁止帯幅の大きい半導体層は不純物濃度の小さい
ものを用いる。(3) A semiconductor layer with a large forbidden band width is used with a small impurity concentration.
以上の様に、ドレイン電圧印加による電界緩和は、禁止
帯幅の大きい半導体を用いて行うことにある。第2図は
本発明の素子構造である。従来の構造に能動層上に禁止
帯幅の大きく、キャリア濃度の小さい半導体8を設ける
に特徴がある。As described above, electric field relaxation by applying a drain voltage is achieved by using a semiconductor with a large forbidden band width. FIG. 2 shows the device structure of the present invention. The conventional structure is characterized in that a semiconductor 8 having a large forbidden band width and a small carrier concentration is provided on the active layer.
一般に半導体に於けるブレークダウン電圧Vaは実験的
に求められており、次式で示される。Generally, the breakdown voltage Va in semiconductors is experimentally determined and is expressed by the following equation.
VB′:60CEt/1.l)”(N[1/10”)−
”’すなわち、E、は半導体の禁止幅(エネルギーギャ
ップ)、Naは半導体内のキャリア濃度である。VB': 60CEt/1. l)"(N[1/10")-
''That is, E is the forbidden width (energy gap) of the semiconductor, and Na is the carrier concentration within the semiconductor.
したがって、ドレイン耐圧を大きくするには、ブレーク
ダウンする半導体層をE8の大きい、NBの小さいもの
を用いると良いことになる。Therefore, in order to increase the drain breakdown voltage, it is better to use a semiconductor layer that breaks down with a large E8 value and a small NB value.
一方、GaxA Q、−xAsはGaとAI2の組成を
変化させることによって、Ex を変えることができる
。On the other hand, in GaxA Q, -xAs, Ex can be changed by changing the composition of Ga and AI2.
A2の量が多くするとEgが大きくなる。例えばG a
0.7A n o、aA sの場合Et =1.79
8e VとなりGaAsの場合1.42eVであり、か
なりGaAQAsのExが大きくなる。Eg increases as the amount of A2 increases. For example, G a
For 0.7A no, aA s, Et = 1.79
8eV, which is 1.42eV in the case of GaAs, and the Ex of GaAQAs is considerably large.
以上のように、濃度の小さいGaA Q Asを用いる
とブレークダウン電圧を大きくとれる。電界効果トラン
ジスタに於けるドレイン耐圧の破壊はゲート・ドレイン
間の表面に電界が集中するために起る事がほとんどであ
る。そのため、この表面にアンドープGaA n As
を用いることにより上記理由から大幅にドレイン耐圧を
改善できる。As described above, the breakdown voltage can be increased by using GaA Q As with a low concentration. Destruction of the drain breakdown voltage in field effect transistors is almost always caused by the concentration of the electric field on the surface between the gate and drain. Therefore, undoped GaA n As is formed on this surface.
By using this, the drain breakdown voltage can be significantly improved for the above reasons.
以下、本実施例について説明する。This example will be described below.
実施例1
第3図(、)に示すような結晶構造をMBE(Mole
cur Beam Epitaxy)法で成長したO真
空度は10−”Torrで、成長条件として温度650
℃である。n型ドーパントとしてはSiを用いた。Example 1 A crystal structure as shown in FIG.
The O vacuum degree was 10-” Torr, and the growth condition was 650°C.
It is ℃. Si was used as the n-type dopant.
Siの量はSiの蒸気圧で制御した。基板としては半絶
縁性GaAs基板1(アンドープLEC法による結晶)
を用いた。面は(100)を用いた。バッファ層として
アンドープGaAs (S iとドープしない)層2を
0.5μmの厚さに成長した。能動層はSiドーパント
を入れたn型GaAs 3を厚さ0.12 μm の厚
さで濃度3×101°’ Ql −”に成長した。更に
その上にアンドープ型GaA Q As層8を成長した
。GaA Q As 8 の組成はG a 0.7A
Q o、aAsにして、厚さ0.15 μmにした。The amount of Si was controlled by the vapor pressure of Si. The substrate is a semi-insulating GaAs substrate 1 (crystal produced by undoped LEC method)
was used. The surface (100) was used. As a buffer layer, an undoped GaAs (not doped with Si) layer 2 was grown to a thickness of 0.5 μm. The active layer was made of n-type GaAs 3 doped with Si dopant and grown to a thickness of 0.12 μm with a concentration of 3×101°'Ql-''.Furthermore, an undoped GaA QAs layer 8 was grown on top of the active layer. .The composition of GaA Q As 8 is Ga 0.7A
Qo, aAs was used and the thickness was 0.15 μm.
これらの層は連続成長で形成した。These layers were formed by continuous growth.
その後、素子間アイソレーションとしてメサエッチング
を用いた。用いたエツチング液はNHaOH: HzO
z: Hz○系である。その時のエツチングマスクはホ
トレジスト[A z 1350 Jを用いた。After that, mesa etching was used for isolation between elements. The etching solution used was NHaOH: HzO.
z: Hz○ system. The etching mask used at that time was photoresist [Az 1350 J].
ホトレジスト膜除去後、第3図(b)のようにソース電
極4、ドレイン電極5となる領域のアンドープGaA
Q As B 層をHCQ系のエツチング液で除去した
。このとき、5iHaガスを用いたCVD(Chemi
cal Vapor Depo5ition )法で絶
縁膜3000人被着し、ホトレジ工程でソース・ドレイ
ン電極の領域のための穴を形成し、これらをマスクとし
て、GaA Q As厚8を選択エツチングしている。After removing the photoresist film, the undoped GaA in the regions that will become the source electrode 4 and drain electrode 5 as shown in FIG.
The Q As B layer was removed using an HCQ-based etching solution. At this time, CVD (Chemistry) using 5iHa gas was performed.
An insulating film of 3,000 layers is deposited using a cal vapor deposition method, holes for source/drain electrode regions are formed in a photoresist process, and using these as a mask, a GaAQAs thickness of 8 is selectively etched.
その後、オーミック金属となるAuG/eNi系を厚さ
3500人の厚さに被着し、リフトオフ法でパターンを
形成した。その後、完全オーミック化を図るため、還元
雰囲気でアロイ化した。Thereafter, an AuG/eNi-based ohmic metal was deposited to a thickness of 3,500 mm, and a pattern was formed using a lift-off method. Then, in order to make it completely ohmic, it was alloyed in a reducing atmosphere.
その後、第3図(c)のようにゲート′、i!極6を形
成した。ゲート電極6は上部のアンドープGaAQAs
8上に形成される。形成方法はホトリソ技術を用いて、
ゲートパターンを形成し、ホトレジスト膜をマスクとし
て絶縁膜をエツチングして、GaAα八s層へ露出させ
、ゲート金属AQを5000人被着した。ゲート金属の
パターン形成は通常用いられているソフトオフ法で形成
した。After that, as shown in FIG. 3(c), the gates', i! Pole 6 was formed. The gate electrode 6 is made of undoped GaAQAs on the upper part.
Formed on 8. The formation method uses photolithography technology,
A gate pattern was formed, and the insulating film was etched using the photoresist film as a mask to expose the GaAα 8s layer, and 5,000 gate metals AQ were deposited. The gate metal pattern was formed by a commonly used soft-off method.
その結果、ドレイン耐圧は18Vが得られた。As a result, a drain breakdown voltage of 18V was obtained.
実施例2
実施例1で説明した第3図(b)にあるソースドレイン
電極形成にアンドープGaAQAs8を選択的にエツチ
ングを行わずに、ホトレジスト膜をマスクとして、Si
イオンを注入し、アニールした後、オーミック金属を被
着し、オーミック電極4゜5を形成したe S iイオ
ン打込み条件は、150Kev、5XIQ”csl″″
8,120KaV、3X10”■−8の多重打込みを行
った。また、アニールは光による瞬間アニール法によっ
て行った。他の工程は実施例と同じである。Example 2 To form the source/drain electrodes shown in FIG. 3(b) described in Example 1, undoped GaAQAs 8 was not selectively etched, but Si was etched using a photoresist film as a mask.
After implanting ions and annealing, an ohmic metal was deposited and an ohmic electrode of 4°5 was formed.The ion implantation conditions were 150Kev, 5XIQ"csl""
Multiple implantation of 8,120 KaV and 3×10''-8 was performed. Also, annealing was performed by an instantaneous annealing method using light.Other steps were the same as in the example.
上記の様にして試作した電界効果トランジスタのドレイ
ン耐圧は20Vとなり、従来に比較し、2倍の改善が図
られた。The drain breakdown voltage of the field effect transistor prototyped as described above was 20V, which was twice the improvement compared to the conventional transistor.
本発明によれば、電界効果トランジスタのドレイン耐圧
を大巾に改善できる効果がある。特にアンドープGaA
Q As結晶はAQ組成を変化させることによって禁
IF帯幅を変化できる。その意味でGaAsに対してG
aA Q Asの組合せが最適である。According to the present invention, there is an effect that the drain breakdown voltage of a field effect transistor can be greatly improved. Especially undoped GaA
Q As crystal can change the forbidden IF band width by changing the AQ composition. In that sense, G for GaAs
The combination of aA Q As is optimal.
InPを能動層に用いた場合はInA Q As、 I
nGaAsに対してはInP又はInA Q Asが組
合せとして用いられる。When InP is used for the active layer, InA Q As, I
For nGaAs, InP or InA Q As are used in combination.
なお、本発明はチャンネル層となる能動層(実施例では
n−GaAs層3 )の直下に能動層と反対の不純物濃
度を持つ層を設けた電界効果トランジスタにも適用でき
る。The present invention can also be applied to a field effect transistor in which a layer having an impurity concentration opposite to that of the active layer is provided directly below the active layer (n-GaAs layer 3 in the embodiment) serving as a channel layer.
第1図は従来の素子構造断面図、第2図は本発明の素子
構造断面図、第3図は素子作成工程に於ける断面図であ
る。
1・・・半導体基板、2・・・バッファ層、3・・・能
動層(n GaAs層)、4・・・ソース電極、5・
・・ドレイン電極、6・・・ゲート電極、7・・・オー
ミック用高濃度半導体層(n+ −GaAs層)、8・
・・禁止帯幅の広い半導体層(アンドープGaA Q
As層)、9・・・絶縁膜(S iOz) m
芽1凹
(久)
第2図
茅3囚
(a)FIG. 1 is a sectional view of a conventional device structure, FIG. 2 is a sectional view of the device structure of the present invention, and FIG. 3 is a sectional view of the device fabrication process. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Buffer layer, 3... Active layer (n GaAs layer), 4... Source electrode, 5...
... Drain electrode, 6... Gate electrode, 7... High concentration semiconductor layer for ohmic use (n+ -GaAs layer), 8.
・・Semiconductor layer with wide forbidden band width (undoped GaA Q
As layer), 9... Insulating film (SiOz) m Bud 1 concave (long) Figure 2 Chi 3 concave (a)
Claims (1)
するアンドープ型または低濃度半導体層を少なくともゲ
ート・ドレイン間に設け、かつ、ゲート電極を能動層上
に設けている事を特徴とする電界効果トランジスタ。 2、特許請求の範囲第1項において、能動層としてGa
Asを、アンドープ型または低濃度半導体層としてGa
AlAsを用いることを特徴とする電界効果トランジス
タ。 3、特許請求の範囲第1項において、ソース・ドレイン
電極は、アンドープ型または低濃度半導体層に不純物を
導入した領域上に形成されていることを特徴とする電界
効果トランジスタ。[Claims] 1. An undoped or low concentration semiconductor layer having a wider energy gap than the active layer is provided on the active layer at least between the gate and drain, and a gate electrode is provided on the active layer. Characteristics of field effect transistors. 2. In claim 1, Ga is used as the active layer.
As is used as an undoped or low concentration semiconductor layer.
A field effect transistor characterized by using AlAs. 3. A field effect transistor according to claim 1, wherein the source/drain electrodes are formed on a region in which an impurity is introduced into an undoped or low concentration semiconductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25474185A JPS62115781A (en) | 1985-11-15 | 1985-11-15 | Field-effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25474185A JPS62115781A (en) | 1985-11-15 | 1985-11-15 | Field-effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62115781A true JPS62115781A (en) | 1987-05-27 |
Family
ID=17269218
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25474185A Pending JPS62115781A (en) | 1985-11-15 | 1985-11-15 | Field-effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62115781A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5777363A (en) * | 1993-11-29 | 1998-07-07 | Texas Instruments Incorporated | Semiconductor device with composite drift region |
JP2008160996A (en) * | 2006-12-25 | 2008-07-10 | Mitsubishi Electric Corp | Power supply unit |
US11181562B2 (en) | 2017-07-31 | 2021-11-23 | Rohm Co., Ltd. | Zero-crossing detection circuit |
US11733275B2 (en) | 2017-07-31 | 2023-08-22 | Rohm Co., Ltd. | Zero-crossing detection circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5768073A (en) * | 1980-10-14 | 1982-04-26 | Nec Corp | Field effect transistor |
-
1985
- 1985-11-15 JP JP25474185A patent/JPS62115781A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5768073A (en) * | 1980-10-14 | 1982-04-26 | Nec Corp | Field effect transistor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5777363A (en) * | 1993-11-29 | 1998-07-07 | Texas Instruments Incorporated | Semiconductor device with composite drift region |
JP2008160996A (en) * | 2006-12-25 | 2008-07-10 | Mitsubishi Electric Corp | Power supply unit |
US11181562B2 (en) | 2017-07-31 | 2021-11-23 | Rohm Co., Ltd. | Zero-crossing detection circuit |
US11733275B2 (en) | 2017-07-31 | 2023-08-22 | Rohm Co., Ltd. | Zero-crossing detection circuit |
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