JPS62281359A - Manufacture of ceramic wiring substrate - Google Patents
Manufacture of ceramic wiring substrateInfo
- Publication number
- JPS62281359A JPS62281359A JP61125253A JP12525386A JPS62281359A JP S62281359 A JPS62281359 A JP S62281359A JP 61125253 A JP61125253 A JP 61125253A JP 12525386 A JP12525386 A JP 12525386A JP S62281359 A JPS62281359 A JP S62281359A
- Authority
- JP
- Japan
- Prior art keywords
- holes
- metal layer
- ceramic
- hole
- wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 14
- 238000007747 plating Methods 0.000 claims description 12
- 239000003462 bioceramic Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010304 firing Methods 0.000 claims description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 18
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000010828 elution Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 9
- 238000005219 brazing Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000004080 punching Methods 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体集積回路素子（ＩＣ）を収納するセラミ
ックパッケージ等に用いられるセラミック配線基返の製
造法に関し、より詳細には広面積の生セラミ・ツク体を
出発材料として小面積のセラミック配線基板を可能な限
り多数個集約的に、かつ生産性良く得る方法に関するも
のである。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a ceramic wiring board used in a ceramic package for housing a semiconductor integrated circuit element (IC). Specifically, the present invention relates to a method for obtaining as many small-area ceramic wiring boards as possible in a concentrated manner and with high productivity using a wide-area raw ceramic block as a starting material.
従来、半導体素子、特に半導体集積回路素子を収納する
ためのセラミックパンケージは第３図に示すように、ア
ルミナセラミック等の電気絶縁材料から成り、その略中
央部に半導体素子を取着するためのキャビティＡ及び該
キャビティＡ周辺より側面を介し底面にまで導出された
タングステン（Ｗ）、モリブデン（Ｍｏ）等の金属粉末
から成る金属層１２を有するセラミック配線基板１１と
蓋体１３とから構成されており、その内部に半導体素子
１４が収納され、気密封止されて半導体装置となる。Conventionally, as shown in Fig. 3, a ceramic pancage for housing semiconductor devices, particularly semiconductor integrated circuit devices, is made of an electrically insulating material such as alumina ceramic, and has a hole approximately in the center for mounting the semiconductor device. It is composed of a ceramic wiring board 11 having a cavity A and a metal layer 12 made of metal powder such as tungsten (W) or molybdenum (Mo) led out from the periphery of the cavity A through the side surface to the bottom surface, and a lid body 13. The semiconductor element 14 is housed inside and hermetically sealed to form a semiconductor device.
尚、前記セラミックパッケージは金属層１２を外部配線
基板にロウ付けする際、そのロウ付は強度を上げるため
に、また金属層１２が酸化腐食するのを防止するために
、該金属］’ｉ１２の露出面にはロウ材と接合性が良く
、耐蝕性に優れた金（ＡＵ）等のメッキ層１５が層着さ
れている。In addition, when the ceramic package is brazed with the metal layer 12 to the external wiring board, the soldering is performed using the metal [i12] in order to increase the strength and to prevent the metal layer 12 from being oxidized and corroded. A plating layer 15 made of gold (AU) or the like, which has good bonding properties with the brazing material and excellent corrosion resistance, is deposited on the exposed surface.
かかる従来のセラミックパッケージはその配線基板１１
が通常、以下に述べる方法によって製作される。Such a conventional ceramic package has its wiring board 11
is usually manufactured by the method described below.
即ち、第４図に示すように、まず貫通孔２４によって複
数の区画に区分された３枚の広面積の未焼成セラミック
シート （グリーンシート）２１．２２．２３を準備し
、それぞれのシート２１．２２．２３の表面及び貫通孔
２４内壁全面に金属ペースト２５を印刷塗布する。次に
これらシート２１．２２．２３を積層し、生セラミック
体２６を得るとともに高温で焼成し、焼成セラミック体
及び金属層１２を形成する。そして最後に金属層１２の
露出面に′ツキによりメッキ層１５を層着させるととも
に貫通孔２４の配線による区分線に沿って切断分離し、
これによって多数個のセラミンク配線基板１１が一度に
製作される。That is, as shown in FIG. 4, first, three wide-area unfired ceramic sheets (green sheets) 21, 22, and 23 divided into a plurality of sections by through holes 24 are prepared, and each sheet 21. The metal paste 25 is printed and coated on the surfaces of 22 and 23 and the entire inner wall of the through hole 24. Next, these sheets 21, 22, 23 are laminated to obtain a raw ceramic body 26 and fired at a high temperature to form a fired ceramic body and metal layer 12. Finally, the plating layer 15 is deposited on the exposed surface of the metal layer 12 by plating, and the plating layer 15 is cut and separated along the dividing line formed by the wiring in the through hole 24.
As a result, a large number of ceramic wiring boards 11 are manufactured at once.
しかし乍ら、この従来のセラミック配線基板の製造法に
よれば、広面積の焼成セラミック体を貫通孔の配列によ
る区分線に沿って切断分離し、小面積の個々のセラミッ
ク配線基板を得た場合、第５図に示すように貫通孔内壁
に形成された金属層１２が切断分離され、その切断分離
面で露出することとなり、そのためこの露出部に大気中
に含まれる水分が付着すると、該水分が金属層１２及び
メッキ層１５に接触して電解質として働き金属層１２と
メッキ層１５との間に両金属のエネルギー準位の相違か
ら電流が流れる電池作用を生じてエネルギー準位が低い
金属層１２が徐々に溶出し、ついには金属層１２が断線
してしまうという欠点を有していた。However, according to this conventional manufacturing method for ceramic wiring boards, when a large-area fired ceramic body is cut and separated along dividing lines formed by an array of through holes, individual ceramic wiring boards with a small area are obtained. As shown in FIG. 5, the metal layer 12 formed on the inner wall of the through hole is cut and separated, and is exposed at the cut and separated surface. Therefore, if moisture contained in the atmosphere adheres to this exposed portion, the moisture will be removed. contacts the metal layer 12 and the plating layer 15 and acts as an electrolyte, causing a battery effect in which current flows between the metal layer 12 and the plating layer 15 due to the difference in the energy levels of both metals, thereby forming a metal layer with a low energy level. 12 is gradually eluted, and the metal layer 12 is eventually broken.
本発明は上記欠点に鑑み案出されたもので、その目的は
広面積の焼成セラミック体を貫ｉｍ孔の配列による区分
線に沿って切断分離し、小面積の個々のセラミック配線
基板を得る際、貫通孔内壁に形成された金属層が切断分
離されて露出するのを皆無となし、金属層が大気中に含
まれる水分の付着により生じる電池作用によって溶出、
断線するのを有効に防止することができるセラミック配
線基板の製造法を提供することにある。The present invention was devised in view of the above-mentioned drawbacks, and its purpose is to cut and separate a fired ceramic body having a large area along a dividing line formed by an array of through-holes to obtain individual ceramic wiring boards having a small area. , the metal layer formed on the inner wall of the through hole is completely prevented from being cut and separated, and the metal layer is eluted by the battery action caused by the adhesion of moisture contained in the atmosphere.
An object of the present invention is to provide a method for manufacturing a ceramic wiring board that can effectively prevent wire breakage.
ｃ問題点を解決するための手段〕
本発明のセラミック配線基板の製造法は、広面積の生セ
ラミック体に、咳生セラミック体を複数の区画に区分す
る如く多数の貫通孔を配列形成する工程と、
前記生セラミック体の少なくとも貫通孔内壁に金属ペー
ストを塗布する工程と、
前記貫通孔内壁に、該貫通孔の配列による区分線に沿っ
て打抜き凹部を形成し、貫通孔内壁に塗布した金属ペー
ストのうち区分線上のものを除去する工程と、
前記金属ペーストが塗布された生セラミンク体を焼成し
、金属層を有する焼成セラミック体を得るとともに金属
層の露出面にメッキ層を層着させる工程と、
前記焼成セラミック体を区分線に沿って切断し、各配線
基板毎に分離する工程
とより成ることを特徴とするものである。c. Means for Solving Problems] The method for manufacturing a ceramic wiring board of the present invention includes the step of forming a large number of through holes in a wide-area bioceramic body in an array so as to divide the bioceramic body into a plurality of sections. a step of applying a metal paste to at least the inner wall of the through hole of the bioceramic body; forming a punched recess on the inner wall of the through hole along a dividing line formed by the arrangement of the through hole; and a step of applying a metal paste to the inner wall of the through hole. a step of removing the part of the paste on the dividing line; and a step of firing the raw ceramic body coated with the metal paste to obtain a fired ceramic body having a metal layer and depositing a plating layer on the exposed surface of the metal layer. The method is characterized by comprising the steps of: cutting the fired ceramic body along dividing lines to separate each wiring board.
次に本発明のセラミンク配線基板の製造法を第１図及び
第２図に示す実施例に基づき詳細に説明する。Next, a method for manufacturing a ceramic wiring board according to the present invention will be explained in detail based on the embodiment shown in FIGS. 1 and 2.
第１図（ａ）は本発明のセラミック配線基板の製造法を
セラミックパッケージに使用されるセラミック配線基板
に適用した場合の例を示す分解斜視図であり、全体とし
て１で示す生セラミック体は第１、第２及び第３の３枚
の未焼成セラミックシー）１ａ、１ｂ、ＩＣから構成さ
れている。FIG. 1(a) is an exploded perspective view showing an example in which the method for manufacturing a ceramic wiring board of the present invention is applied to a ceramic wiring board used in a ceramic package. It is composed of three unfired ceramic sheets (1, 2, and 3) 1a, 1b, and IC.
前記未焼成セラミックシート１ａ、１ｂ、ＩＣはアルミ
ナ（ＡｌｚＯｉ） 、シリカ（ＳｉＯ□）等のセラミッ
ク原料粉末に適当な溶剤、溶媒を添加混合して泥漿物を
作り、これを従来周知のドクターブレード法等によりシ
ート状と成すことによて形成される。The unfired ceramic sheets 1a, 1b and IC are made by adding and mixing a suitable solvent to ceramic raw material powder such as alumina (AlzOi) or silica (SiO□) to form a slurry, which is then processed by the conventionally well-known doctor blade method. It is formed by forming it into a sheet shape.
前記各未焼成セラミックシート１ａ、ｌｂ、ＩＣには、
該シートｌａ、ｌｂ、ＩＣを複数の区画に区分する如く
多数の貫通孔２ａ、２ｂ、２Ｃが配列形成されており、
貫通孔２ａ、２ｂ、２Ｃは従来周知の打抜き加工法によ
って形成される。この貫通孔２ａ、２ｂ、２Ｃは広面積
の未焼成セラミックシートｌａ、１ｂ、ＩＣを所望する
セラミック配線基板に対応した形状の複数の区画に区分
するとともに後述するリード用金属層を引き廻す際の通
路として使用される。Each of the unfired ceramic sheets 1a, lb, and IC includes:
A large number of through holes 2a, 2b, 2C are arranged and formed to divide the sheets la, lb, and IC into a plurality of sections,
The through holes 2a, 2b, and 2C are formed by a conventionally known punching method. These through holes 2a, 2b, and 2C are used to divide the wide-area unfired ceramic sheets la, 1b, and IC into a plurality of sections each having a shape corresponding to a desired ceramic wiring board, and also to be used for routing metal layers for leads, which will be described later. used as a passageway.
また前記第１及び第２の未焼成セラミックシート１ａ、
１ｂにはそれぞれ各貫通孔’ｌａ、’ｌｂの配列による
区分’！ｔｔｉ Ｂによって囲まれた各領域の略中央部
に半導体素子を収納するだめのキャビティーを形成する
空所を存しており、該空所も従来周知の打抜き加工法に
よって形成される。Further, the first and second unfired ceramic sheets 1a,
In 1b, each through hole is divided by arrangement of 'la' and 'lb'! At approximately the center of each area surrounded by tti B, there is a cavity for forming a cavity for accommodating a semiconductor element, and this cavity is also formed by a conventionally well-known punching method.
前記第２の未焼成セラミックシートｌｂにはその上面か
ら貫通孔２ｂの内壁にかけてリード用金属ｆｆｉ ４
ａが印刷塗布されており、また第３の未焼成セラミック
シー１−ＩＣ上にはその上面の略中央部に半導体素子を
取着するためのダイアタッチ用金属層５が、貫通孔２Ｃ
の内壁から下面にかけてリード用金属層４ｂがそれぞれ
印刷塗布されている（第１図（ｂ）及び第２図参照）。The second unfired ceramic sheet lb has lead metal ffi 4 from its upper surface to the inner wall of the through hole 2b.
A is printed and coated on the third unfired ceramic sheet 1-IC, and a die attach metal layer 5 for attaching a semiconductor element is formed approximately in the center of the upper surface of the third green ceramic sheet 1-IC through the through hole 2C.
A lead metal layer 4b is printed and coated from the inner wall to the lower surface of each (see FIG. 1(b) and FIG. 2).
このリード用金属層４ａ、４ｂ及びダイアチッチ用金属
層５はタングステン（Ｗ）、モリブデン（ＭＯ）等の高
融点金属粉末に適当な溶剤、溶媒を添加混合し、ペース
ト状となした金属ペーストを従来周知のスクリーン印刷
法を採用することによって未焼成セラミックシート１ｂ
、ＩＣのそれぞれに印刷塗布される。The metal layers 4a and 4b for leads and the metal layer 5 for die-cutting are conventionally made using a metal paste made by adding and mixing a suitable solvent to high melting point metal powder such as tungsten (W) or molybdenum (MO) to form a paste. By adopting the well-known screen printing method, the unfired ceramic sheet 1b
, are printed and coated on each of the ICs.
前記３枚の未焼成セラミックシート１ａ、１ｂ。The three unfired ceramic sheets 1a and 1b.
１ｃは各貫通孔２ａ、２ｂ、２Ｃの位置を正確に合わせ
て順位積層され、約１５０°Ｃに加熱したホットプレス
機によって熱圧着されて生セラミック体１が作成される
。1c are laminated in order with the positions of the through holes 2a, 2b, and 2C accurately aligned, and the raw ceramic body 1 is produced by thermocompression bonding using a hot press machine heated to about 150°C.
前記生セラミック体１は次に各貫通孔内壁の一部が打抜
かれて凹部３が形成され、貫通孔内壁に塗布したリード
用金属層４ａ、４ｂの一部が除去される。この打抜き凹
部３が形成される位置は貫通孔の配列による区分線已に
沿った位置に形成され、これによって後述する焼成セラ
ミック体を区分線Ｂに沿って切断し、各配線基板毎に分
離する際にはその切断分離部にリード用金属層４ａ、４
ｂは存在しないこととなる。Next, a part of the inner wall of each through hole of the bioceramic body 1 is punched out to form a recess 3, and a part of the lead metal layers 4a and 4b coated on the inner wall of the through hole is removed. The punched recesses 3 are formed along the dividing line by the arrangement of the through holes, so that the fired ceramic body, which will be described later, is cut along the dividing line B and separated into each wiring board. In this case, the lead metal layers 4a, 4 are placed at the cut and separated parts.
b does not exist.
前記打抜き四部３は未焼成セラミックシート１ａ、ｌｂ
、ｌｃに貫通孔２ａ、２ｂ、２Ｃを形成する場合と同様
な打抜き加工法によって形成される。The four punched parts 3 are unfired ceramic sheets 1a, lb.
, lc by the same punching method as in the case of forming the through holes 2a, 2b, 2C.
次に、前記生セラミック体１は還元雰囲気中（Ｈｚ−Ｎ
ｚガス中）、約１４００〜１６００℃の温度で焼成され
、生セラミック体１とリード用金属層４ａ、４ｂ及びダ
イアタッチ用金属層５とを焼結一体化させ、焼成セラミ
ック体１゛、リード金属層４゛及びダイアタッチ金属層
５°が形成される。Next, the bioceramic body 1 is placed in a reducing atmosphere (Hz-N
z gas) at a temperature of approximately 1,400 to 1,600°C, the raw ceramic body 1, the lead metal layers 4a, 4b, and the die attach metal layer 5 are sintered and integrated, and the fired ceramic body 1' and the lead are fired. A metal layer 4' and a die attach metal layer 5' are formed.
そして次に前記リード金属層４“及びダイアタッチ金属
層５° を有する焼成セラミック体１゛ は金メツキ浴
中に浸漬されるとともに一定の電界が印加され（電解メ
ンキ法）、リード金属層４゛及びダイアタッチ金属層５
°の露出面に金（Ａｕ）から成るメッキ層が層着される
。このメッキ層はリード金属層４゛及びダイアタッチ金
属層５゛が酸化腐食するのを防止する作用を為すととも
にリード金属層４゛ と外部配線基板とをロウ付けする
際、あるいはダイアタッチ金属層５゛ と半導体素子と
をロウ付けする際、リード金属層４゛及びダイアタッチ
金属層５゛ とロウ材との濡れ性を改善して接合強度を
上げる作用を為す。Next, the fired ceramic body 1'' having the lead metal layer 4'' and the die attach metal layer 5'' is immersed in a gold plating bath and a constant electric field is applied (electrolytic coating method). and die attach metal layer 5
A plating layer made of gold (Au) is deposited on the exposed surface of the plate. This plating layer has the function of preventing oxidation corrosion of the lead metal layer 4'' and the die attach metal layer 5'', and is also used when brazing the lead metal layer 4'' and an external wiring board, or when the die attach metal layer 5'' is being brazed. When brazing the lead metal layer 4 and the semiconductor element, it improves the wettability between the lead metal layer 4 and the die attach metal layer 5 and the brazing material, thereby increasing the bonding strength.
尚、前記リード金属層４゛及びダイアタッチ金属層５°
の露出面に層着されるメッキ層は電解メッキ法に限る
ことなく無電解メッキ法によっても層着することができ
る。Note that the lead metal layer 4'' and the die attach metal layer 5''
The plating layer to be deposited on the exposed surface is not limited to electrolytic plating, but can also be deposited by electroless plating.
そして最後に、前記焼成セラミック体１゛は貫通孔の配
列による区分線已に沿って切断分離され、これによって
個々のセラミック配線基板が製作される。この場合、貫
通孔内壁に設けたリード金属層４゛は該貫通孔内壁に形
成した打抜き凹部によって区分線Ｂの線上には全く存在
しないことから区分線Ｂに沿って切断分離したとしても
その切断分離面にはリード金属Ｎ４°が切断されて露出
することは−切なく、そのため大気中に含まれる水分が
リード金属層に付着し、該金属層を溶出、断線させるこ
ともない。Finally, the fired ceramic body 1' is cut and separated along the dividing lines defined by the arrangement of the through holes, thereby producing individual ceramic wiring boards. In this case, the lead metal layer 4' provided on the inner wall of the through hole does not exist at all on the dividing line B due to the punched recess formed on the inner wall of the through hole, so even if it is cut and separated along the dividing line B, the cut It is unfortunate that the lead metal N4° is cut and exposed on the separation surface, and therefore moisture contained in the atmosphere does not adhere to the lead metal layer and cause the metal layer to elute and break.
かくして、本発明のセラミック配線基板の製造法によれ
ば、生セラミック体を複数の区画に区分する貫通孔の内
壁に塗布された金属ペーストのうち貫通孔の配列による
区分線上に位置するものが貫通孔内壁に設ける打抜き凹
部によって除去されることから、焼成セラミック体を区
分線に沿って切断し、各セラミック配線基板毎に分離し
たとしても貫通孔内壁に形成された金属層は切断されて
露出することは一切なく、金属層に大気中に含まれる水
分が付着し電池作用を生じて該金属層が溶出、断線する
のを有効に防止することが可能となる。Thus, according to the method for manufacturing a ceramic wiring board of the present invention, among the metal pastes applied to the inner walls of the through holes that divide the bioceramic body into a plurality of sections, the metal paste located on the dividing line formed by the arrangement of the through holes penetrates. Since the metal layer formed on the inner wall of the through hole is removed by the punched recess provided on the inner wall of the hole, even if the fired ceramic body is cut along the dividing line and separated into each ceramic wiring board, the metal layer formed on the inner wall of the through hole will be cut and exposed. There is nothing wrong with this, and it is possible to effectively prevent moisture contained in the atmosphere from adhering to the metal layer and causing a battery effect, causing the metal layer to elute and break.
第１図（ａ）は本発明のセラミック配線基板の製造法を
セラミックパッケージに適用した場合の例を示す部分分
解斜視図、第１図（ｂ）は第１図（ａ）の部分断面図、
第２図は第１図（ａ）、（ｂ）の貫通孔の部分を説明す
るための部分斜視図、第３図は従来のセラミックパッケ
ージの断面図、第４図は第３図のセラミックパッケージ
の製造法を説明するための部分断面図、第５図は第３図
の一部を示す斜視図である。
１：生セラミック体
１” ：焼成セラミック体
２ａ、２ｂ、２ｃ：貫通孔
３：打抜き凹部
４ａ、４ｂ：リード用金属層
４° ：リード金属層
Ｂ；区分線FIG. 1(a) is a partially exploded perspective view showing an example in which the method for manufacturing a ceramic wiring board of the present invention is applied to a ceramic package, FIG. 1(b) is a partial cross-sectional view of FIG. 1(a),
Fig. 2 is a partial perspective view for explaining the through hole portion of Figs. 1(a) and (b), Fig. 3 is a sectional view of a conventional ceramic package, and Fig. 4 is the ceramic package of Fig. 3. FIG. 5 is a partial sectional view for explaining the manufacturing method of FIG. 3, and FIG. 5 is a perspective view showing a part of FIG. 1: Raw ceramic body 1": Fired ceramic body 2a, 2b, 2c: Through hole 3: Punching recesses 4a, 4b: Lead metal layer 4°: Lead metal layer B; Partition line
Claims (1)
区画に区分する如く多数の貫通孔を配列形成する工程と
、 前記生セラミック体の少なくとも貫通孔内壁に金属ペー
ストを塗布する工程と、 前記貫通孔内壁に、該貫通孔の配列による区分線に沿っ
て打抜き凹部を形成し、貫通孔内壁に塗布した金属ペー
ストのうち区分線上のものを除去する工程と、 前記金属ペーストが塗布された生セラミック体を焼成し
、金属層を有する焼成セラミック体を得るとともに金属
層の露出面にメッキ層を層着させる工程と、 前記焼成セラミック体を区分線に沿って切断し、各配線
基板毎に分離する工程とより成るセラミック配線基板の
製造法。[Claims] A step of forming a large number of through holes in a wide-area bioceramic body so as to divide the bioceramic body into a plurality of sections, and applying a metal paste to at least the inner wall of the through holes of the bioceramic body. forming a punched recess on the inner wall of the through hole along a dividing line formed by the arrangement of the through holes, and removing a portion of the metal paste applied to the inner wall of the through hole on the dividing line; firing the raw ceramic body coated with the paste to obtain a fired ceramic body having a metal layer and depositing a plating layer on the exposed surface of the metal layer; cutting the fired ceramic body along a dividing line; A method for manufacturing a ceramic wiring board, which comprises a step of separating each wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12525386A JPH0785496B2 (en) | 1986-05-29 | 1986-05-29 | Ceramic wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12525386A JPH0785496B2 (en) | 1986-05-29 | 1986-05-29 | Ceramic wiring board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62281359A true JPS62281359A (en) | 1987-12-07 |
| JPH0785496B2 JPH0785496B2 (en) | 1995-09-13 |
Family
ID=14905534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12525386A Expired - Lifetime JPH0785496B2 (en) | 1986-05-29 | 1986-05-29 | Ceramic wiring board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0785496B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4651152B2 (en) * | 2000-03-27 | 2011-03-16 | 京セラ株式会社 | Multi-cavity ceramic wiring board |
| JP2011228412A (en) * | 2010-04-19 | 2011-11-10 | Panasonic Corp | Resin seal type semiconductor package and method for manufacturing the same |
| JP2014237296A (en) * | 2013-06-10 | 2014-12-18 | セイコーエプソン株式会社 | Method of producing functional unit, functional mother substrate and functional unit |
| CN113725190A (en) * | 2021-07-27 | 2021-11-30 | 南瑞联研半导体有限责任公司 | Copper-clad ceramic lining plate structure of power device and packaging method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51103262A (en) * | 1975-03-07 | 1976-09-11 | Hitachi Ltd | SERAMITSUKUPATSUKEEJINOSEIZOHO |
| JPS58137237A (en) * | 1982-02-08 | 1983-08-15 | Kyocera Corp | Preparation of ceramic substrate for semiconductor package |
-
1986
- 1986-05-29 JP JP12525386A patent/JPH0785496B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51103262A (en) * | 1975-03-07 | 1976-09-11 | Hitachi Ltd | SERAMITSUKUPATSUKEEJINOSEIZOHO |
| JPS58137237A (en) * | 1982-02-08 | 1983-08-15 | Kyocera Corp | Preparation of ceramic substrate for semiconductor package |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4651152B2 (en) * | 2000-03-27 | 2011-03-16 | 京セラ株式会社 | Multi-cavity ceramic wiring board |
| JP2011228412A (en) * | 2010-04-19 | 2011-11-10 | Panasonic Corp | Resin seal type semiconductor package and method for manufacturing the same |
| JP2014237296A (en) * | 2013-06-10 | 2014-12-18 | セイコーエプソン株式会社 | Method of producing functional unit, functional mother substrate and functional unit |
| CN113725190A (en) * | 2021-07-27 | 2021-11-30 | 南瑞联研半导体有限责任公司 | Copper-clad ceramic lining plate structure of power device and packaging method thereof |
| CN113725190B (en) * | 2021-07-27 | 2024-03-29 | 南瑞联研半导体有限责任公司 | Copper-clad ceramic lining plate structure of power device and packaging method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0785496B2 (en) | 1995-09-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |