JPS62277790A - Manufacture of wiring board - Google Patents
Manufacture of wiring boardInfo
- Publication number
- JPS62277790A JPS62277790A JP12145086A JP12145086A JPS62277790A JP S62277790 A JPS62277790 A JP S62277790A JP 12145086 A JP12145086 A JP 12145086A JP 12145086 A JP12145086 A JP 12145086A JP S62277790 A JPS62277790 A JP S62277790A
- Authority
- JP
- Japan
- Prior art keywords
- resist pattern
- wiring board
- copper
- pattern
- stainless steel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims description 15
- 239000002313 adhesive film Substances 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910001220 stainless steel Inorganic materials 0.000 description 9
- 239000010935 stainless steel Substances 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 1
- 235000009984 Pterocarpus indicus Nutrition 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 241000533793 Tipuana tipu Species 0.000 description 1
- BZHJMEDXRYGGRV-UHFFFAOYSA-N Vinyl chloride Chemical compound ClC=C BZHJMEDXRYGGRV-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- BGTFCAQCKWKTRL-YDEUACAXSA-N chembl1095986 Chemical compound C1[C@@H](N)[C@@H](O)[C@H](C)O[C@H]1O[C@@H]([C@H]1C(N[C@H](C2=CC(O)=CC(O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O)=C2C=2C(O)=CC=C(C=2)[C@@H](NC(=O)[C@@H]2NC(=O)[C@@H]3C=4C=C(C(=C(O)C=4)C)OC=4C(O)=CC=C(C=4)[C@@H](N)C(=O)N[C@@H](C(=O)N3)[C@H](O)C=3C=CC(O4)=CC=3)C(=O)N1)C(O)=O)=O)C(C=C1)=CC=C1OC1=C(O[C@@H]3[C@H]([C@H](O)[C@@H](O)[C@H](CO[C@@H]5[C@H]([C@@H](O)[C@H](O)[C@@H](C)O5)O)O3)O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O[C@@H]3[C@H]([C@H](O)[C@@H](CO)O3)O)C4=CC2=C1 BGTFCAQCKWKTRL-YDEUACAXSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 五 発明の詳細な説明 （産業上の利用分野） 本発明は配線板の製造１５法に関する。[Detailed description of the invention] V. Detailed description of the invention (Industrial application field) The present invention relates to 15 methods for manufacturing wiring boards.
（従来の技術〉
配線板の線巾、線間隔Ｑ工ＬＳＩの高集積化に伴います
ます細か（なっている。こうした高密度化に対処する微
細パターン形成法として、銅張り積層板または銅箔付き
フィルムの不用部分全エツチングして回路パターンを形
成する方法（ナフトラクト法）に代り、絶縁基材表面の
必要部分に無電解銅めっきなどにより回路形成する方法
（アディティブ法）成るい（工５へ９μｍの鋼箔を用い
た銅張り積層板または銅箔付ぎフィルムをベースに必要
部分にめっきした後ペースの薄い銅箔をクイックエツチ
ングする方法（セミアディティブ法〕がある。(Conventional technology) The line width and line spacing of wiring boards are becoming increasingly finer as LSIs become more highly integrated.Currently using copper-clad laminates or copper foil Instead of the method of forming a circuit pattern by etching all the unnecessary parts of the attached film (naft tract method), there is a method of forming a circuit on the necessary parts of the surface of the insulating base material by electroless copper plating (additive method). There is a method (semi-additive method) in which a copper-clad laminate using 9 μm steel foil or a film with copper foil is plated on the necessary parts and then a thin copper foil is quickly etched.
（発明が解決しようとする問題点）
アディティブ法においては、現状では絶縁基材表面の粗
度が大きく、まＴこ無電解銅めっき液の自己分解によっ
て銅粒子が異状析出する銅フリ現象があり、ナフトラク
ト法以上の微細パターン形５５Ｃは容易でない、ｌまた
、セミアディティブ法におい又も、銅張り積層板や銅２
６付きフィルムの製造工程において発生する銅箔のへこ
み及び傷などのため、断線あるいはショートが発生し易
い。さらに何れの方法においても、エツチングまたはめ
っきレジストパターン形成の工程において、フォトマス
クの欠陥や露光時のゴミの混入などに帰因する焼き付は
不良の問題が深刻である。しかもなお、毎回レジストパ
ターン形成を行う必要がある。(Problems to be Solved by the Invention) In the additive method, the roughness of the surface of the insulating base material is currently large, and there is also a copper frill phenomenon in which copper particles are deposited abnormally due to self-decomposition of the electroless copper plating solution. , it is not easy to create a finer pattern 55C than the naphtract method. Also, in the semi-additive method, copper-clad laminates and copper 2
Due to dents and scratches on the copper foil that occur during the manufacturing process of the film with 6, wire breakage or short circuits are likely to occur. Furthermore, in any of the methods, there is a serious problem of printing failures caused by defects in the photomask or contamination of dust during exposure in the process of etching or plating resist pattern formation. Moreover, it is still necessary to form a resist pattern each time.
（問題を解決するための手段） 本発明は次の工程による配線板の製造方法である。(Means to solve the problem) The present invention is a method for manufacturing a wiring board using the following steps.
囚 導電性を有する保持体面に絶縁性を有するレジスト
パターンを形成する。An insulating resist pattern is formed on the conductive holder surface.
ＩＢＩ 加熱圧着すると厚さ方向にのみ４電注が得ら
れる接層フィルムを、前記レジストパターンを形成した
面の全面に加熱圧着する。IBI A contact film, which can be bonded by heat and pressure to obtain a four-voltage bond only in the thickness direction, is bonded by heat and pressure to the entire surface on which the resist pattern is formed.
（Ｃ） ＦｔｆＪ記接着フィルム上の前記レジストパ
ターン以外の部分に、電気めっきによって４電性パター
ンを形成する。(C) A tetraelectric pattern is formed by electroplating on a portion of the FtfJ adhesive film other than the resist pattern.
ｐ） 前記接着フィルムを前記保持体より剥離する。p) Peeling off the adhesive film from the holder.
第１図ａ〜ｅは、本発明の実施例を示すが、以下具体的
ＫＭｌ明する。厚さ１ｍｍのステンレス板１を用意する
。この他用いることができる金属板をニステンレス板上
に電気めっきで厚さ５０〜８０μｍ程度の銅めっきＮを
設けたもの、成るいは４＊性及び加工性にＩ＆ｎ １こ
厚さ１ｍｍ程度のアルミニウム板などである。ステンレ
ス板１０表面をサンドペーパーで研摩後、フォトレジス
ト（リストンＴ−１２０６）ｋロールラミネータによっ
てラミネートする。次にフォトマスクを当℃で紫外線を
照射した後、境像によって所望する部分にレジストパタ
ーン２を設け、次いで塩化第二鉄（ＦｅＣ１３）俗液（
２８〜４２１謎％〕で前記レジストパターン以外の部分
をエツチングして凹部３を設け、しかる後に別記レジス
トパターン２を塩化メチレンで剥離した。FIGS. 1a to 1e show embodiments of the present invention, and specific details will be given below. A stainless steel plate 1 with a thickness of 1 mm is prepared. Other metal plates that can be used include copper plating N with a thickness of about 50 to 80 μm electroplated on a stainless steel plate, or a metal plate with a thickness of about 1 mm. Such as aluminum plate. After polishing the surface of the stainless steel plate 10 with sandpaper, it is laminated with photoresist (Riston T-1206) using a k-roll laminator. Next, after irradiating the photomask with ultraviolet rays at the same temperature, a resist pattern 2 is provided in the desired area according to the boundary image, and then a ferric chloride (FeC13) common solution (
28 to 421 percent)] to form recesses 3, and then the resist pattern 2 described separately was peeled off using methylene chloride.
形成される前記凹部３の深さを工３０Ｓ７０μｍに調整
可能である。なお、深さ５０〜７０μｍの範囲でエツチ
ングする場合、サイドエツチングの影響があるため、フ
ォトマスク設計時に実際必要なレジストライン巾より１
０μｍ程度広く設定した方が良い。次に表１に示す組成
の偵脂４を前記凹部３に充填したのち１５０℃、４０
ｋｇ ／ ＜ｉで６０分間加熱圧着口、再びサンドペー
パで研摩する。この際、充填樹脂４をエシート状にした
ものを加熱圧着しても良（、又はポリウレタン、ポリエ
ステル、シリコーン、７）紫檀（脂、ポリエチレン、塩
化ビニル圀脂でも良い。The depth of the recess 3 to be formed can be adjusted to 70 μm. Note that when etching in the depth range of 50 to 70 μm, there is an effect of side etching, so the width of the resist line should be 1
It is better to set it as wide as about 0 μm. Next, after filling the concave portion 3 with grease 4 having the composition shown in Table 1,
kg/<i for 60 minutes, and then sand the opening again with sandpaper. At this time, the filled resin 4 may be heated and pressed in the form of sheet (or polyurethane, polyester, silicone, 7) rosewood, polyethylene, vinyl chloride resin.
また２度目の研摩の際はステンレス１ｖ７１の露出面５
が凹部６より深くならないように研摩し、このステンレ
ス板をマスター基板６とする。なお、マスター基板は単
にステンレス板１上の所望する部分以外に液状レジスト
などにより与さ１〜５ａｍ程度のレジストパターンを形
成したもので良く、Ｊｉ％さ１８〜５０μｍのフィルム
状レジスト全使用してパターン形成をした後、電気めっ
きでレジスト厚と同等の厚さの回路パターンを形成した
ものも便用可能である。次に異方導電性フィルム（アニ
ンルムー１０５２日立化成社′ｇＪ）７に１ｓｏ℃、１
０ｋｇ／ａｎ’で１分間加熱圧着する。さらに１．６Ａ
／ｄｌ１１″′Ｃ硫酸銅めっきを行い、導体厚１０μｍ
の回路パターン８を得る。次いで異方導電性フィルム７
をマスター基板６より剥離し、所望する配線板とする。Also, when polishing for the second time, the exposed surface 5 of the stainless steel 1v71
The stainless steel plate is polished so that it is no deeper than the recess 6, and this stainless steel plate is used as the master substrate 6. Note that the master substrate may simply be a resist pattern of about 1 to 5 am formed using a liquid resist or the like on the stainless steel plate 1 other than the desired portion, and a resist pattern of about 1 to 5 μm with a Ji% of 18 to 50 μm is used entirely. After pattern formation, a circuit pattern having a thickness equivalent to the resist thickness is formed by electroplating. Next, an anisotropic conductive film (Aninlumu 1052 Hitachi Chemical 'gJ) was coated at 1so℃ and 1
Heat and press at 0 kg/an' for 1 minute. Another 1.6A
/dl11'''C copper sulfate plating, conductor thickness 10μm
A circuit pattern 8 is obtained. Next, the anisotropic conductive film 7
is peeled off from the master board 6 to obtain a desired wiring board.
この配線板は、線巾、線間隔が８０μｍの回路パターン
を有するものである。本発明によって得たマスター基板
６は６００回の再利用可能な成績を得た。This wiring board has a circuit pattern with a line width and line spacing of 80 μm. The master board 6 obtained according to the present invention was able to be reused 600 times.
表１
（発明の効果）
本発明の配線板製造方法におけるマスター基板は再利用
が可能であるため、工程が短縮できる。Table 1 (Effects of the Invention) Since the master substrate in the wiring board manufacturing method of the present invention can be reused, the process can be shortened.
本発明の製造方法は、配線板の高密度化に十分対応する
ことができる。The manufacturing method of the present invention can sufficiently cope with increasing the density of wiring boards.
本発明による製造コストは大巾に減少した。Manufacturing costs with the present invention have been greatly reduced.
第１図（ａ）〜（Ｃ）は本発明を説明する断面図である
。
１・・・・・・ステンレス板、２・・・・・・エツチン
グ用レジストパターン、３・・・・・・エツチング部（
凹り、４・・・・・・充填樹脂、５・・・・・・ステン
レス板表面、６・・・・・・マスター基板、７・・・・
・・異方導電性フィルム、８・・・・・・回路パターン
。
第１図FIGS. 1(a) to 1(C) are cross-sectional views illustrating the present invention. 1... Stainless steel plate, 2... Resist pattern for etching, 3... Etching part (
Recess, 4...Filled resin, 5...Stainless steel plate surface, 6...Master board, 7...
...Anisotropic conductive film, 8...Circuit pattern. Figure 1
Claims (1)
トパターンを形成する第一工程。 （Ｂ）加熱圧着すると厚さ方向にのみ導電性が得られる
接着フィルムを、前記レジストパ ターンを形成した面の全面に加熱圧着する 第二工程。 （Ｃ）前記接且フィルム上の前記レジストパターン以外
の部分に、電気めっきによって導 電性パターンを形成する第三工程。 （Ｄ）前記接着フィルムを前記保持体より剥離する第四
工程。[Claims] 1. A method for manufacturing a wiring board comprising the following steps: (A) A first step of forming an insulating resist pattern on the surface of the conductive holder. (B) A second step of heat-pressing an adhesive film that can obtain conductivity only in the thickness direction by heat-pressing onto the entire surface on which the resist pattern is formed. (C) A third step of forming a conductive pattern on a portion of the adhesive film other than the resist pattern by electroplating. (D) A fourth step of peeling off the adhesive film from the holder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12145086A JPS62277790A (en) | 1986-05-27 | 1986-05-27 | Manufacture of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12145086A JPS62277790A (en) | 1986-05-27 | 1986-05-27 | Manufacture of wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62277790A true JPS62277790A (en) | 1987-12-02 |
Family
ID=14811434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12145086A Pending JPS62277790A (en) | 1986-05-27 | 1986-05-27 | Manufacture of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62277790A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05287557A (en) * | 1992-04-15 | 1993-11-02 | Uehara Name Plate Kogyo Kk | Pretreatment of stainless steel sheet for resist printing and ic card protective cover |
-
1986
- 1986-05-27 JP JP12145086A patent/JPS62277790A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05287557A (en) * | 1992-04-15 | 1993-11-02 | Uehara Name Plate Kogyo Kk | Pretreatment of stainless steel sheet for resist printing and ic card protective cover |
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