JPS62267677A - Testing system for counter circuit - Google Patents
Testing system for counter circuitInfo
- Publication number
- JPS62267677A JPS62267677A JP61112869A JP11286986A JPS62267677A JP S62267677 A JPS62267677 A JP S62267677A JP 61112869 A JP61112869 A JP 61112869A JP 11286986 A JP11286986 A JP 11286986A JP S62267677 A JPS62267677 A JP S62267677A
- Authority
- JP
- Japan
- Prior art keywords
- serial
- parallel
- lsi
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 33
- 238000006243 chemical reaction Methods 0.000 claims description 16
- 238000010998 test method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はカウンタ回路試験方式に関し、特にＬＳＩに内
蔵されるカウンタ回路試験方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter circuit testing method, and particularly to a counter circuit testing method built into an LSI.
従来、この種のカウンタ回路試験方式は、第３図に示す
ようになっていた。Conventionally, this type of counter circuit testing method has been as shown in FIG.
第３図は従来のカウンタ回路試験方式の一例を示すブロ
ック図である。ＬＳＩｌ０に内蔵された２ビットカウン
タ回路（以下ＣＮＴ）１２はＬＳＩ主機能回路１１によ
って使用されるが、ＬＳｌｌｏの製造時にＣＮＴ１２の
機能の正常性を確認するために、データ入力端子Ｄｏ、
Ｄｉ、〜Ｄνと、データ出力端子ＱＯ，Ｑ１．〜（ｌと
、任意データをロードするロード端子り等をＬＳＩｌ０
の外部端子として出しておき、データ入力端子ＤＯ，Ｄ
ｉ、〜ＩＭ’にテストパターンを設定しデータ出力端子
ＱＯ，Ｑ１．〜Ｑ２の出カバターンをチェックすること
により行なっている。なお参照記号ＩＮ０，１．〜ｎと
０ＵＴ０．１．〜ｍはそれぞれＬＳＩ主機能回路１１の
人、出力端子である。FIG. 3 is a block diagram showing an example of a conventional counter circuit testing method. The 2-bit counter circuit (hereinafter referred to as CNT) 12 built into LSI10 is used by the LSI main function circuit 11, but in order to confirm the normality of the function of CNT12 during the manufacturing of LSI10, the data input terminal Do,
Di, ~Dν, and data output terminals QO, Q1 . ~(L, load terminal for loading arbitrary data, etc. are connected to LSI10.
output as external terminals, and connect them to data input terminals DO, D.
A test pattern is set on data output terminals QO, Q1 . ~ This is done by checking the output turn of Q2. Note that reference symbols IN0, 1. ~n and 0UT0.1. -m are output terminals of the LSI main function circuit 11, respectively.
〔発明が解決しようとする問題点）
上述した従来のカウンタ回路試験方式では、入カバター
ン、出カバターン共並列に行なっているのでｎビ・ソト
カウンタの場合は少なくとも２ｎ本の端子が必要となり
、ｎが大きくなるほど端子数が多くなるという欠点があ
る。特にＬＳＩに内蔵されるカウンタ回路では、ＬＳＩ
の端子数は経済性、製造性から制限を受けるのでこれは
致命的欠点である。なお、端子制限の場合、試験端子を
使用せずカウンタ回路で実際にカウントアツプして試験
する方式もあるが、この方式では試験時間が非常に長く
かかるという欠点がある。[Problems to be Solved by the Invention] In the conventional counter circuit testing method described above, input cover turns and output cover turns are performed in parallel, so in the case of an n-bi soto counter, at least 2n terminals are required. The disadvantage is that the larger the number of terminals, the larger the number of terminals. Especially in the counter circuit built into LSI, LSI
This is a fatal drawback because the number of terminals in the device is limited by economics and manufacturability. In the case of terminal restriction, there is a method in which the test is performed by actually counting up with a counter circuit without using the test terminal, but this method has the disadvantage that the test takes a very long time.
本発明のカウンタ回路試験方式は、ＬＳＩに内蔵される
カウンタ回路において、入力ビット群に接続され前記Ｌ
ＳＩの外部から入力した直列情報を並列情報に変換する
直列／並列変換回路と、出力ビット群に接続され並列情
報を直列情報に変換する並列／直列変換回路とを備え、
前記ＬＳＩの外部から前記直列／並列変換回路に直列の
テストパターンを入力し前記並列／直列変換回路出力の
直列データをチェックしている。In the counter circuit test method of the present invention, in a counter circuit built in an LSI, the L
Equipped with a serial/parallel conversion circuit that converts serial information input from outside the SI into parallel information, and a parallel/serial conversion circuit that is connected to the output bit group and converts parallel information into serial information,
A serial test pattern is input to the serial/parallel conversion circuit from outside the LSI, and the serial data output from the parallel/serial conversion circuit is checked.
〔実施例〕 次に本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.
第１図は本発明のカウンタ回路試験方式の一実施例を示
すブロック図、第２図は第１図における直列／並列変換
の状況を示すタイムチャートである。FIG. 1 is a block diagram showing an embodiment of the counter circuit testing method of the present invention, and FIG. 2 is a time chart showing the status of serial/parallel conversion in FIG. 1.
第１図において、ＬＳＩＩは従来例におけるＬＳＩｌ０
（第３図に図示）のＣＮＴ１２の前段。In FIG. 1, LSII is LSIl0 in the conventional example.
(shown in FIG. 3) in the front stage of the CNT 12.
後段にそれぞれ直列／並列変換回路（以下Ｓ／Ｐ）１３
、並列／直列変換回路（以下Ｐ／５）１４を接続し、Ｌ
ＳＩＩの外部端子としてＳ／Ｐ １３は試験用入力端子
Ｔ、Ｄと接続され、またＰ／Ｓ １４は試験用出力端子
Ｑと接続されている。Serial/parallel conversion circuit (hereinafter referred to as S/P) 13 in the subsequent stage
, parallel/serial conversion circuit (hereinafter referred to as P/5) 14 is connected, and L
As external terminals of the SII, the S/P 13 is connected to test input terminals T and D, and the P/S 14 is connected to a test output terminal Q.
ＣＮＴ１２の試験は、第１図に示すように１個の試験用
入力端子りから（ｅ＋１）ビットの直列データを入力し
、Ｓ、／Ｐ１３により入力データＤＯ，Ｄｉ、〜ＩＭに
変換して分配し、ＣＮＴ１２に試験用入力端子りからの
テストパターンをセットする。ＣＮＴ１２の出力ＱＯ，
Ｑｌ、〜Ｑｌ！はＰ／Ｓ １４により直列変換され１個
のデータ出力端子Ｑに（ｆ＋１）ビットの直列データと
して出力され、ＬＳＩＩの外部に表示される。To test CNT12, as shown in Figure 1, (e+1) bits of serial data is input from one test input terminal, converted to input data DO, Di, ~IM by S, /P13, and distributed. Then, set the test pattern from the test input terminal to CNT12. Output QO of CNT12,
Ql, ~Ql! is serially converted by the P/S 14, outputted to one data output terminal Q as (f+1) bits of serial data, and displayed externally of the LSII.
以上説明したように本発明は、１つの入力端子からのテ
ストパターンを直列／並列回路によって（ｆ＋１）ピッ
Ｉ・に展開してカウンタ回路にテストパターンをセット
し、キャリアウドビットＣを含む（ｆ＋２＞ビットの出
カバターンを並列／直列変換回路を介して１個の出力端
子に（ｅ ＋２ ＞ビットの直列データとして表示する
ことができる。As explained above, the present invention develops a test pattern from one input terminal into (f+1) pins I by a series/parallel circuit, sets the test pattern in the counter circuit, and sets the test pattern in the counter circuit, including the carried bit C (f+2 The > bit output pattern can be displayed as (e +2 > bit serial data) on one output terminal via a parallel/serial conversion circuit.
従ってビット数の大きなカウンタを内蔵するＬＳＩにお
いてもカウンタ試験用のデータ入力用、出力用端子とし
て各１本でよいので、端子制限によるＬＳＩ化が不可と
いう事態がなくなり、またテストパターンによる試験な
ので試験時間が短くなる効果がある。Therefore, even in an LSI that has a built-in counter with a large number of bits, only one terminal each is needed for data input and output for counter testing, eliminating the situation where LSI implementation is impossible due to terminal limitations, and since testing is based on a test pattern, the test This has the effect of shortening the time.
第１図は本発明のカウンタ回路試験方式の一実施例を示
すブロック図、第２図は第１図における直列／並列変換
の状況を示すタイムチャート、第３図は従来のカウンタ
回路試験方式の一例を示すブロック図である。
ｌ、１０・・・ＬＳＩ、１１・・・ＬＳＩ主機能回路、
１２・・・カウンタ回路（ＣＮＴ）、１３・・・直列／
並列変換回路（Ｓ／’Ｐ）−１４・・・並列／直列変換
回路（Ｐ／Ｓ）、Ｄ、Ｔ・・・試験用入力端子、Ｑ・・
・試験用出力端子。Fig. 1 is a block diagram showing an embodiment of the counter circuit testing method of the present invention, Fig. 2 is a time chart showing the status of serial/parallel conversion in Fig. 1, and Fig. 3 is a block diagram showing an embodiment of the counter circuit testing method of the present invention. FIG. 2 is a block diagram showing an example. l, 10...LSI, 11...LSI main function circuit,
12...Counter circuit (CNT), 13...Series/
Parallel conversion circuit (S/'P)-14...Parallel/serial conversion circuit (P/S), D, T...Test input terminal, Q...
・Test output terminal.
Claims (1)
群に接続され前記ＬＳＩの外部から入力した直列情報を
並列情報に変換する直列／並列変換回路と、出力ビット
群に接続され並列情報を直列情報に変換する並列／直列
変換回路とを備え、前記ＬＳＩの外部から前記直列／並
列変換回路に直列のテストパターンを入力し前記並列／
直列変換回路出力の直列データをチェックすることを特
徴とするカウンタ回路試験方式。A counter circuit built into an LSI includes a serial/parallel conversion circuit connected to an input bit group to convert serial information input from outside the LSI into parallel information, and a serial/parallel conversion circuit connected to an output bit group to convert parallel information to serial information. a parallel/serial conversion circuit that inputs a serial test pattern from outside the LSI to the serial/parallel conversion circuit;
A counter circuit test method characterized by checking serial data output from a serial conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61112869A JPS62267677A (en) | 1986-05-16 | 1986-05-16 | Testing system for counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61112869A JPS62267677A (en) | 1986-05-16 | 1986-05-16 | Testing system for counter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62267677A true JPS62267677A (en) | 1987-11-20 |
Family
ID=14597561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61112869A Pending JPS62267677A (en) | 1986-05-16 | 1986-05-16 | Testing system for counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62267677A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010006832A (en) * | 1999-06-16 | 2001-01-26 | 아끼구사 나오유끼 | Semiconductor integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56140448A (en) * | 1980-04-03 | 1981-11-02 | Nec Corp | Logical operation circuit |
| JPS6041774A (en) * | 1983-08-18 | 1985-03-05 | Sanyo Electric Co Ltd | Nonaqueous electrolyte battery |
-
1986
- 1986-05-16 JP JP61112869A patent/JPS62267677A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56140448A (en) * | 1980-04-03 | 1981-11-02 | Nec Corp | Logical operation circuit |
| JPS6041774A (en) * | 1983-08-18 | 1985-03-05 | Sanyo Electric Co Ltd | Nonaqueous electrolyte battery |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010006832A (en) * | 1999-06-16 | 2001-01-26 | 아끼구사 나오유끼 | Semiconductor integrated circuit |
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