JPS62265764A - Manufacture of thin film field effect transistor - Google Patents
Manufacture of thin film field effect transistorInfo
- Publication number
- JPS62265764A JPS62265764A JP10844486A JP10844486A JPS62265764A JP S62265764 A JPS62265764 A JP S62265764A JP 10844486 A JP10844486 A JP 10844486A JP 10844486 A JP10844486 A JP 10844486A JP S62265764 A JPS62265764 A JP S62265764A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- source
- drain
- silicon layer
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 8
- 230000005669 field effect Effects 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000003071 parasitic effect Effects 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は薄膜電界効果トランジスタにおいて、ソース・
ゲート間およびドレイン・ゲート間の重なりを零とし、
寄生容量を低減するに好適な薄膜電界効果トランジスタ
の製造方法に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a thin film field effect transistor in which a source
The overlap between gates and between drain and gate is set to zero,
The present invention relates to a method of manufacturing a thin film field effect transistor suitable for reducing parasitic capacitance.
近年、非単結晶シリコンにより形成された薄膜電界効果
トランジスタ（ＴＰＴ）が注目されている。特に、上記
半導体薄膜が低温で形成できるため、薄膜半導体装置を
構成するための基板が特に限定されず、また、従来の露
光技術、エツチング技術等のパターン形成法もそのまま
使用でき大面積基板への集積化も可能であるなどの利点
を有する。In recent years, thin film field effect transistors (TPTs) formed from non-single crystal silicon have attracted attention. In particular, since the semiconductor thin film described above can be formed at low temperatures, there are no particular limitations on the substrate used to construct the thin film semiconductor device, and conventional pattern forming methods such as exposure technology and etching technology can be used as is, making it possible to form large-area substrates. It has advantages such as being able to be integrated.
第２図は従来のＴＰＴの基本構造を概略的に示す図であ
る。この図において、１は絶縁性基板。FIG. 2 is a diagram schematically showing the basic structure of a conventional TPT. In this figure, 1 is an insulating substrate.
２は非晶質シリコン等の半導体膜、３はゲート絶縁膜、
４はゲート電極、９．１０はそれぞれソースドレイン電
極で良好なオーミックコンタクトを得るための不純物ド
ープ半導体膜である。2 is a semiconductor film such as amorphous silicon, 3 is a gate insulating film,
Reference numeral 4 is a gate electrode, and reference numerals 9 and 10 are source and drain electrodes, respectively, which are impurity-doped semiconductor films for obtaining good ohmic contact.
さて、第２図に示した構造ではゲート電極４とソース・
ドレイン９，１０は自己整合の位置に関係なく、ゲート
電極２とソース・ドレイン９゜１ｏの平面的型なりは不
純物を含まない非晶質シリコン２とゲート絶縁膜３とを
積層誘電体とする重なり容量を形成する。一般に、寄生
容量を有するＴＰＴを含む回路の動作速度を上げるため
には、ＴＰＴのＯＮ状態における抵抗を下げればよいが
、このためにはＴＰＴのチャンネル幅を大きくする必要
がある。この場合従来構造のＴＥＴでは寄生容量もチャ
ンネル幅に比例して増えるため１本質的な動作速度の向
上とはならない。Now, in the structure shown in FIG. 2, the gate electrode 4 and the source
Regardless of the self-alignment position of the drains 9 and 10, the planar type of the gate electrode 2 and source/drain 9°1o is made of a laminated dielectric material consisting of amorphous silicon 2 containing no impurities and a gate insulating film 3. forming an overlapping capacitance. Generally, in order to increase the operating speed of a circuit including a TPT having parasitic capacitance, it is sufficient to reduce the resistance in the ON state of the TPT, but for this purpose it is necessary to increase the channel width of the TPT. In this case, in the conventional TET structure, the parasitic capacitance also increases in proportion to the channel width, so that there is no substantial improvement in operating speed.
そこで、第２図に示す構造が特開昭５８−１９００５８
号公報に記載のように、ソース・ドレインとゲート間の
重なりが雰の構造となっている。しかし。Therefore, the structure shown in FIG.
As described in the publication, the overlap between the source/drain and the gate forms the structure. but.
この構造ではソース・ドレインとゲート間隔が近く、ソ
ース・ドレインとゲートのショートを防止するため、不
純物をドープした半導体膜９，１０を極めて薄くする必
要があり、膜形成の制御が難しい。In this structure, the distance between the source/drain and the gate is close, and in order to prevent a short circuit between the source/drain and the gate, it is necessary to make the impurity-doped semiconductor films 9 and 10 extremely thin, making it difficult to control film formation.
本発明の目的は、ソース・ゲートおよびドレインソー入
間の重なりを零とし、自己整合させてＴＰＴ回路の動作
速度の向上を図り、素子の微細化と高集積化を可能とす
るとともに、ソース・ゲート間あるいはドレイン・ゲー
ト間のショートの少ないＴＰＴの製造方法を提供するこ
とにある。An object of the present invention is to eliminate the overlap between the source gate and the drain input, improve the operating speed of the TPT circuit by self-aligning, and enable miniaturization and high integration of elements. Another object of the present invention is to provide a method for manufacturing a TPT with less short-circuiting between the drain and the gate.
本発明においては、まず絶縁性基板上に半導体膜を堆積
し、この上にゲート絶縁膜となる酸化シリコン膜を堆積
し、その表面を不純物をドープした半導体膜でおおいゲ
ート電極を形成する。そしてこのゲート電極をマスクと
して前記絶縁膜をエツチングしてソースおよびドレイン
領域の半導体表面を露出させる。この後、さらに露出し
た半導体表面を選択エツチングする。この後、露出した
半導体表面およびゲート電極表面に不純物をドープした
半導体を選択的ゲート絶縁膜、半導体界面以下に堆積す
ることトこよりソース・ドレインとゲート間の重なりを
零とし、ソース・ドレイン間のショートの少ないＴＰＴ
を製造する。In the present invention, a semiconductor film is first deposited on an insulating substrate, a silicon oxide film serving as a gate insulating film is deposited thereon, and the surface thereof is covered with a semiconductor film doped with impurities to form a gate electrode. Then, using this gate electrode as a mask, the insulating film is etched to expose the semiconductor surface of the source and drain regions. After this, the exposed semiconductor surface is further selectively etched. After that, a semiconductor doped with impurities is deposited on the exposed semiconductor surface and the gate electrode surface as a selective gate insulating film, which is deposited below the semiconductor interface, thereby reducing the overlap between the source/drain and gate to zero, and reducing the overlap between the source/drain and the gate. TPT with less short circuit
Manufacture.
以下、本発明の一実施例を第１図により説明する。まず
、絶縁性基板１上に厚さ２０００人の不純物を含まない
非単結晶シリコン層２をＳｉＨ４のプラズマＣＶＤより
堆積する（ａ）、その後。An embodiment of the present invention will be described below with reference to FIG. First, a non-single crystal silicon layer 2 containing no impurities is deposited to a thickness of 2000 on an insulating substrate 1 by SiH4 plasma CVD (a), and then.
（ｂ）に示すように非単結晶シリコンＮ２をパターン形
成して島状の非単結晶シリコン層２′を形成する。さら
に（ｃ）に示すように常圧ＣＶＤにより厚さ１０００人
のゲート絶縁膜となる酸化シリコン層３を堆積し、次に
ゲート電極となる不純物をドープしたシリコン層４を５
００人の厚さに堆積する。次に、ゲート電極４上にレジ
ストパターン５を形成する（ｄ）。その後、レジストパ
ターン５をマスクとし、ゲート電極となる不純物をドー
プしたシリコンＮ４をＣＦ ４ ＋ Ｏｘ系ガスでプラ
ズマエツチング除去し、その後ＣＨＦ ｓガスでゲート
絶縁膜３をプラズマエツチング除去し、ソース・ドレイ
ン領域の不純物を含まない非単結晶シリコン層２′ を
露出させる（ｆ）、その後、さらにゲート電極４をマス
クとし、ＣＦ ４ ＋ Ｏｚ系ガスで不純物を含まない
非単結晶シリコン層２′を厚さ１５００人プラズマエツ
チングする（ｇ）。As shown in (b), the non-single crystal silicon N2 is patterned to form an island-shaped non-single crystal silicon layer 2'. Furthermore, as shown in (c), a silicon oxide layer 3, which will become a gate insulating film, is deposited to a thickness of 1000 nm by atmospheric pressure CVD, and then a silicon layer 4 doped with impurities, which will become a gate electrode, is deposited.
Deposited to a thickness of 0.00 people. Next, a resist pattern 5 is formed on the gate electrode 4 (d). Thereafter, using the resist pattern 5 as a mask, the impurity-doped silicon N4 that will become the gate electrode is removed by plasma etching with CF 4 + Ox gas, and then the gate insulating film 3 is removed by plasma etching with CHF s gas to form the source and drain. The region of the non-single crystal silicon layer 2' that does not contain impurities is exposed (f), and then, using the gate electrode 4 as a mask, the non-single crystal silicon layer 2' that does not contain impurities is thickened using CF 4 + Oz-based gas. 1,500 people were plasma etched (g).
次に、この上に不純物をドープしたシリコン膜６゜７．
８を非単結晶シリコンＭ２’ 、４を種とした選択エピ
タキシャル成長により厚さ１０００人形成する（ｈ）。Next, a silicon film 6°7. doped with impurities is placed on top of this.
8 is made of non-single-crystal silicon M2', and 4 is selectively epitaxially grown to a thickness of 1000 nm using 4 as a seed (h).
なお、本発明は上記実施例に限定されない０例えば、非
単結晶シリコンＭ２はＧｅ等の半導体やｓｂ等の化合物
半導体であってもよい。また、これらの半導体膜の形成
法はスパック、蒸着、熱分解法などいかなる方法でもよ
い。また、ゲート絶縁膜も酸化シリコンに限らず窒化シ
リコン等でもよい。Note that the present invention is not limited to the above embodiments. For example, the non-single crystal silicon M2 may be a semiconductor such as Ge or a compound semiconductor such as sb. Further, the method for forming these semiconductor films may be any method such as spucking, vapor deposition, or thermal decomposition. Furthermore, the gate insulating film is not limited to silicon oxide, but may also be silicon nitride or the like.
本発明によれば、ゲートに自己整合されたソース・ドレ
インが、ゲート絶縁膜の膜厚以上の間隔、をもって形成
できるので、ゲート電極とソース・ドレイン電極の間の
寄生容量が小さく、高速動作が可能となる。また、ソー
ス・ドレインとゲートのショートが低減できるので、Ｔ
ＥＴ回路の素子の微細化、高集積化を図る効果がある。According to the present invention, the source/drain that is self-aligned to the gate can be formed with a spacing greater than the thickness of the gate insulating film, so the parasitic capacitance between the gate electrode and the source/drain electrode is small, and high-speed operation is possible. It becomes possible. In addition, short circuits between the source/drain and gate can be reduced, so T
This has the effect of achieving miniaturization and high integration of ET circuit elements.
第１図（ａ）〜（ｈ）は本発明の一実施例のＴＰＴの製
造工程を示す断面図、第２図は従来構造のＴＰＴの断面
図である。
１・・・絶縁性基板、２，２′・・・不純物を含まない
非単結晶シリコン層、３・・・ゲート絶縁膜（酸化シリ
コン）、４・・・ゲート電極（不純物をドープしたシリ
コン層）、５・・・レジスト、６，７，８，９゜１０・
・・不純物をドープしたシリコン層。1A to 1H are cross-sectional views showing the manufacturing process of a TPT according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a TPT having a conventional structure. 1... Insulating substrate, 2, 2'... Non-single crystal silicon layer containing no impurities, 3... Gate insulating film (silicon oxide), 4... Gate electrode (silicon layer doped with impurities) ), 5... resist, 6, 7, 8, 9°10.
...Silicon layer doped with impurities.
Claims (1)
導体膜の表面を絶縁膜でおおつてその上にゲート電極を
形成する工程と、このゲート電極をマスクとして前記絶
縁膜をエッチングしてソースおよびドレイン領域の半導
体膜表面を露出させる工程と、この後さらにゲートをマ
スクとして半導体膜をエッチングし、前記半導体膜エッ
チング表面とゲート電極上に選択的に不純物をドープし
た半導体膜を前記絶縁膜半導体膜界面以下に形成する工
程とより成る薄膜電界効果トランジスタであり、ソース
・ゲート間およびドレイン・ゲート間の重なりを少なく
し、寄生容量を低減すると共に、ソース・ゲート間およ
びドレイン・ゲート間のショートを低減することを特徴
とする薄膜電界効果トランジスタの製造方法。1. A step of depositing a semiconductor film on an insulating substrate, a step of covering the surface of this semiconductor film with an insulating film and forming a gate electrode thereon, and etching the insulating film using the gate electrode as a mask. A step of exposing the semiconductor film surface of the source and drain regions, and then further etching the semiconductor film using the gate as a mask, and adding a semiconductor film selectively doped with impurities to the insulating film on the etched surface of the semiconductor film and the gate electrode. It is a thin film field effect transistor that is formed below the semiconductor film interface, reducing the overlap between the source and gate and between the drain and gate, reducing parasitic capacitance, and reducing the overlap between the source and gate and between the drain and gate. A method for manufacturing a thin film field effect transistor characterized by reducing short circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10844486A JPS62265764A (en) | 1986-05-14 | 1986-05-14 | Manufacture of thin film field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10844486A JPS62265764A (en) | 1986-05-14 | 1986-05-14 | Manufacture of thin film field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62265764A true JPS62265764A (en) | 1987-11-18 |
Family
ID=14484932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10844486A Pending JPS62265764A (en) | 1986-05-14 | 1986-05-14 | Manufacture of thin film field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62265764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1287563A1 (en) * | 2000-05-16 | 2003-03-05 | Infineon Technologies AG | Field effect transistor and method for producing a field effect transistor |
-
1986
- 1986-05-14 JP JP10844486A patent/JPS62265764A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1287563A1 (en) * | 2000-05-16 | 2003-03-05 | Infineon Technologies AG | Field effect transistor and method for producing a field effect transistor |
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