EP1287563A1 - Field effect transistor and method for producing a field effect transistor - Google Patents

Field effect transistor and method for producing a field effect transistor

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Publication number
EP1287563A1
EP1287563A1 EP01943066A EP01943066A EP1287563A1 EP 1287563 A1 EP1287563 A1 EP 1287563A1 EP 01943066 A EP01943066 A EP 01943066A EP 01943066 A EP01943066 A EP 01943066A EP 1287563 A1 EP1287563 A1 EP 1287563A1
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EP
European Patent Office
Prior art keywords
field effect
effect transistor
region
layer
area
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EP01943066A
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German (de)
French (fr)
Inventor
Franz Kreupl
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/902—FET with metal source region

Definitions

  • the invention relates to a field effect transistor and a method for producing a field effect transistor.
  • the length of the space charge zone and, associated therewith, the length of the channel region d is indirectly proportional to the root of the doping of the semiconductor used as a substrate in the field effect transistor.
  • a drain layer of the field effect transistor is provided with a barrier layer to be tunneled through by electrical charge carriers, according to [2] made of niobium oxide.
  • the invention is based on the problem of specifying a field effect transistor and a method for producing a field effect transistor with an improved scalability compared to the known field effect transistors.
  • a field effect transistor has an electrically non-conductive substrate, a drain region and a source region.
  • Both the drain region and the source region can contain a metal electrode.
  • a channel region is provided between the drain region and the source region, the channel region having a metal layer, that is to say clearly a metal layer forms the channel region required in a field effect transistor for transporting electrical charge carriers from the source region into the drain region ,
  • a gate area is provided, via which the channel area can be controlled.
  • Such a field effect transistor can be manufactured according to the following procedure.
  • a drain region and a source region are formed on or in a substrate.
  • a channel layer forming a channel area is applied to the substrate between the drain area and the source area.
  • a separating layer is applied to the metal layer and between the drain region and the source region.
  • On the interface is a Gate region is formed, the gate region being electrically separated from the drain region, the source region and the channel region by the separating layer in such a way that the channel region can be controlled via the gate region.
  • the invention can clearly be seen in the fact that the channel region formed by a semiconductor material in conventional field effect transistors and which can be controlled via the gate region is formed according to the invention by a metal layer which, due to a field effect occurring in the case of a thin metal layer, extends across the gate region of a field effect transistor can be controlled.
  • a second gate region can be provided in the field effect transistor, so that a so-called dual gate arrangement is formed in the field effect transistor.
  • the second gate area too, it is possible to control the channel area, as with a conventional field effect transistor.
  • the first gate area and the second gate area can be electrically coupled to one another.
  • the metal layer can have one or more layers of metal atoms.
  • a further advantage of the invention can be seen in particular in the high electrical conductivity of the metal layer which forms the channel region. In this way, the power loss generated when the field effect transistor is switched from a first state to a second state is reduced. Due to the high conductivity of the metal layer, the speed of the switching operation of the field effect transistor is also considerably increased compared to conventional field effect transistors.
  • the metal layer can contain at least one of the following metals: platinum, gold, silver, titanium, tantalum, palladium, bismuth, indium, chromium, vanadium, manganese, iron, cobalt, nickel, yttrium, zirconium, niobium, molybdenum, technetium, hafnium, Tungsten, or an alloy of at least two of the aforementioned metals.
  • the separating layer can be an electrically insulating separating layer and / or a layer with a large dielectric constant and / or a ferroelectric layer.
  • the separating layer can contain SBT, silicon dioxide, and / or BST.
  • the drain region and / or the source region and / or the gate region comprise metal, for example a metal electrode.
  • the same metals can be used as the metal for the metal electrode or the metal electrodes as for the metal layer, i.e. the metal electrode or the metal electrodes can contain:
  • metals other than metal electrodes can also be used. Due to the high conductivity of the corresponding connections, ie electrodes of the field effect transistor, the overall conductivity of the field effect transistor is further increased in accordance with this embodiment of the invention, whereby the speed when switching the field effect transistor from a conductive state to a blocking state is further increased considerably.
  • the field effect transistor is particularly well suited for high-frequency applications.
  • the drain region and the source region can be formed on the substrate in a known manner, for example by means of predeterminable doping of charge carriers, electrons or holes.
  • the metal layer can be separated from the gas phase by means of a suitable deposition process (chemical vapor deposition, CVD).
  • CVD chemical vapor deposition
  • FIG. 1 shows a cross section through a field effect transistor according to a first embodiment of the invention
  • Figure 2 shows a cross section through a field effect transistor according to a second embodiment of the invention
  • Figure 3 shows a cross section through a field effect transistor according to a third embodiment of the invention.
  • Fig.l shows a field effect transistor 100 according to a first embodiment of the invention.
  • the field effect transistor 100 has a substrate 101 made of electrically non-conductive material, that is to say made of an electrically insulating material, according to the first exemplary embodiment made of silicon dioxide SiO 2 or aluminum oxide Al 2 O 3 .
  • a first metal electrode 102 and a second metal electrode 103 are applied to the substrate 101 at a distance of 1 nm to 1000 nm from one another by means of a CVD method, a sputtering method or a vapor deposition method.
  • the first metal electrode 102 and the second metal electrode 103 may be made of platinum or titanium. Alternatively, any metallic alloy or metal can be used to form the first metal electrode 102 or the second metal electrode 103.
  • the first metal electrode 102 serves as the source region of the field effect transistor 100 and the second metal electrode 103 serves as the drain region of the field effect transistor 100.
  • a monoatomic or multi-atomic metal layer 104 made of platinum is deposited between the first metal electrode 102 and the second metal electrode 103 by means of a suitable CVD method.
  • the metal layer 104 is electrically coupled to the first metal electrode 102 and to the second metal electrode 103 and clearly forms a channel region within the field defect transistor 100.
  • the first metal electrode 102 and the second metal electrode 103 each have a width b, symbolized in FIG. 1 by a double arrow 105, 106 from 1 nm to 100 nm.
  • the widths of the metal electrodes 102, 103 need not be the same.
  • the channel area i.e. the metal layer 104 has a surface
  • an electrically insulating separating layer 107 made of silicon dioxide or silicon nitride Si 3 N4 is applied to the metal layer 104 by means of a CVD process, a sputtering process or a vapor deposition process.
  • a gate electrode 109 forming or forming a gate region is introduced or applied.
  • the gate electrode 109 can also be produced from the metals or metal alloys mentioned above, from which the first metal electrode 102 or the second metal electrode 103 can be formed.
  • a further insulated Rende layer 110 applied, for example, silicon dioxide or silicon nitride.
  • FIG. 2 shows a field effect transistor 200 according to a second exemplary embodiment of the invention.
  • the field effect transistor 200 according to the second embodiment is substantially the same as the field effect transistor 100 according to the first embodiment.
  • the manufacturing method and the selected dimensions for manufacturing the field effect transistor 200 are the same as those of the field effect transistor 100, as described in connection with the first embodiment.
  • the field effect transistor 200 according to the second exemplary embodiment differs from the field effect transistor 100 according to the first exemplary embodiment in particular in that a further gate electrode 201 is provided as the gate region in the substrate 101, hereinafter referred to as the second gate electrode 201.
  • the first gate electrode 109 is electrically coupled to the second gate electrode 201 arranged below the channel region 104, which is spaced from a lower surface 202 of the channel region 104 at a distance of 1 nm to 50 nm, symbolized in FIG. 2 by an arrow 203.
  • first gate electrode 109 and the second gate electrode 201 thus form a so-called dual gate arrangement in the field effect transistor 200.
  • the second gate electrode 201 is embedded in the substrate 101 according to a dual damascene process.
  • the structure for the second gate electrode 201 is etched into the substrate 101 and then the metal from which the second gate electrode 201 is to be formed is deposited in such a way that the structure etched for the second gate electrode 201 is at least completely identical to the deposited one Metal is filled. Any metal protruding from the structure is removed using a chemical mechanical polishing process (CMP process). The desired oxide is then again deposited accordingly.
  • CMP process chemical mechanical polishing process
  • FIG 3 shows a field effect transistor 300 according to a third exemplary embodiment of the invention.
  • the field effect transistor 300 according to the third exemplary embodiment essentially corresponds to the field effect transistor 100 according to the first exemplary embodiment.
  • the same components of the field effect transistor 300 according to the third embodiment are provided with the same reference numerals as the corresponding components of the field effect transistor 100 according to the first embodiment.
  • the field effect transistor 300 according to the third exemplary embodiment differs from the field effect transistor 100 according to the first exemplary embodiment in particular in that that an electrically insulating layer 301 with a high dielectric constant, ie with a dielectric constant in the range from 1 to 1000, or a ferroelectric layer 301 is applied to the metal layer 104.
  • the layer 301 is applied over the entire area over the channel region by means of a CVD method, a sputtering method or a vapor deposition method.
  • Layer 301 is made of BST or SBT, for example.
  • the thickness of the layer 301 symbolized in FIG. 3 by a double arrow 302 is 1 nm to 50 nm according to the third exemplary embodiment.
  • the first gate electrode 109 is applied to the layer 301.
  • an insulating separating layer 107 is applied to the element resulting in the previous steps.
  • a second gate electrode (not shown) is also provided for the arrangement according to the third exemplary embodiment, which is electrically coupled to the first gate electrode 109.

Abstract

The invention relates to a field effect transistor with a drain region, a source region, a channel region and a gate region. The gate region is provided with a metal layer.

Description

BesehreibungBesehreibung
Feldeffekttransistor und Verfahren zum Herstellen eines FeldeffekttransistorsField effect transistor and method for producing a field effect transistor
Die Erfindung betrifft einen Feldeffekttransistor sowie ein Verfahren zum Herstellen eines Feldeffekttransistors.The invention relates to a field effect transistor and a method for producing a field effect transistor.
Ein solcher Feldeffekttransistor und ein Verfahren zu dessen Herstellung sind aus [1] bekannt.Such a field effect transistor and a method for its production are known from [1].
Ferner ist bei dem in [1] beschriebenen üblichen Feldeffekttransistor bekannt, dass die Länge der Raumladungszone und damit verbunden die Länge des Kanalbereichs d indirekt pro- portional ist zur Wurzel der Dotierung des in dem Feldeffekttransistor als Substrat verwendeten Halbleiters.Furthermore, in the conventional field effect transistor described in [1], it is known that the length of the space charge zone and, associated therewith, the length of the channel region d is indirectly proportional to the root of the doping of the semiconductor used as a substrate in the field effect transistor.
Somit gilt bei den aus [1] bekannten Feldeffekttransistoren:The following applies to the field effect transistors known from [1]:
d oc /! . (1)d oc /! , (1)
VNVN
Aus diesem Zusammenhang zwischen der Länge des Kanalbereichs und der Dotierung des Substrats ist ersichtlich, dass die Skalierbarkeit eines Halbleiterbauelements, insbesondere ei- nes Halbleiter-Feldeffekttransistors durch die nur begrenzt mögliche Skalierung der Dotierung des verwendeten Halbleiters eingeschränkt ist.It can be seen from this relationship between the length of the channel region and the doping of the substrate that the scalability of a semiconductor component, in particular a semiconductor field-effect transistor, is limited by the scaling of the doping of the semiconductor used, which is only possible to a limited extent.
Weiterhin ist in [2] ein sogenannter Metall-Tunnel-Transistor beschrieben, bei dem zwischen dem Source-Bereich und demFurthermore, a so-called metal tunnel transistor is described in [2], in which between the source region and the
Drain-Bereich des Feldeffekttransistors eine durch elektrische Ladungsträger zu durchtunnelnde Barriereschicht, gemäß [2] aus Niobiumoxid, vorgesehen ist.A drain layer of the field effect transistor is provided with a barrier layer to be tunneled through by electrical charge carriers, according to [2] made of niobium oxide.
In [3], [4] ist beschrieben, dass bei einer sehr dünnen Metallschicht mit einer Dicke von einigen Nanometern, insbeson- dere einer Dicke von 5,5 nm ein sogenannter Feldeffekt in der Metallschicht zu beobachten ist.In [3], [4] it is described that in the case of a very thin metal layer with a thickness of a few nanometers, in particular a thickness of 5.5 nm, a so-called field effect can be observed in the metal layer.
Der Erfindung liegt das Problem zugrunde, einen Feldeffekt- transistor sowie ein Verfahren zur Herstellung eines Feldeffekttransistors anzugeben mit einer gegenüber den bekannten Feldeffekttransistoren verbesserten Skalierbarkeit.The invention is based on the problem of specifying a field effect transistor and a method for producing a field effect transistor with an improved scalability compared to the known field effect transistors.
Das Problem wird durch den Feldeffekttransistor und das Ver- fahren zum Herstellen eines Feldeffekttransistors mit den Merkmalen gemäß den unabhängigen Patentansprüchen gelöst.The problem is solved by the field effect transistor and the method for producing a field effect transistor with the features according to the independent patent claims.
Ein Feldeffekttransistor weist ein elektrisch nicht leitendes Substrat, einen Drain-Bereich sowie einen Source-Bereich auf.A field effect transistor has an electrically non-conductive substrate, a drain region and a source region.
Sowohl der Drain-Bereich als auch der Source-Bereich können eine Metallelektrode enthalten.Both the drain region and the source region can contain a metal electrode.
Zwischen dem Drain-Bereich und dem Source-Bereich ist ein Ka- nalbereich vorgesehen, wobei der Kanalbereich eine Metallschicht aufweist, dass heißt anschaulich bildet eine Metallschicht den in einem Feldeffekttransistor erforderlichen Kanalbereich zum Transport elektrischer Ladungsträger von dem Source-Bereich in den Drain-Bereich.A channel region is provided between the drain region and the source region, the channel region having a metal layer, that is to say clearly a metal layer forms the channel region required in a field effect transistor for transporting electrical charge carriers from the source region into the drain region ,
Weiterhin ist ein Gate-Bereich vorgesehen, über den der Kanalbereich gesteuert werden kann.Furthermore, a gate area is provided, via which the channel area can be controlled.
Ein solcher Feldeffekttransistor kann gemäß folgendem Verfa - ren hergestellt werden.Such a field effect transistor can be manufactured according to the following procedure.
Auf oder in einem Substrat werden ein Drain-Bereich und ein Source-Bereich gebildet. Zwischen dem Drain-Bereich und dem Source-Bereich wird eine einen Kanalbereich bildende Kanal- schicht auf dem Substrat aufgebracht. Auf der Metallschicht und zwischen dem Drain-Bereich und dem Source-Bereich wird eine Trennschicht aufgebracht. Auf der Trennschicht wird ein Gate-Bereich gebildet, wobei der Gate-Bereich durch die Trennschicht von dem Drain-Bereich, dem Source-Bereich und dem Kanalbereich elektrisch getrennt ist derart, dass der Kanalbereich über den Gate-Bereich steuerbar ist.A drain region and a source region are formed on or in a substrate. A channel layer forming a channel area is applied to the substrate between the drain area and the source area. A separating layer is applied to the metal layer and between the drain region and the source region. On the interface is a Gate region is formed, the gate region being electrically separated from the drain region, the source region and the channel region by the separating layer in such a way that the channel region can be controlled via the gate region.
Anschaulich kann die Erfindung darin gesehen werden, dass der bei üblichen Feldeffekttransistoren durch ein Halbleitermaterial gebildete Kanalbereich, der über den Gate-Bereich gesteuert werden kann, erfindungsgemäß gebildet wird durch eine Metallschicht, die aufgrund eines bei einer dünnen Metallschicht auftretenden Feldeffekts über den Gate-Bereich eines Feldeffekttransistors gesteuert werden kann.The invention can clearly be seen in the fact that the channel region formed by a semiconductor material in conventional field effect transistors and which can be controlled via the gate region is formed according to the invention by a metal layer which, due to a field effect occurring in the case of a thin metal layer, extends across the gate region of a field effect transistor can be controlled.
In dem Feldeffekttransistor kann ein zweiter Gate-Bereich vorgesehen sein, so dass eine sogenannte Dual-Gate-Anordnung in dem Feldeffekttransistor gebildet ist. Auch mit dem zweiten Gate-Bereich ist es möglich den Kanalbereich, wie bei einem üblichen Feldeffekttransistor, zu steuern. Der erste Gate-Bereich und der zweite Gate-Bereich können miteinander elektrisch gekoppelt sein.A second gate region can be provided in the field effect transistor, so that a so-called dual gate arrangement is formed in the field effect transistor. With the second gate area, too, it is possible to control the channel area, as with a conventional field effect transistor. The first gate area and the second gate area can be electrically coupled to one another.
Die Metallschicht kann eine oder mehrere Lagen von Metallatomen aufweisen.The metal layer can have one or more layers of metal atoms.
Insbesondere aufgrund der sehr hohen Skalierbarkeit der Metallschicht und der Unabhängigkeit der Breite des Kanalbereichs von der Dotierung des Halbleitermaterials, da nunmehr ja Metall für die Realisierung des Kanals in dem Feldeffekttransistor eingesetzt wird, ist eine erhebliche Verbesserung in der Skalierbarkeit des erfindungsgemäßen Feldeffekttransistors erreicht.In particular due to the very high scalability of the metal layer and the independence of the width of the channel region from the doping of the semiconductor material, since metal is now used for the realization of the channel in the field effect transistor, a considerable improvement in the scalability of the field effect transistor according to the invention has been achieved.
Ein weiterer Vorteil der Erfindung ist insbesondere in der hohen elektrischen Leitfähigkeit der Metallschicht, die den Kanalbereich bildet, zu sehen. Auf diese Weise wird die erzeugte Verlustleistung beim Umschalten des Feldeffekttransistors von einem ersten Zustand in einen zweiten Zustand reduziert. Aufgrund der hohen Leitfähigkeit der Metallschicht ist auch die Geschwindigkeit des Schaltvorgangs des Feldeffekttransistors erheblich erhöht verglichen mit üblichen Feldeffekttransistoren.A further advantage of the invention can be seen in particular in the high electrical conductivity of the metal layer which forms the channel region. In this way, the power loss generated when the field effect transistor is switched from a first state to a second state is reduced. Due to the high conductivity of the metal layer, the speed of the switching operation of the field effect transistor is also considerably increased compared to conventional field effect transistors.
Die Metallschicht kann zumindest eines der folgenden Metalle enthalten: Platin, Gold, Silber, Titan, Tantal, Palladium, Wismut, Indium, Chrom, Vanadium, Mangan, Eisen, Kobalt, Nickel, Yttrium, Zirkon, Niob, Molybdän, Technetium, Hafnium, Wolfram, oder eine Legierung aus mindestens zwei der zuvor genannten Metallen.The metal layer can contain at least one of the following metals: platinum, gold, silver, titanium, tantalum, palladium, bismuth, indium, chromium, vanadium, manganese, iron, cobalt, nickel, yttrium, zirconium, niobium, molybdenum, technetium, hafnium, Tungsten, or an alloy of at least two of the aforementioned metals.
Die Trennschicht kann eine elektrisch isolierende Trennschicht und/oder eine Schicht mit eine großen Dielektrizitätskonstante und/oder eine ferroelektrische Schicht sein.The separating layer can be an electrically insulating separating layer and / or a layer with a large dielectric constant and / or a ferroelectric layer.
Insbesondere kann die Trennschicht SBT, Siliziumdioxid, und/oder BST enthalten.In particular, the separating layer can contain SBT, silicon dioxide, and / or BST.
Ferner ist es gemäß einer Ausgestaltung der Erfindung vorgesehen, dass der Drain-Bereich und/oder der Source-Bereich und/oder der Gate-Bereich Metall aufweisen, beispielsweise eine Metallelektrode.Furthermore, it is provided according to an embodiment of the invention that the drain region and / or the source region and / or the gate region comprise metal, for example a metal electrode.
Als Metall für die Metallelektrode bzw. die Metallelektroden können die gleichen Metalle verwendet werden wie für die Me- tallschicht, d.h. die Metallelektrode bzw. die Metallelektroden können enthalten:The same metals can be used as the metal for the metal electrode or the metal electrodes as for the metal layer, i.e. the metal electrode or the metal electrodes can contain:
Platin, Gold, Silber, Titan, Tantal, Palladium, Wismut, Indium, oder eine Legierung aus mindestens zwei der zuvor genannten Metallen.Platinum, gold, silver, titanium, tantalum, palladium, bismuth, indium, or an alloy of at least two of the aforementioned metals.
Es können j edoch auch andere Metalle als Metallelektroden eingesetzt werden. Aufgrund der hohen Leitfähigkeit der entsprechenden Anschlüsse, d.h. Elektroden des Feldeffekttransistors wird die gesamte Leitfähigkeit des Feldeffekttransistors gemäß dieser Aus- gestaltung der Erfindung weiter erhöht, wodurch die Geschwindigkeit beim Umschalten des Feldeffekttransistors von einem leitenden Zustand in einen sperrenden Zustand weiter erheblich erhöht wird.However, metals other than metal electrodes can also be used. Due to the high conductivity of the corresponding connections, ie electrodes of the field effect transistor, the overall conductivity of the field effect transistor is further increased in accordance with this embodiment of the invention, whereby the speed when switching the field effect transistor from a conductive state to a blocking state is further increased considerably.
Aufgrund der hohen Schaltgeschwindigkeit eignet sich der Feldeffekttransistor somit insbesondere sehr gut für Hochfrequenzanwendungen.Due to the high switching speed, the field effect transistor is particularly well suited for high-frequency applications.
Der Drain-Bereich und der Source-Bereich können auf dem Sub- strat auf bekannte Weise, beispielsweise mittels vorgebbarer Dotierung von Ladungsträgern, Elektronen oder Löchern, gebildet werden.The drain region and the source region can be formed on the substrate in a known manner, for example by means of predeterminable doping of charge carriers, electrons or holes.
Die Metallschicht kann mittels eines geeigneten Abscheidever- fahren aus der Gasphase (Chemical Vapour Deposition, CVD-The metal layer can be separated from the gas phase by means of a suitable deposition process (chemical vapor deposition, CVD).
Verfahren) , eines Aufdampf-Verfahrens, eines Sputter-Verfah- rens oder eines Atomic-Layer-Deposition-Verfahrens aufgetragen werden.Process), a vapor deposition process, a sputtering process or an atomic layer deposition process.
Die oben dargestellten Ausgestaltungen der Erfindung bezüglich des Feldeffekttransistors betreffen ebenso das Verfahren zum Herstellen des Feldeffekttransistors.The embodiments of the invention described above with respect to the field effect transistor also relate to the method for producing the field effect transistor.
Ausführungsbeispiele der Erfindung sind in den Figuren darge- stellt und werden im weiteren näher erläutert.Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.
Es zeigenShow it
Figur 1 einen Querschnitt durch einen Feldeffekttransistor gemäß einem ersten Ausführungsbeispiel der Erfindung; Figur 2 einen Querschnitt durch einen Feldeffekttransistor gemäß einem zweiten Ausführungsbeispiel der Erfindung;1 shows a cross section through a field effect transistor according to a first embodiment of the invention; Figure 2 shows a cross section through a field effect transistor according to a second embodiment of the invention;
Figur 3 einen Querschnitt durch einen Feldeffekttransistor gemäß einem dritten Ausführungsbeispiel der Erfindung.Figure 3 shows a cross section through a field effect transistor according to a third embodiment of the invention.
Fig.l zeigt einen Feldeffekttransistor 100 gemäß einem ersten Ausführungsbeispiel der Erfindung.Fig.l shows a field effect transistor 100 according to a first embodiment of the invention.
Der Feldeffekttransistor 100 weist ein Substrat 101 aus elektrisch nicht leitendem Material, das heißt aus einem elektrisch isolierendem Material, gemäß dem ersten Ausführungs- beispiel aus Siliziumdioxid Siθ2 oder Aluminiumoxid AI2O3, auf.The field effect transistor 100 has a substrate 101 made of electrically non-conductive material, that is to say made of an electrically insulating material, according to the first exemplary embodiment made of silicon dioxide SiO 2 or aluminum oxide Al 2 O 3 .
In einem Abstand von 1 nm bis 1000 nm voneinander sind eine erste Metallelektrode 102 und eine zweite Metallelektrode 103 auf dem Substrat 101 mittels eines CVD-Verfahrens, eines Sputter-Verfahrens oder eines Aufdampf-Verfahrens aufgebracht.A first metal electrode 102 and a second metal electrode 103 are applied to the substrate 101 at a distance of 1 nm to 1000 nm from one another by means of a CVD method, a sputtering method or a vapor deposition method.
Die erste Metallelektrode 102 und die zweite Metallelektrode 103 können aus Platin oder aus Titan hergestellt werden. Alternativ können beliebige metallische Legierungen oder Metalle verwendet werden zum Bilden der ersten Metallelektrode 102 oder der zweiten Metallelektrode 103.The first metal electrode 102 and the second metal electrode 103 may be made of platinum or titanium. Alternatively, any metallic alloy or metal can be used to form the first metal electrode 102 or the second metal electrode 103.
Die erste Metallelektrode 102 dient als Source-Bereich des Feldeffekttransistors 100 und die zweite Metallelektrode 103 dient als Drain-Bereich des Feldeffekttransistors 100.The first metal electrode 102 serves as the source region of the field effect transistor 100 and the second metal electrode 103 serves as the drain region of the field effect transistor 100.
Zwischen der ersten Metallelektrode 102 und der zweiten Me- tallelektrode 103 ist eine monoatomare oder mehratomare Me- tallschicht 104 aus Platin mittels eines geeigneten CVD- Verfahrens abgeschieden. Die Metallschicht 104 ist mit der ersten Metallelektrode 102 und mit der zweiten Metallelektrode 103 elektrisch gekoppelt und bildet anschaulich einen Kanalbereich innerhalb des Fel- deffekttransistors 100.A monoatomic or multi-atomic metal layer 104 made of platinum is deposited between the first metal electrode 102 and the second metal electrode 103 by means of a suitable CVD method. The metal layer 104 is electrically coupled to the first metal electrode 102 and to the second metal electrode 103 and clearly forms a channel region within the field defect transistor 100.
Die erste Metallelektrode 102 und die zweite Metallelektrode 103 weisen jeweils eine Breite b, in Fig.l symbolisiert jeweils durch einen Doppelpfeil 105,106 von 1 nm bis 100 nm auf. In diesem Zusammenhang ist darauf hinzuweisen, dass die Breiten der Metallelektrσden 102, 103 nicht gleich sein müssen.The first metal electrode 102 and the second metal electrode 103 each have a width b, symbolized in FIG. 1 by a double arrow 105, 106 from 1 nm to 100 nm. In this connection it should be pointed out that the widths of the metal electrodes 102, 103 need not be the same.
Der Kanalbereich, d.h. die Metallschicht 104, weist eine Flä-The channel area, i.e. the metal layer 104 has a surface
2 2 ehe von 1 x 1 nm bis 1000 x 1000 nm auf.2 2 before from 1 x 1 nm to 1000 x 1000 nm.
Auf der Metallschicht 104 wird in einem weiteren Verfahrenschritt eine elektrisch isolierende Trennschicht 107 aus Siliziumdioxid oder Siliziumnitrid Si3N4 aufgebracht mittels eines CVD-Verfahrens, eines Sputter-Verfahrens oder eines Aufdampf-Verfahrens .In a further process step, an electrically insulating separating layer 107 made of silicon dioxide or silicon nitride Si 3 N4 is applied to the metal layer 104 by means of a CVD process, a sputtering process or a vapor deposition process.
In die Trennschicht 107 oder alternativ auf der Trennschicht 107 ist in einem Abstand p zu der Oberfläche des Kanalbe- reichs, d.h. zu der Oberfläche der Metallschicht 104, symbolisiert in Fig.l durch einen weiteren Doppelpfeil 108 in einem Bereich von 1 nm bis 50 nm eine einen Gate-Bereich bildende Gateelektrode 109 eingebracht bzw. aufgebracht.In the separating layer 107 or alternatively on the separating layer 107 at a distance p to the surface of the channel region, i.e. to the surface of the metal layer 104, symbolized in FIG. 1 by a further double arrow 108 in a range from 1 nm to 50 nm, a gate electrode 109 forming or forming a gate region is introduced or applied.
Auch die Gateelektrode 109 kann aus den oben genannten Metallen oder Metalllegierungen hergestellt werden, aus denen die erste Metallelektrode 102 oder die zweite Metallelektrode 103 gebildet werden können.The gate electrode 109 can also be produced from the metals or metal alloys mentioned above, from which the first metal electrode 102 or the second metal electrode 103 can be formed.
Über der Trennschicht 107 ist ferner in einem letzten Schritt zum Schutz des Feldeffekttransistors 100 eine weitere isolie- rende Schicht 110 aufgebracht, die beispielsweise Siliziumdioxid oder Siliziumnitrid aufweist.In a last step to protect the field effect transistor 100, a further insulated Rende layer 110 applied, for example, silicon dioxide or silicon nitride.
Fig.2 zeigt einen Feldeffekttransistor 200 gemäß einem zwei- ten Ausführungsbeispiel der Erfindung.2 shows a field effect transistor 200 according to a second exemplary embodiment of the invention.
Elemente des Feldeffekttransistors 200 gemäß dem zweiten Aus- führungsbeispiel, die gleich sind den Elementen des Feldeffekttransistors 100 gemäß dem ersten Ausführungsbeispiel, werden mit dem gleichen Bezugszeichen bezeichnet.Elements of the field effect transistor 200 according to the second exemplary embodiment, which are the same as the elements of the field effect transistor 100 according to the first exemplary embodiment, are denoted by the same reference symbols.
Der Feldeffekttransistor 200 gemäß dem zweiten Ausführungsbeispiel ist im wesentlichen gleich dem Feldeffekttransistor 100 gemäß dem ersten Ausführungsbeispiel.The field effect transistor 200 according to the second embodiment is substantially the same as the field effect transistor 100 according to the first embodiment.
Somit sind auch die Herstellungsverfahren und die gewählten Dimensionierungen zum Herstellen des Feldeffekttransistors 200 gleich denen des Feldeffekttransistors 100, wie im Zusammenhang mit dem ersten Ausführungsbeispiel beschrieben.Thus, the manufacturing method and the selected dimensions for manufacturing the field effect transistor 200 are the same as those of the field effect transistor 100, as described in connection with the first embodiment.
Der Feldeffekttransistor 200 gemäß dem zweiten Ausführungsbeispiel unterscheidet sich vom Feldeffekttransistor 100 gemäß dem ersten Ausführungsbeispiel insbesondere darin, dass in dem Substrat 101 eine weitere Gateelektrode 201 als Gate- Bereich vorgesehen ist, im weiteren bezeichnet als zweite Gateelektrode 201.The field effect transistor 200 according to the second exemplary embodiment differs from the field effect transistor 100 according to the first exemplary embodiment in particular in that a further gate electrode 201 is provided as the gate region in the substrate 101, hereinafter referred to as the second gate electrode 201.
Die erste Gateelektrode 109 ist mit der unterhalb des Kanalbereichs 104 angeordneten zweiten Gateelektrode 201, die von einer unteren Oberfläche 202 des Kanalbereichs 104 in einem Abstand von 1 nm bis 50 nm, symbolisiert in Fig.2 durch einen Pfeil 203, elektrisch gekoppelt.The first gate electrode 109 is electrically coupled to the second gate electrode 201 arranged below the channel region 104, which is spaced from a lower surface 202 of the channel region 104 at a distance of 1 nm to 50 nm, symbolized in FIG. 2 by an arrow 203.
Dies führt dazu, dass bei Ansteuerung der ersten Gateelektro- de 109, das heißt bei Anlegen eines elektrischen Potentials an die erste Gateelektrode 109, ein entsprechendes elektri- sches Potential auch an die zweite Gateelektrode 201 angelegt wird.As a result, when the first gate electrode 109 is activated, that is to say when an electrical potential is applied to the first gate electrode 109, a corresponding electrical cal potential is also applied to the second gate electrode 201.
Anschaulich bilden somit die erste Gateelektrode 109 und die zweite Gateelektrode 201 eine sogenannte Dual-Gate-Anordnung in dem Feldeffekttransistor 200.Clearly, the first gate electrode 109 and the second gate electrode 201 thus form a so-called dual gate arrangement in the field effect transistor 200.
Die zweite Gateelektrode 201 wird gemäß diesem Ausführungsbeispiel gemäß einem Dual-Damascene-Prozess in das Substrat 101 eingebettet.According to this exemplary embodiment, the second gate electrode 201 is embedded in the substrate 101 according to a dual damascene process.
Dies bedeutet, dass die Struktur für die zweite Gateelektrode 201 in das Substrat 101 geätzt wird und anschließend das Metall, aus dem die zweite Gateelektrode 201 gebildet werden soll, abgeschieden wird derart, dass die für die zweite Gateelektrode 201 geätzte Struktur zumindest vollständig mit dem abgeschiedenen Metall gefüllt ist. Eventuell über die Struktur überstehendes Metall wird mittels eines chemisch mechanischen Polierverfahrens (CMP-Verfahren) entfernt. An- schließend erfolgt wiederum eine entsprechende Abscheidung des gewünschten Oxids.This means that the structure for the second gate electrode 201 is etched into the substrate 101 and then the metal from which the second gate electrode 201 is to be formed is deposited in such a way that the structure etched for the second gate electrode 201 is at least completely identical to the deposited one Metal is filled. Any metal protruding from the structure is removed using a chemical mechanical polishing process (CMP process). The desired oxide is then again deposited accordingly.
Fig.3 zeigt einen Feldeffekttransistor 300 gemäß einem dritten Ausführungsbeispiel der Erfindung.3 shows a field effect transistor 300 according to a third exemplary embodiment of the invention.
Der Feldeffekttransistor 300 gemäß dem dritten Ausführungsbeispiel entspricht im wesentlichen dem Feldeffekttransistor 100 gemäß dem ersten Ausführungsbeispiel.The field effect transistor 300 according to the third exemplary embodiment essentially corresponds to the field effect transistor 100 according to the first exemplary embodiment.
Gleiche Komponenten des Feldeffekttransistors 300 gemäß dem dritten Ausführungsbeispiel werden mit gleichen Bezugszeichen versehen wie die entsprechenden Komponenten des Feldeffekttransistors 100 gemäß dem ersten Ausführungsbeispiel.The same components of the field effect transistor 300 according to the third embodiment are provided with the same reference numerals as the corresponding components of the field effect transistor 100 according to the first embodiment.
Der Feldeffekttransistor 300 gemäß dem dritten Ausführungsbeispiel unterscheidet sich von dem Feldeffekttransistor 100 gemäß dem ersten Ausführungsbeispiel insbesondere dadurch, dass auf der Metallschicht 104 eine elektrisch isolierende Schicht 301 mit hoher Dielektrizitätskonstante, d.h. mit einer Dielektrizitätskonstante im Bereich von 1 bis 1000 oder eine ferroelektrische Schicht 301 aufgebracht.The field effect transistor 300 according to the third exemplary embodiment differs from the field effect transistor 100 according to the first exemplary embodiment in particular in that that an electrically insulating layer 301 with a high dielectric constant, ie with a dielectric constant in the range from 1 to 1000, or a ferroelectric layer 301 is applied to the metal layer 104.
Die Schicht 301 ist ganzflächig über dem Kanalbereich aufgebracht mittels eines CVD-Verfahrens eines Sputter-Verfahrens oder eines Aufdampf-Verfahrens .The layer 301 is applied over the entire area over the channel region by means of a CVD method, a sputtering method or a vapor deposition method.
Die Schicht 301 ist beispielsweise aus BST oder SBT hergestellt.Layer 301 is made of BST or SBT, for example.
Die in Fig.3 mit einem Doppelpfeil 302 symbolisierte Dicke der Schicht 301 beträgt gemäß dem dritten Ausführungsbeispiel 1 nm bis 50 nm.The thickness of the layer 301 symbolized in FIG. 3 by a double arrow 302 is 1 nm to 50 nm according to the third exemplary embodiment.
Auf der Schicht 301 ist die erste Gateelektrode 109 aufgebracht.The first gate electrode 109 is applied to the layer 301.
In einem letzten Schritt wird, wie gemäß den vorangegangenen Ausführungsbeispielen, eine isolierende Trennschicht 107 auf dem sich gemäß den vorangegangenen Schritten ergebenden Element aufgebracht .In a last step, as in the previous exemplary embodiments, an insulating separating layer 107 is applied to the element resulting in the previous steps.
Gemäß eines vierten Ausführungsbeispiels ist vorgesehen, dass für die Anordnung gemäß dem dritten Ausführungsbeispiel ebenfalls eine zweite Gateelektrode (nicht dargestellt) vorgesehen ist, die mit der ersten Gateelektrode 109 elektrisch gekoppelt ist. In diesem Dokument sind folgende Veröffentlichungen zitiert:According to a fourth exemplary embodiment, it is provided that a second gate electrode (not shown) is also provided for the arrangement according to the third exemplary embodiment, which is electrically coupled to the first gate electrode 109. The following publications are cited in this document:
[1] R. Müller, Bauelemente der Halbleiterelektronik, Springer Verlag, erste Auflage, ISBN 3-540-06224-6, S. 130 - 157, 1973;[1] R. Müller, Components of Semiconductor Electronics, Springer Verlag, first edition, ISBN 3-540-06224-6, pp. 130 - 157, 1973;
[2] E.S. Snow et al., A metal/oxide tunneling transistor, Applied Physics Letters, Vol. 72, Nr. 23, S. 3071 - 3073, June 1998;[2] E.S. Snow et al., A metal / oxide tunneling transistor, Applied Physics Letters, Vol. 72, No. 23, pp. 3071-3073, June 1998;
[3] G. Martinez-Arizala et al., Coulo b-glass-like behaviour of ultrathin films of metals, Physical Review B, Vol. 57, Nr. 2, S. 670 - 672, January 1998;[3] G. Martinez-Arizala et al., Coulo b-glass-like behavior of ultrathin films of metals, Physical Review B, Vol. 57, No. 2, pp. 670-672, January 1998;
[4] Z. Ovadyahu und M. Pollak, Disorder and Magnetic field[4] Z. Ovadyahu and M. Pollak, Disorder and Magnetic field
Dependence of Slow Electronic Relaxation, Physical Review Letters, Vol. 79, Nr. 3, S. 459 - 462, July 1997. Dependence of Slow Electronic Relaxation, Physical Review Letters, Vol. 79, No. 3, pp. 459 - 462, July 1997.

Claims

Patentansprüche claims
1. Feldeffekttransistor, mit1. Field effect transistor, with
• einem elektrisch nicht leitenden Substrat, • einem Drain-Bereich,An electrically non-conductive substrate, a drain area,
• einem Source-Bereich,A source area,
• mit einem Kanalbereich zwischen dem Drain-Bereich und dem Source-Bereich,With a channel area between the drain area and the source area,
• mit einem Gate-Bereich, mit dem der Kanalbereich gesteu- ert werden kann,With a gate area with which the channel area can be controlled,
• wobei der Kanalbereich eine Metallschicht aufweist.• The channel area has a metal layer.
2. Feldeffekttransistor nach Anspruch 1, mit einem zweiten Gate-Bereich, mit dem der Kanalbereich ge- steuert werden kann.2. Field effect transistor according to claim 1, with a second gate region with which the channel region can be controlled.
3. Feldeffekttransistor nach Anspruch 1 oder 2, bei dem die Metallschicht eine oder mehrere Lagen von Metallatomen aufweist.3. Field effect transistor according to claim 1 or 2, wherein the metal layer has one or more layers of metal atoms.
4. Feldeffekttransistor nach einem der Ansprüche 1 bis 3, bei dem die Metallschicht zumindest eines der folgenden Metalle enthält:4. Field effect transistor according to one of claims 1 to 3, wherein the metal layer contains at least one of the following metals:
• Platin, • Gold,• platinum, • gold,
• Silber,• silver,
• Titan,Titanium,
• Tantal,• tantalum,
• Palladium, • Wismut,• palladium, • bismuth,
• Indium,Indium,
• Chrom,• chrome,
• Vanadium,Vanadium,
• Mangan, • Eisen,• manganese, • iron,
• Kobalt,Cobalt,
• Nickel, Yttrium, Zirkon, Niob, Molybdän, Technetiu , Hafnium, Wolfram, oder eine Legierung aus mindestens zwei der zuvor genannten Metallen.Nickel, Yttrium, zircon, niobium, molybdenum, technetiu, hafnium, tungsten, or an alloy of at least two of the aforementioned metals.
5. Feldeffekttransistor nach einem der Ansprüche 1 bis 4, bei dem die Trennschicht eine elektrisch isolierende Schicht ist.5. Field effect transistor according to one of claims 1 to 4, wherein the separating layer is an electrically insulating layer.
6. Feldeffekttransistor nach einem der Ansprüche 1 bis 5, bei dem die Trennschicht eine Schicht mit einer großen Dielektrizitätskonstante ist.6. Field effect transistor according to one of claims 1 to 5, wherein the separating layer is a layer with a large dielectric constant.
7. Feldeffekttransistor nach einem der Ansprüche 1 bis 6, bei dem die Trennschicht eine ferroelektrische Schicht ist.7. Field effect transistor according to one of claims 1 to 6, wherein the separating layer is a ferroelectric layer.
8. Feldeffekttransistor nach einem der Ansprüche 1 bis 7, bei dem der Drain-Bereich und/oder der Source-Bereich und/oder der Gate-Bereich Metall aufweist bzw. aufweisen.8. Field effect transistor according to one of claims 1 to 7, in which the drain region and / or the source region and / or the gate region comprises or have metal.
9. Verfahren zum Herstellen eines Feldeffekttransistors,9. Method for producing a field effect transistor,
• bei dem auf einem Substrat ein Drain-Bereich und ein Source-Bereich gebildet werden,In which a drain region and a source region are formed on a substrate,
• bei dem zwischen dem Drain-Bereich und dem Source- Bereich eine einen Kanalbereich bildende Metallschicht auf dem Substrat aufgebracht wird,In which a metal layer forming a channel region is applied to the substrate between the drain region and the source region,
• bei dem auf der Metallschicht und zwischen dem Drain- Bereich und dem Source-Bereich eine Trennschicht aufgebracht wird, • bei dem auf der Trennschicht ein Gate-Bereich gebildet wird, wobei der Gate-Bereich durch die Trennschicht von dem Drain-Bereich, dem Source-Bereich und dem Kanalbe- reich getrennt ist derart, dass der Kanalbereich über den Gate-Bereich steuerbar ist. • in which a separating layer is applied to the metal layer and between the drain region and the source region, • in which a gate region is formed on the separating layer, the gate region being separated from the drain region by the separating layer Source area and the channel is richly separated such that the channel area can be controlled via the gate area.
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