JPS62239568A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS62239568A JPS62239568A JP61083524A JP8352486A JPS62239568A JP S62239568 A JPS62239568 A JP S62239568A JP 61083524 A JP61083524 A JP 61083524A JP 8352486 A JP8352486 A JP 8352486A JP S62239568 A JPS62239568 A JP S62239568A
- Authority
- JP
- Japan
- Prior art keywords
- drive output
- polysilicon
- operates
- high drive
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000872 buffer Substances 0.000 abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- 229920005591 polysilicon Polymers 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特にＭＯ８トラン
ジスタからなる高駆動出力バッファが複数同時動作する
場合に生じる電源ノイズの防止に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to prevention of power supply noise that occurs when a plurality of high-drive output buffers made of MO8 transistors operate simultaneously.
ＭＯ８半導体集積回路装置の高駆動出力バッファが、複
数同時動作する場合、電源にノイズを生じ、それが、電
源変動となり、誤動作の原因り１つになっていた。従来
この電源変動を、小さくｇさえるために、同時動作゛［
る複数の高駆動出力バッファの動作時間を少しずつずら
し、個々の高駆動出力バッファが動作する事による電源
ノイズが重複しないようにしていた。When a plurality of high-drive output buffers of an MO8 semiconductor integrated circuit device operate simultaneously, noise is generated in the power supply, which causes fluctuations in the power supply and is one of the causes of malfunctions. Conventionally, in order to keep this power supply fluctuation to a small value, simultaneous operation ゛[
The operating times of the multiple high drive output buffers were gradually shifted to avoid duplication of power supply noise caused by the operation of the individual high drive output buffers.
また、各高駆動出力バッファは例えば第３図に示ように
、アルミ配線４に７本のポリシリゲートＡ、Ｇが接続さ
れてにす、アルミ配線４のＺから信号が入ると、７本の
ポリシリゲートが一斉に動作する構成となっている。In addition, each high drive output buffer has, for example, seven polysilicon gates A and G connected to the aluminum wiring 4 as shown in FIG. are configured to operate simultaneously.
上述した従来の高駆動出力バッファの動作時間χずらす
電源ノイズ防止方法は５次のような欠点がある。The above-described conventional method for preventing power supply noise by shifting the operating time χ of a high drive output buffer has the following drawbacks.
まず第１に１つの高駆動出力バッファが動作した場合に
生じる電源ノイズは普通士ａｍＳ程度読くため１例えば
、３２個の高駆動出力バッファが。First of all, the power supply noise that occurs when one high drive output buffer operates is usually about 2 amS, so 1, for example, 32 high drive output buffers.
同時動作する場合１個々の高駆動出力バッファが生じる
電源ノイズの重ａをさけようとすると。When operating simultaneously, one attempts to avoid the power supply noise burden caused by individual high-drive output buffers.
３２個の高駆動出力バッファに各々十数ｍｓの遅夕！＆
乞設は順次動作させなければならない。そのため、ｌ爵
初めに励１′１する高駆動出力バッファと最後に動作す
る高駆動出力バッファの時間的ずれは。Each of the 32 high-drive output buffers has a delay of more than 10 ms! &
The arrangements must be operated in sequence. Therefore, the time difference between the high drive output buffer that is activated at the beginning and the high drive output buffer that is activated last is as follows.
五百ｎｓＫもなりもはや同時動作とは、言えなくなって
し！５という欠点がある。At 500 nsK, it can no longer be called simultaneous operation! There is a drawback of 5.
第２ ｔ’ｃ 、上記しｔ遅延を設けるためインバータ
回路などでこの遅延回路を作ると多数のインバータが必
要となり、その＾めに、占汀される＋ｆｉ潰が大さくな
り、こｎは半導体チップ面積の有効利用が固定されてマ
スタースライス方式のゲートアレイなどでは、ポリシリ
配線は、下池工桿で作られる友め、高妻励出力パッ７ア
であろうと、低駆動出力バッファあるいは入カパッフア
であろうと。2nd t'c To provide the t delay described above, if this delay circuit is constructed using an inverter circuit, a large number of inverters will be required, and the occupied +fi will become large. In gate arrays where the effective use of chip area is fixed and the master slice method is used, polysilicon interconnects can be used with low-drive output buffers or input buffers, whether they are made with Shimoike-Koji, Takatsuma excitation output buffers, etc. No matter what.
”ｆべてのバッファに遅延回路用ポリシリ配線ぞ用意し
なければならず、この事は、過酸的に半導本チップ面檀
σノ拡大？：まねくという欠点がある。It is necessary to prepare polysilicon wiring for delay circuits for all buffers, which has the drawback of increasing the semiconductor chip surface area due to overoxidation.
本発明の半導体果禎回路装置は、複数のゲート電極を有
するＭＯＳトランジスタの咳複数のゲート電極の少くと
も２つが直列に接続されていることを特徴とする。The semiconductor circuit device of the present invention is characterized in that at least two of the plurality of gate electrodes of a MOS transistor having a plurality of gate electrodes are connected in series.
次に本発明について、図面を参照し−ご説明する。 Next, the present invention will be explained with reference to the drawings.
アルミ配１ｌＩＱ！４によりポリシリゲート間がコンタ
クト５を介して接続さねている。第２図は第１図を等画
回路で示したものである。本発明では第１図に示すよう
に、ポリシリゲートの両端に、１対のコンタクトｆｆ：
設けてある。■（に信号が入ると、ｉず、ポリシリゲー
トＡが、動作し１次にポリシリゲートの抵抗成分で、あ
る時間−ｉｔ ＜ ｎでポリシリゲートＢが動作する。Aluminum layout 1lIQ! 4, the polysilicon gates are connected via contacts 5. FIG. 2 is an isometric circuit diagram of FIG. 1. In the present invention, as shown in FIG. 1, a pair of contacts ff:
It is provided. (2) When a signal is input to (, polysiligate A is activated, and first, due to the resistance component of the polysiligate, polysiligate B is activated for a certain time -it < n.
このように１．て、ポリシリゲートは、次々動作し、最
後に７番目・、ニポリシリゲートＧが動作する。今例え
ば１本発明の一実施例の第１図に示す高駆動出力バッフ
ァが７個同時動作した場合を考えると、実際に同時動作
するのは、１内々の高駆動出力バッファの中の１本のポ
リシリゲートであり、従って、７本のポリシリゲートが
同時動作する事になる。この事は、７本のポリシリゲー
トをもつ従来の高駆動出力バッファが１細動作した事と
、はぼ等価になる。In this way 1. The polysiligates operate one after another, and finally the seventh polysiligate G operates. For example, if we consider a case where seven high drive output buffers shown in FIG. 1 according to an embodiment of the present invention operate simultaneously, only one of the high drive output buffers actually operates simultaneously. Therefore, seven polysiligates operate simultaneously. This is approximately equivalent to one small operation of a conventional high drive output buffer having seven polysilicate gates.
本発明ケ用いた場合、又、ポリシリゲート本数が多くな
ればなるほど、その同時動作可能な、高駆動出力バッフ
ァの数が、ふえるのは明らかである。When the present invention is used, it is clear that as the number of polysilicate gates increases, the number of high drive output buffers that can operate simultaneously increases.
以上説明したように１本発明は、各高駆動出力バッファ
の複数のゲートを時間ケずらして駆動することにより、
高、駆動出力バッファを複数同時動作させる場合１個々
の高駆動出力バッファの動作時間をずら丁ことなく、電
源ノイズをＨさえて同時動作させる事ができるという効
果がある。又。As explained above, one aspect of the present invention is to drive multiple gates of each high drive output buffer with staggered times.
When a plurality of high drive output buffers are operated simultaneously, there is an advantage that the operation time of each high drive output buffer is not staggered, and the power supply noise can be suppressed to allow simultaneous operation. or.
その場合、特別な回路を一切用いていないため。In that case, no special circuit is used.
半導体チップの面積が有効利用できるという効果がある
。This has the effect that the area of the semiconductor chip can be used effectively.
第１図は本発明の一実施例の高駆動出力バッファの平面
図、第２図は、第１図の等価回路図、第３図は、従来の
高駆動出力バッファの平面図である。
１・・・・・・ソース、２・・・・・・ドレイン、３・
・・・・・ポリシリゲート、４・・・・・・アルミ配線
、５・・・・・・コンタクト。
代理人 弁理士 内 原 町″゛−；゛・１、・FIG. 1 is a plan view of a high drive output buffer according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is a plan view of a conventional high drive output buffer. 1... Source, 2... Drain, 3.
...Polysiligate, 4...Aluminum wiring, 5...Contact. Agent Patent Attorney Machi Uchihara ゛-；゛・１．・
Claims (1)
のゲート電極の少くとも２つが直列に接続されている事
を特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device, wherein at least two of the plurality of gate electrodes of a MOS transistor having a plurality of gate electrodes are connected in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61083524A JPS62239568A (en) | 1986-04-11 | 1986-04-11 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61083524A JPS62239568A (en) | 1986-04-11 | 1986-04-11 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62239568A true JPS62239568A (en) | 1987-10-20 |
Family
ID=13804866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61083524A Pending JPS62239568A (en) | 1986-04-11 | 1986-04-11 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62239568A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162893A (en) * | 1988-05-23 | 1992-11-10 | Fujitsu Limited | Semiconductor integrated circuit device with an enlarged internal logic circuit area |
| JP2005277378A (en) * | 2004-02-24 | 2005-10-06 | Seiko Instruments Inc | High-voltage operation field effect transistor, its bias circuit and its high-voltage circuit |
| JP2012004581A (en) * | 2004-02-24 | 2012-01-05 | Seiko Instruments Inc | High-voltage operation method of field effect transistor and bias circuit thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61277225A (en) * | 1985-05-31 | 1986-12-08 | Seiko Epson Corp | Output buffer circuit |
-
1986
- 1986-04-11 JP JP61083524A patent/JPS62239568A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61277225A (en) * | 1985-05-31 | 1986-12-08 | Seiko Epson Corp | Output buffer circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162893A (en) * | 1988-05-23 | 1992-11-10 | Fujitsu Limited | Semiconductor integrated circuit device with an enlarged internal logic circuit area |
| JP2005277378A (en) * | 2004-02-24 | 2005-10-06 | Seiko Instruments Inc | High-voltage operation field effect transistor, its bias circuit and its high-voltage circuit |
| JP2012004581A (en) * | 2004-02-24 | 2012-01-05 | Seiko Instruments Inc | High-voltage operation method of field effect transistor and bias circuit thereof |
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