JPS62234363A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62234363A JPS62234363A JP7781686A JP7781686A JPS62234363A JP S62234363 A JPS62234363 A JP S62234363A JP 7781686 A JP7781686 A JP 7781686A JP 7781686 A JP7781686 A JP 7781686A JP S62234363 A JPS62234363 A JP S62234363A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- polycrystalline silicon
- layer
- substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000010354 integration Effects 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本発明は、半導体基板内および基板上に能動素子のほか
に抵抗、コンデンサなどの受動素子が集積される半導体
集積回路に関する。The present invention relates to a semiconductor integrated circuit in which passive elements such as resistors and capacitors are integrated in and on a semiconductor substrate in addition to active elements.
半導体集積回路において、抵抗としては基板内に形成し
た異なる導電型の層による拡散抵抗が従来用いられてい
た。ところが、拡散抵抗は基板内に集積される他の素子
と電気的に絶縁するための分離領域を必要とすること、
また同一分離領域内に二つ以上の拡散抵抗が存在する場
合、抵抗間の絶縁のために所定の間隔をあける必要があ
ることから高集積化に対する障害となる。これに対し、
多結晶シリコン層によって抵抗を形成する場合は、この
多結晶シリコン層は基板上に酸化膜を介して形成するこ
とができるため、他の回路素子との間の分Ｍ ＳＫＩ域
を必要とせずに電気的に絶縁でき、集積回路の高集積化
に適している。しかしながら、多結晶シリコンは抵抗温
度係数が負であるため、例えばバイポーラＩＣにおいて
多く使用されるベースドライブ抵抗に多結晶シリコン抵
抗を適用した場合、高温になるとトランジスタのｈ Ｆ
！、の増大とベースドライブ抵抗の減少によるベース電
流の増大とから、相乗してコレクタ電流が増大するため
好ましくなかった。BACKGROUND ART In semiconductor integrated circuits, a diffused resistor formed by layers of different conductivity types formed in a substrate has conventionally been used as a resistor. However, diffused resistors require an isolation region to electrically insulate them from other elements integrated within the substrate.
Further, when two or more diffused resistors are present in the same isolation region, it is necessary to leave a predetermined distance between the resistors to insulate them, which becomes an obstacle to high integration. In contrast,
When forming a resistor using a polycrystalline silicon layer, this polycrystalline silicon layer can be formed on the substrate via an oxide film, so there is no need for a M SKI area between it and other circuit elements. It can be electrically insulated and is suitable for highly integrated circuits. However, polycrystalline silicon has a negative temperature coefficient of resistance, so if a polycrystalline silicon resistor is used as a base drive resistor, which is often used in bipolar ICs, the transistor's h F
! , and an increase in base current due to a decrease in base drive resistance, which is undesirable because the collector current increases synergistically.
本発明は、上述の問題を解決し、温度係数を任意の値に
することができ、また拡散抵抗に比して高集積化の可能
な抵抗を有する半導体集積回路を提供することを目的と
する。
（発明の要点］
本発明、半導体集積回路が半導体基板内に形成された異
なる導電型の層からなる拡散抵抗と、基板上に絶縁膜を
介して被着された多結晶シリコン層からなる膜抵抗とを
組合わせてなる抵抗を存するもので、拡散抵抗の温度係
数が正で、膜抵抗の温度係数が負であることから任意の
温度係数をもたせることができ、また基板内と基板上の
双方を利用するため高集積化が可能で上述の目的が達成
される。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a semiconductor integrated circuit having a resistance that can have a temperature coefficient of any value and can be highly integrated compared to a diffused resistance. . (Summary of the Invention) The present invention provides a semiconductor integrated circuit comprising a diffused resistor consisting of layers of different conductivity types formed within a semiconductor substrate, and a film resistor consisting of a polycrystalline silicon layer deposited on the substrate via an insulating film. Since the temperature coefficient of diffused resistance is positive and the temperature coefficient of film resistance is negative, it is possible to have any temperature coefficient, and it is possible to have any temperature coefficient both in the substrate and on the substrate. Since it uses , high integration is possible and the above purpose is achieved.
第１図は、本発明の一実施例を示し、シリコン基板ｌに
基板と異なる導電型の拡散層２を形成し、基板１の表面
を酸化膜で覆ったのち不純物を含む多結晶シリコン層４
を堆積し、つづいて表面を絶縁膜５で覆い、その開口部
で絶縁抵抗層２あるいは多結晶シリコン抵抗層４に接触
する端子型［６１゜６２、接続電極６３を設ける。この
実施例は、拡散抵抗層２の真上の酸化膜３の上に多結晶
シリコン抵抗層４を形成する立体構造で、膜抵抗を電極
６３により接続したものである。この構造により、負の
温度係数を有する多結晶シリコンからなる膜抵抗と正の
温度係数を有する拡散抵抗が直列抵抗されるため温度補
償ができる。しかも、立体構造により抵抗の占める面積
が小さくてすむため、高密度化が容易となり、今後の超
々ＬＳＩに有効な手段となる。
第２図は別の実施例を示し、第１図と共通の部分には同
一の符号が付されている。第２図＋ａ＋においては、基
板１を覆う薄い酸化膜３上に不純物をドープしていない
多結晶シリコンを全面に堆積したのち、フォトリソグラ
フィにより多結晶シリコン層４０を形成する０次いで基
板上からイオン注入すれば、第２ｌ−）に示すように、
自己整合により多結晶シリコン層４０の存在しない場所
に拡散抵抗層２が形成でき、同時に多結晶シリコン層４
０にイオン注入され、不純物が添加された多結晶シリコ
ン抵抗層４が得られる０図示しない電極により拡散抵抗
層２と多結晶シリコン抵抗層４を直列あるいは並列に接
続して任意の抵抗値をもつ抵抗を構成することができる
。膜抵抗層４の下の拡散抵抗層２が存在しない領域が、
抵抗層２の間の絶縁のために必要な領域として役立ち、
基板面積が有効に利用できるため高集積化に有効である
。
第３図には、＆１１１１により多結晶シリコン抵抗、ｍ
１２により拡散抵抗、また線１３により両者の直列接続
抵抗、線１４により並列接ｔＩｉ抵抗の温度特性を示す
、 ｍ１３．１４の傾きは、両者の比率を適当に選ぶこ
とにより変化するので、任意の温度係数を得ることがで
きる。FIG. 1 shows an embodiment of the present invention, in which a diffusion layer 2 of a conductivity type different from that of the substrate is formed on a silicon substrate 1, the surface of the substrate 1 is covered with an oxide film, and then a polycrystalline silicon layer 4 containing impurities is formed.
Then, the surface is covered with an insulating film 5, and a terminal-type connecting electrode 63 is provided to contact the insulating resistance layer 2 or polycrystalline silicon resistance layer 4 at the opening. This embodiment has a three-dimensional structure in which a polycrystalline silicon resistance layer 4 is formed on an oxide film 3 directly above a diffused resistance layer 2, and a film resistance is connected by an electrode 63. With this structure, temperature compensation can be achieved because a film resistor made of polycrystalline silicon having a negative temperature coefficient and a diffused resistor having a positive temperature coefficient are resisted in series. Furthermore, because the area occupied by the resistor can be reduced due to the three-dimensional structure, it is easy to increase the density, and this will be an effective means for future ultra-super LSIs. FIG. 2 shows another embodiment, in which parts common to those in FIG. 1 are given the same reference numerals. In FIG. 2+a+, polycrystalline silicon that is not doped with impurities is deposited on the entire surface of the thin oxide film 3 that covers the substrate 1, and then a polycrystalline silicon layer 40 is formed by photolithography. If injected, as shown in 2nd l-),
Due to self-alignment, the diffused resistance layer 2 can be formed in a place where the polycrystalline silicon layer 40 does not exist, and at the same time the polycrystalline silicon layer 4 can be formed.
A polycrystalline silicon resistance layer 4 with impurities added by ion implantation is obtained by connecting the diffused resistance layer 2 and the polycrystalline silicon resistance layer 4 in series or parallel with an electrode (not shown) to have an arbitrary resistance value. A resistor can be configured. The region under the membrane resistance layer 4 where the diffused resistance layer 2 does not exist is
serves as the necessary area for insulation between the resistive layers 2;
Since the board area can be used effectively, it is effective for high integration. In Figure 3, polycrystalline silicon resistance, m
12 shows the temperature characteristics of the diffused resistance, line 13 shows the series connection resistance of both, and line 14 shows the temperature characteristics of the parallel connection tIi resistance.The slope of m13.14 can be changed by appropriately selecting the ratio of the two, so it can be set to any desired value. Temperature coefficient can be obtained.
本発明によれば、半導体集積回路の抵抗を多結晶シリコ
ン膜抵抗と拡散抵抗により形成するので、任意の抵抗温
度係数が得られ、温度特性の改善が容易に行える。また
基板内と基板上の双方を利用して抵抗を形成するので、
高集積化に対して有効で、チップ面積の減少が可能にな
る。According to the present invention, since the resistor of the semiconductor integrated circuit is formed by a polycrystalline silicon film resistor and a diffused resistor, an arbitrary resistance temperature coefficient can be obtained, and the temperature characteristics can be easily improved. Also, since the resistance is formed using both inside and on the substrate,
This is effective for high integration and allows for a reduction in chip area.
第１図は本発明の一実施例を示す部分断面図、第２図は
異なる実施例の抵抗形成工程を順次示す断面図、第３図
は各種抵抗の温度特性線図である。FIG. 1 is a partial cross-sectional view showing one embodiment of the present invention, FIG. 2 is a cross-sectional view sequentially showing the resistor forming process of different embodiments, and FIG. 3 is a temperature characteristic diagram of various resistors.
Claims (1)
る拡散抵抗と、基板上に絶縁膜を介して被着された多結
晶シリコン層からなる膜抵抗とを組合わせてなる抵抗を
有することを特徴とする半導体集積回路。1) Having a resistance made by combining a diffused resistance made of layers of different conductivity types formed in a semiconductor substrate and a film resistance made of a polycrystalline silicon layer deposited on the substrate via an insulating film. A semiconductor integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7781686A JPS62234363A (en) | 1986-04-04 | 1986-04-04 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7781686A JPS62234363A (en) | 1986-04-04 | 1986-04-04 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62234363A true JPS62234363A (en) | 1987-10-14 |
Family
ID=13644550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7781686A Pending JPS62234363A (en) | 1986-04-04 | 1986-04-04 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62234363A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01309365A (en) * | 1988-06-07 | 1989-12-13 | Nec Ic Microcomput Syst Ltd | Integrated circuit |
| JPH03101262A (en) * | 1989-09-14 | 1991-04-26 | Fuji Electric Co Ltd | Built-in resistance for integrated circuit device |
| US5622901A (en) * | 1990-02-08 | 1997-04-22 | Nippondenso Co., Ltd. | Method of forming a semiconductor strain sensor |
| JP2006190709A (en) * | 2004-12-28 | 2006-07-20 | Mitsumi Electric Co Ltd | Semiconductor device |
| US7659176B2 (en) | 2005-01-06 | 2010-02-09 | International Business Machines Corporation | Tunable temperature coefficient of resistance resistors and method of fabricating same |
-
1986
- 1986-04-04 JP JP7781686A patent/JPS62234363A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01309365A (en) * | 1988-06-07 | 1989-12-13 | Nec Ic Microcomput Syst Ltd | Integrated circuit |
| JPH03101262A (en) * | 1989-09-14 | 1991-04-26 | Fuji Electric Co Ltd | Built-in resistance for integrated circuit device |
| US5622901A (en) * | 1990-02-08 | 1997-04-22 | Nippondenso Co., Ltd. | Method of forming a semiconductor strain sensor |
| JP2006190709A (en) * | 2004-12-28 | 2006-07-20 | Mitsumi Electric Co Ltd | Semiconductor device |
| US7659176B2 (en) | 2005-01-06 | 2010-02-09 | International Business Machines Corporation | Tunable temperature coefficient of resistance resistors and method of fabricating same |
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