JP2006190709A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006190709A
JP2006190709A JP2004381864A JP2004381864A JP2006190709A JP 2006190709 A JP2006190709 A JP 2006190709A JP 2004381864 A JP2004381864 A JP 2004381864A JP 2004381864 A JP2004381864 A JP 2004381864A JP 2006190709 A JP2006190709 A JP 2006190709A
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resistance element
element portion
polysilicon
semiconductor device
pattern
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Naoki Miyasaka
直樹 宮坂
Shigeo Tamura
成郎 田村
Yasuhisa Ishikawa
泰久 石川
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Mitsumi Electric Co Ltd
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Mitsumi Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To improve the space efficiency of the part of a resistance element in a CMOS semiconductor device. <P>SOLUTION: A diffusion resistance element RA having a positive temperature characteristic and a polysilicon resistance element RB having a negative temperature characteristic are lapped planely with a silicon oxide film 50 set between so that the diffusion resistance element RA is a lower side and the polysilicon resistance element RB is an upper side. The diffusion resistance element RA and the polysilicon resistance element RB are electrically connected in series. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置に関する。   The present invention relates to a semiconductor device.

図６は従来のＣＭＯＳ半導体装置１を示す。ＣＭＯＳ半導体装置１は、シリコン基板２上に、ＣＭＯＳ半導体素子及び抵抗素子等が密に作り込んである構成である。このうち、抵抗素子の部分についてみると、所望の温度特性となるように、例えば零の温度特性となるように、或いは、所望の温度特性となるように、正の温度特性を有する拡散抵抗素子部ＲＡと負の温度特性を有するポリシリコン抵抗素子部ＲＢとが、平面図上並んだ配置で、且つ、直列に接続されている構成である。ここで、正の温度特性とは温度が上昇すると抵抗値が上がる特性であり、負の温度特性とは温度が上昇すると抵抗値が下がる特性であり、零の温度特性とは温度が上昇しても抵抗値が変化しない特性である。
特開平５−９０５０２号公報 FIG. 6 shows a conventional CMOS semiconductor device 1. The CMOS semiconductor device 1 has a configuration in which CMOS semiconductor elements, resistance elements, and the like are densely formed on a silicon substrate 2. Among these, the resistance element portion has a positive temperature characteristic so as to achieve a desired temperature characteristic, for example, a zero temperature characteristic or a desired temperature characteristic. The portion RA and the polysilicon resistance element portion RB having negative temperature characteristics are arranged side by side on the plan view and connected in series. Here, the positive temperature characteristic is a characteristic in which the resistance value increases as the temperature rises, the negative temperature characteristic is a characteristic in which the resistance value decreases as the temperature rises, and the zero temperature characteristic is a temperature rise. The resistance value does not change.
JP-A-5-90502

しかし、拡散抵抗素子部ＲＡとポリシリコン抵抗素子部ＲＢとが平面図上並んだ配置であるため、スペース効率が良くなかった。このため、抵抗素子の数が増えてくると、その影響も徐々に大きくなって、ＣＭＯＳ半導体装置１の縦横のサイズの小型化を図る上で無視できないものとなってきている。   However, since the diffused resistor element RA and the polysilicon resistor element RB are arranged side by side on the plan view, the space efficiency is not good. For this reason, as the number of resistance elements increases, the influence gradually increases, and cannot be ignored in reducing the vertical and horizontal sizes of the CMOS semiconductor device 1.

また、拡散抵抗素子部ＲＡとポリシリコン抵抗素子部ＲＢとが平面図上並んだ配置である場合には、発熱源からの距離が相違し、拡散抵抗素子部ＲＡの温度とポリシリコン抵抗素子部ＲＢの温度とに差が出て、温度特性を設計通りにすることが出来ない場合も起こる。また、温度特性の変動を抑えるために、アルミ変更、トリミング等による合わせ込みを行っているため、レイアウト面積が大きくなっていた。   Further, when the diffusion resistance element portion RA and the polysilicon resistance element portion RB are arranged side by side in a plan view, the distance from the heat generation source is different, and the temperature of the diffusion resistance element portion RA and the polysilicon resistance element portion are different. There may be a case where there is a difference between the RB temperature and the temperature characteristics cannot be made as designed. Further, in order to suppress fluctuations in temperature characteristics, alignment is performed by changing aluminum, trimming, etc., so that the layout area is large.

そこで、本発明は、上記課題を解決した半導体装置を提供することを目的とする。   Therefore, an object of the present invention is to provide a semiconductor device that solves the above-described problems.

本発明は、抵抗素子が、
正又は負の温度特性を有する第１の抵抗素子部と、
該第１の抵抗素子部とは逆の温度特性を有する第２の抵抗素子部とを、
上下の配置で形成してあり、第１の抵抗素子部と第２の抵抗素子部とが重なっていることを特徴とする。 In the present invention, the resistance element is
A first resistance element portion having a positive or negative temperature characteristic;
A second resistance element portion having a temperature characteristic opposite to that of the first resistance element portion,
The first resistive element portion and the second resistive element portion are overlapped with each other.

本発明によれば、第１の抵抗素子部と第２の抵抗素子部とが並んで配置してある構成に比べてスペース効率の向上を図ることが出来る。   According to the present invention, space efficiency can be improved as compared with the configuration in which the first resistance element portion and the second resistance element portion are arranged side by side.

次に本発明の実施の形態について説明する。   Next, an embodiment of the present invention will be described.

［抵抗素子１２の概略構成］
図１は発明の実施例１になるＣＭＯＳ半導体装置１０を示す。Ｘ１−Ｘ２が長さ方向、Ｙ１−Ｙ２が幅方向、Ｚ１−Ｚ２が厚さ方向である。ＣＭＯＳ半導体装置１０は、シリコンチップ基板１１上に、ＣＭＯＳ半導体素子及び抵抗素子等が密に作り込んである構成である。このうち、抵抗素子１２の部分についてみると、温度による特性の変動が抑えられるように、第１の抵抗素子部であるところの正の温度特性を有する拡散抵抗素子部ＲＡと第２の抵抗素子部であるところの負の温度特性を有するポリシリコン抵抗素子部ＲＢとが、拡散抵抗素子部ＲＡが下側、ポリシリコン抵抗素子部ＲＢが上側とされて平面的に重なった配置で、且つ、電気的に直列に接続されている構成である。よって抵抗素子１２は従来に比較してスペース効率良く形成され、ＣＭＯＳ半導体装置１０のサイズＡ×Ｂは小さい。 [Schematic Configuration of Resistance Element 12]
FIG. 1 shows a CMOS semiconductor device 10 according to a first embodiment of the invention. X1-X2 is the length direction, Y1-Y2 is the width direction, and Z1-Z2 is the thickness direction. The CMOS semiconductor device 10 has a configuration in which CMOS semiconductor elements, resistance elements, and the like are densely formed on a silicon chip substrate 11. Among these, when the resistance element 12 is viewed, the diffused resistance element portion RA having the positive temperature characteristics and the second resistance element, which are the first resistance element portions, are suppressed so that the fluctuation of the characteristics due to temperature can be suppressed. The polysilicon resistance element portion RB having negative temperature characteristics, which is a portion, is arranged so that the diffusion resistance element portion RA is on the lower side and the polysilicon resistance element portion RB is on the upper side, and overlaps in a plane. It is the structure electrically connected in series. Therefore, the resistance element 12 is formed more efficiently than the conventional one, and the size A × B of the CMOS semiconductor device 10 is small.

［抵抗素子１２の構成］
図２及び図３は抵抗素子１２の部分を拡大して示す。図３は平面図であり、図２は図３中、II-II線に沿う断面図である。 [Configuration of Resistance Element 12]
2 and 3 show an enlarged portion of the resistance element 12. 3 is a plan view, and FIG. 2 is a cross-sectional view taken along line II-II in FIG.

拡散抵抗素子部ＲＡは、半導体装置基板１１の上面に形成してあり、Ｙ１−Ｙ２に長さＬ１の４本のＰ型拡散抵抗パターン２０がＸ１−Ｘ２方向に等ピッチＰ１で平行に並んでおり、隣同士のＰ型拡散抵抗パターン２０の両側の端が互い違いにコンタクト２１Ｙ１，２１Ｙ２でもって電気的に接続してある構成であり、ジグザク状となっている。２５は拡散抵抗素子部ＲＡの一端の端子であり、２６は拡散抵抗素子部ＲＡの他端の端子である。   The diffused resistor element RA is formed on the upper surface of the semiconductor device substrate 11, and four P-type diffused resistor patterns 20 having a length L1 are arranged in parallel at an equal pitch P1 in the X1-X2 direction in Y1-Y2. Further, both ends of the adjacent P-type diffused resistor pattern 20 are electrically connected by the contacts 21Y1 and 21Y2 alternately, and have a zigzag shape. Reference numeral 25 denotes a terminal at one end of the diffused resistor element RA, and reference numeral 26 denotes a terminal at the other end of the diffused resistor element RA.

各Ｐ型拡散抵抗パターン２０の両端にはＰ＋拡散されたＰ＋型拡散層２２，２３が形成してある。コンタクト２１Ｙ１，２１Ｙ２はＰ＋型拡散層２２，２３上に形成してあり、コンタクト２１Ｙ１，２１Ｙ２とＰ型拡散抵抗パターン２０との接続部分の電気抵抗が低くされている。   P + diffusion layers 22 and 23 diffused P + are formed at both ends of each P diffusion resistance pattern 20. The contacts 21Y1 and 21Y2 are formed on the P + type diffusion layers 22 and 23, and the electrical resistance of the connection portion between the contacts 21Y1 and 21Y2 and the P type diffusion resistance pattern 20 is lowered.

拡散抵抗素子部ＲＡのＰ型拡散抵抗パターン２０は、通常よりも厚いシリコン酸化膜５０で覆われている。シリコン酸化膜５０が通常よりも厚いことによって、拡散抵抗パターン２０とポリシリコンパターン４０とは確実に絶縁されて分離されている。   The P-type diffused resistor pattern 20 of the diffused resistor element RA is covered with a silicon oxide film 50 that is thicker than usual. Since the silicon oxide film 50 is thicker than usual, the diffused resistor pattern 20 and the polysilicon pattern 40 are reliably insulated and separated.

ポリシリコン抵抗素子部ＲＢは、シリコン酸化膜５０の上面に形成してあり、Ｙ１−Ｙ２に長さＬ２の４本のポリシリコンパターン４０がＸ１−Ｘ２方向に等ピッチＰ２で平行に並んでおり、隣同士のポリシリコンパターン４０の両側の端が互い違いにコンタクト４１Ｙ１，４１Ｙ２でもって電気的に接続してある構成であり、ジグザク状となっている。３５はポリシリコン抵抗素子部ＲＢの一端の端子であり、３６はポリシリコン抵抗素子部ＲＢの他端の端子である。   The polysilicon resistance element portion RB is formed on the upper surface of the silicon oxide film 50, and four polysilicon patterns 40 having a length L2 are arranged in parallel at an equal pitch P2 in the X1-X2 direction in Y1-Y2. The ends of both sides of the adjacent polysilicon pattern 40 are alternately connected with the contacts 41Y1 and 41Y2 in a zigzag shape. Reference numeral 35 denotes a terminal at one end of the polysilicon resistance element portion RB, and reference numeral 36 denotes a terminal at the other end of the polysilicon resistance element portion RB.

ポリシリコン抵抗素子部ＲＢは、シリコン酸化膜５１でもって覆われている。   The polysilicon resistance element portion RB is covered with a silicon oxide film 51.

拡散抵抗素子部ＲＡの端子２６とポリシリコン抵抗素子部ＲＢの端子３６とが配線３７でもって接続してあり、拡散抵抗素子部ＲＡとポリシリコン抵抗素子部ＲＢとは電気的に直列に接続されており、抵抗素子１２を形成している。抵抗素子１２は端子２５と端子３５とを有する。拡散抵抗素子部ＲＡとポリシリコン抵抗素子部ＲＢとはシリコン酸化膜５０でもって分離されている。   A terminal 26 of the diffused resistor element RA and a terminal 36 of the polysilicon resistor element RB are connected by a wiring 37, and the diffused resistor element RA and the polysilicon resistor element RB are electrically connected in series. The resistor element 12 is formed. The resistance element 12 has a terminal 25 and a terminal 35. The diffused resistor element RA and the polysilicon resistor element RB are separated by the silicon oxide film 50.

ここで、長さＬ１，Ｌ２は、ＲＡ、ＲＢを同一方向で形成した場合、Ｌ２＜Ｌ１の関係にある。ピッチＰ１，Ｐ２は、Ｐ２＜Ｐ１の関係にある。   Here, the lengths L1 and L2 have a relationship of L2 <L1 when RA and RB are formed in the same direction. The pitches P1 and P2 have a relationship of P2 <P1.

Ｐ型拡散抵抗パターン２０及びポリシリコンパターン４０は、Ｙ１−Ｙ２方向上の中心を一致して配置してあり、ポリシリコンパターン４０は拡散抵抗パターン２０の長さ内に含まれ、ポリシリコン抵抗素子部ＲＢは、拡散抵抗素子部ＲＡが形成されている領域の範囲内に配置してある。   The P-type diffused resistor pattern 20 and the polysilicon pattern 40 are arranged so that their centers in the Y1-Y2 direction coincide with each other. The polysilicon pattern 40 is included within the length of the diffused resistor pattern 20, and the polysilicon resistor element The part RB is disposed within the region where the diffused resistor element RA is formed.

ここで、Ｐ型拡散抵抗パターン２０及びポリシリコンパターン４０は長さＬ１，Ｌ２がＬ２＜Ｌ１の関係にあり、且つ、Ｙ１−Ｙ２方向上の中心が一致して配置してあることにより、Ｙ１−Ｙ２方向上、Ｙ１側のコンタクト４１Ｙ１及びＹ２側のコンタクト４１Ｙ２は夫々Ｙ１側のコンタクト２１Ｙ１及びＹ２側のコンタクト２１Ｙ２より内側に位置することになり、コンタクト４１Ｙ１とコンタクト２１Ｙ１とは干渉し合わず、且つ、コンタクト４１Ｙ２とコンタクト２１Ｙ２とは干渉し合わない配置となっている。   Here, the P-type diffused resistor pattern 20 and the polysilicon pattern 40 are such that the lengths L1 and L2 are in a relationship of L2 <L1 and the centers in the Y1-Y2 direction coincide with each other. In the −Y2 direction, the Y1 side contact 41Y1 and the Y2 side contact 41Y2 are positioned inside the Y1 side contact 21Y1 and the Y2 side contact 21Y2, respectively, and the contact 41Y1 and the contact 21Y1 do not interfere with each other, In addition, the contact 41Y2 and the contact 21Y2 are arranged so as not to interfere with each other.

ＣＭＯＳ半導体装置１０は使用中に加熱されて温度が変化するけれども、抵抗素子１２の部分についてみると、ポリシリコン抵抗素子部ＲＢの負の温度特性と拡散抵抗素子部ＲＡの正の温度特性とが打ち消しあって、温度特性が零になるようにしてある。ここで、ポリシリコン抵抗素子部ＲＢと拡散抵抗素子部ＲＡとが平面図上同じ位置に位置しているため、発熱源からポリシリコン抵抗素子部ＲＢ及び拡散抵抗素子部ＲＡまでの距離が同じとなり、ポリシリコン抵抗素子部ＲＢの温度と拡散抵抗素子部ＲＡの温度は同じとなり、温度特性を設計通りにすることが可能となる。なお、この抵抗素子１２は例えばブリーダ抵抗である。   Although the CMOS semiconductor device 10 is heated during use and changes its temperature, the resistance element 12 has a negative temperature characteristic of the polysilicon resistance element part RB and a positive temperature characteristic of the diffusion resistance element part RA. The temperature characteristics are set to zero by canceling each other. Here, since the polysilicon resistance element portion RB and the diffusion resistance element portion RA are located at the same position on the plan view, the distance from the heat generation source to the polysilicon resistance element portion RB and the diffusion resistance element portion RA becomes the same. The temperature of the polysilicon resistance element portion RB and the temperature of the diffusion resistance element portion RA are the same, and the temperature characteristics can be made as designed. The resistance element 12 is a bleeder resistance, for example.

［抵抗素子１２の製造工程］
次に、図４及び図５を参照して、上記抵抗素子１２を形成する工程について説明する。 [Manufacturing Process of Resistance Element 12]
Next, with reference to FIGS. 4 and 5, a process of forming the resistance element 12 will be described.

先ず、図４（Ａ），（Ｂ）に示すように、Ｐ型のシリコン基板６０の上面側のうち前記の拡散抵抗素子部ＲＡを形成する予定の領域にＮウエル６１を形成する。   First, as shown in FIGS. 4A and 4B, an N well 61 is formed in a region where the diffusion resistance element RA is to be formed on the upper surface side of a P-type silicon substrate 60.

次いで、Ｎウエル６１の上面側に例えばボロンを拡散して、図４（Ｃ）に示すように、Ｐ型拡散抵抗パターン２０を設計ルールに準拠した幅寸法及び間隔で形成する。   Next, for example, boron is diffused on the upper surface side of the N-well 61, and as shown in FIG. 4C, the P-type diffused resistor pattern 20 is formed with a width dimension and an interval conforming to the design rule.

次いで、シリコン基板６０の上面に、シリコン酸化膜５０を通常よりも厚く形成し、図４（Ｄ）に示すように、Ｐ型拡散抵抗パターン２０がシリコン酸化膜５０でもって覆われた状態とする。   Next, a silicon oxide film 50 is formed on the upper surface of the silicon substrate 60 to be thicker than usual, and the P-type diffusion resistance pattern 20 is covered with the silicon oxide film 50 as shown in FIG. .

次いで、ＣＶＤを行って、図４（Ｅ）に示すように、ポリシリコンパターン４０を設計ルールに準拠した幅寸法及び間隔でシリコン酸化膜５０上に形成する。   Next, CVD is performed to form a polysilicon pattern 40 on the silicon oxide film 50 with a width dimension and an interval conforming to the design rule, as shown in FIG.

次いで、シリコン基板６０の上面に、シリコン酸化膜５１を形成し、図５（Ａ）に示すように、ポリシリコンパターン４０がシリコン酸化膜５１でもって覆われた状態とする。   Next, a silicon oxide film 51 is formed on the upper surface of the silicon substrate 60 so that the polysilicon pattern 40 is covered with the silicon oxide film 51 as shown in FIG.

次いで、二層のシリコン酸化膜５０、５１のうちＰ型拡散抵抗２０の両端とポリシリコンパターン４０の両端に対応する部分を除去して開口５３，５４を形成し、Ｐ型拡散抵抗２０の両端にＰ＋拡散させて、図５（Ｂ）に示すように、Ｐ＋型拡散層２２，２３を形成する。このとき、ポリシリコンパターン４０の両端にもＰ＋拡散がなされる。また、このとき、基板６０の上面全体に薄い酸化膜（図示せず）が形成される。   Next, portions of the two-layer silicon oxide films 50 and 51 corresponding to both ends of the P-type diffused resistor 20 and both ends of the polysilicon pattern 40 are removed to form openings 53 and 54, and both ends of the P-type diffused resistor 20 are formed. P + diffusion layers 22 and 23 are formed as shown in FIG. 5B. At this time, P + diffusion is also performed on both ends of the polysilicon pattern 40. At this time, a thin oxide film (not shown) is formed on the entire upper surface of the substrate 60.

最後に、ポリシリコンパターン４０の両端とＰ型拡散抵抗２０の両端に対応する部分を除去して開口５５，５６を形成し、アルミニウムを蒸着し、エッチングして、開口５５，５６を埋めるように、コンタクト２１、４１、端子２５，３５を形成する。これによって、抵抗素子１２が形成される。   Finally, portions corresponding to both ends of the polysilicon pattern 40 and both ends of the P-type diffusion resistor 20 are removed to form openings 55 and 56, and aluminum is deposited and etched to fill the openings 55 and 56. The contacts 21 and 41 and the terminals 25 and 35 are formed. Thereby, the resistance element 12 is formed.

上記より分かるように、抵抗素子１２は、図６に示す拡散抵抗素子部ＲＡとポリシリコン抵抗素子部ＲＢとが平面図上並んだ配置の抵抗素子を製造する工程と略同じ工程でもって、即ち、従来の製造工程を変更せずに製造することが可能である。   As can be seen from the above, the resistance element 12 has substantially the same process as the process of manufacturing the resistance element in which the diffused resistance element portion RA and the polysilicon resistance element portion RB shown in FIG. It is possible to manufacture without changing the conventional manufacturing process.

［変形例］
上記の構造の抵抗素子１２はバイポーラ半導体装置にも形成することが可能である。 [Modification]
The resistance element 12 having the above structure can also be formed in a bipolar semiconductor device.

なお、配線３７は形成しないで、拡散抵抗素子部ＲＡを一つの抵抗素子、ポリシリコン抵抗素子部ＲＢを別の一つの抵抗素子として使用することも可能である。   It is also possible to use the diffusion resistance element portion RA as one resistance element and the polysilicon resistance element portion RB as another resistance element without forming the wiring 37.

なお、温度特性を考慮しない場合には、ポリシリコン抵抗素子部ＲＢに変えて別の抵抗素子部を設けてもよい。   In the case where temperature characteristics are not considered, another resistance element portion may be provided instead of the polysilicon resistance element portion RB.

また、前記のように温度特性を零であるようにする他に、ポリシリコン抵抗素子部ＲＢ及び拡散抵抗素子部ＲＡを適宜形成して、上記の構造の抵抗素子１２を故意に何がしかの温度特性を有するように構成することも出来る。   In addition to making the temperature characteristics zero as described above, the polysilicon resistance element portion RB and the diffusion resistance element portion RA are appropriately formed, and the resistance element 12 having the above-described structure is deliberately formed. It can also be configured to have temperature characteristics.

また、前記のように抵抗素子部ＲＡ、ＲＢの向きを揃えなくても、抵抗素子１２は形成出来る。例えば、抵抗素子部ＲＡの向きに対して９０度の向きに抵抗素子部ＲＢを形成してもよい。その場合には、Ｐ型拡散抵抗パターン及びポリシリコンパターンの長さは、Ｌ２＜Ｌ１の関係はなくてもよい。   Further, the resistance element 12 can be formed without aligning the directions of the resistance element portions RA and RB as described above. For example, the resistance element portion RB may be formed in a direction of 90 degrees with respect to the direction of the resistance element portion RA. In that case, the lengths of the P-type diffused resistor pattern and the polysilicon pattern may not have a relationship of L2 <L1.

本発明の実施例１になるＣＭＯＳ半導体装置を示す斜視図である。It is a perspective view which shows the CMOS semiconductor device which becomes Example 1 of this invention. ＣＭＯＳ半導体装置の抵抗素子の部分を拡大して示す、図３中、II-II線に沿う断面図である。It is sectional drawing which follows the II-II line | wire in FIG. 3, which expands and shows the part of the resistive element of a CMOS semiconductor device. ＣＭＯＳ半導体装置の抵抗素子の部分を拡大して示す平面図である。It is a top view which expands and shows the part of the resistive element of a CMOS semiconductor device. ＣＭＯＳ半導体装置の抵抗素子の製造工程を示す図である。It is a figure which shows the manufacturing process of the resistive element of a CMOS semiconductor device. 図４（Ｅ）に続く抵抗素子の製造工程を示す図である。It is a figure which shows the manufacturing process of the resistive element following FIG.4 (E). 従来のＣＭＯＳ半導体装置を示す斜視図である。It is a perspective view which shows the conventional CMOS semiconductor device.

符号の説明Explanation of symbols

１０ ＣＭＯＳ半導体装置
１１ シリコンチップ基板
１２ 抵抗素子
ＲＡ 拡散抵抗素子部
ＲＢ ポリシリコン抵抗素子部
２０ Ｐ型拡散抵抗パターン
２１Ｙ１，２１Ｙ２ コンタクト
２２，２３ Ｐ＋型拡散層
２５，２６ 端子
３５，３６ 端子
３７ 配線
４０ ポリシリコンパターン
４１Ｙ１，４１Ｙ２ コンタクト
５０，５１ シリコン酸化膜
６０ Ｐ型のシリコン基板
６１ Ｎウエル DESCRIPTION OF SYMBOLS 10 CMOS semiconductor device 11 Silicon chip substrate 12 Resistance element RA Diffusion resistance element part RB Polysilicon resistance element part 20 P-type diffusion resistance pattern 21Y1, 21Y2 Contact 22, 23 P + type diffusion layer 25, 26 Terminal 35, 36 Terminal 37 Wiring 40 Polysilicon pattern 41Y1, 41Y2 Contact 50, 51 Silicon oxide film 60 P type silicon substrate 61 N well

Claims (4)

抵抗素子を有し、
該抵抗素子は、正又は負の温度特性を有する第１の抵抗素子部と、該第１の抵抗素子部とは逆の温度特性を有する第２の抵抗素子部とが上下の配置で形成してあり、該第１の抵抗素子部と該第２の抵抗素子部とが重なっている構成であることを特徴とする半導体装置。 Having a resistance element,
The resistance element includes a first resistance element portion having a positive or negative temperature characteristic and a second resistance element portion having a temperature characteristic opposite to that of the first resistance element portion. A semiconductor device characterized in that the first resistance element portion and the second resistance element portion overlap each other. 請求項１に記載の半導体装置において、
前記第１の抵抗素子部は、拡散抵抗素子部であり、下側に位置し、
前記第２の抵抗素子部は、ポリシリコン抵抗素子部であり、前記拡散抵抗素子部の上側に位置している構成としたことを特徴とする半導体装置。 The semiconductor device according to claim 1,
The first resistance element portion is a diffused resistance element portion, and is located on the lower side.
2. The semiconductor device according to claim 1, wherein the second resistance element portion is a polysilicon resistance element portion and is positioned above the diffused resistance element portion. 請求項２に記載の半導体装置において、
前記拡散抵抗素子部と前記ポリシリコン抵抗素子部とは電気的に直列に接続してある構成としたことを特徴とする半導体装置。 The semiconductor device according to claim 2,
The semiconductor device characterized in that the diffusion resistance element portion and the polysilicon resistance element portion are electrically connected in series. 請求項２又は請求項３に記載の半導体装置において、
前記拡散抵抗素子部は、複数の拡散抵抗パターンが平行に並んでおり、隣同士の拡散抵抗パターンの両側の端が互い違いに第１のコンタクトでもって電気的に接続してあり、ジグザク状となっている構成であり、
前記ポリシリコン抵抗素子部は、複数のポリシリコンパターンが平行に並んでおり、隣同士のポリシリコンパターンの両側の端が互い違いに第２のコンタクトでもって電気的に接続してあり、ジグザク状となっている構成であり、
前記ポリシリコンパターンの長さは前記拡散抵抗パターンの長さよりも短く、前記第１のコンタクトと前記第２のコンタクトとは干渉しないで配置してある構成としたことを特徴とする半導体装置。 The semiconductor device according to claim 2 or claim 3,
The diffused resistor element portion has a plurality of diffused resistor patterns arranged in parallel, and the ends on both sides of the adjacent diffused resistor pattern are alternately electrically connected by the first contact, and have a zigzag shape. The configuration
In the polysilicon resistance element portion, a plurality of polysilicon patterns are arranged in parallel, and both ends of the adjacent polysilicon patterns are alternately electrically connected by the second contacts, It is the composition that
The length of the polysilicon pattern is shorter than the length of the diffused resistor pattern, and the first and second contacts are arranged so as not to interfere with each other.
JP2004381864A 2004-12-28 2004-12-28 Semiconductor device Pending JP2006190709A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011091758A (en) * 2009-10-26 2011-05-06 Seiko Epson Corp Constant current generating circuit, resistance circuit, integrated circuit device and electronic apparatus
JP2011090637A (en) * 2009-10-26 2011-05-06 Seiko Epson Corp Regulator, integrated circuit device and electronic apparatus
JP2014099926A (en) * 2014-02-20 2014-05-29 Seiko Epson Corp Constant current generating circuit, resistance circuit, integrated circuit device, and electronic apparatus
US9014654B2 (en) 2011-12-09 2015-04-21 Murata Manufacturing Co., Ltd. Semiconductor apparatus
WO2015166654A1 (en) * 2014-05-01 2015-11-05 パナソニックＩｐマネジメント株式会社 Semiconductor device and semiconductor module
JP2016201415A (en) * 2015-04-08 2016-12-01 富士電機株式会社 Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5929054U (en) * 1982-08-18 1984-02-23 日本電気株式会社 semiconductor equipment
JPS62234363A (en) * 1986-04-04 1987-10-14 Fuji Electric Co Ltd Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5929054U (en) * 1982-08-18 1984-02-23 日本電気株式会社 semiconductor equipment
JPS62234363A (en) * 1986-04-04 1987-10-14 Fuji Electric Co Ltd Semiconductor integrated circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011091758A (en) * 2009-10-26 2011-05-06 Seiko Epson Corp Constant current generating circuit, resistance circuit, integrated circuit device and electronic apparatus
JP2011090637A (en) * 2009-10-26 2011-05-06 Seiko Epson Corp Regulator, integrated circuit device and electronic apparatus
US9014654B2 (en) 2011-12-09 2015-04-21 Murata Manufacturing Co., Ltd. Semiconductor apparatus
JP2014099926A (en) * 2014-02-20 2014-05-29 Seiko Epson Corp Constant current generating circuit, resistance circuit, integrated circuit device, and electronic apparatus
WO2015166654A1 (en) * 2014-05-01 2015-11-05 パナソニックＩｐマネジメント株式会社 Semiconductor device and semiconductor module
JP2016201415A (en) * 2015-04-08 2016-12-01 富士電機株式会社 Semiconductor device

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