JPS62225005A - Oscillation circuit - Google Patents
Oscillation circuitInfo
- Publication number
- JPS62225005A JPS62225005A JP6901486A JP6901486A JPS62225005A JP S62225005 A JPS62225005 A JP S62225005A JP 6901486 A JP6901486 A JP 6901486A JP 6901486 A JP6901486 A JP 6901486A JP S62225005 A JPS62225005 A JP S62225005A
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- circuit
- power consumption
- waveform
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 67
- 230000002401 inhibitory effect Effects 0.000 claims abstract description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 7
- 230000003111 delayed effect Effects 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 5
- 238000007493 shaping process Methods 0.000 abstract description 4
- 230000000295 complement effect Effects 0.000 description 4
- 238000004904 shortening Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、発振開始の時間が早く、かつ消費電力の小さ
な発振回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an oscillation circuit that starts oscillation quickly and consumes little power.
従来の技術
従来、発振回路の電源投入後の発振開始時間を短かくす
るには、発振回路の能力を大きくし、接続される水晶振
動子やセラミック発振素子に供給するエネルギを大きく
することが必要であったが、このことは、消費電力を大
きくすることにつながり、低消費電力と相反する。Conventional technology Conventionally, in order to shorten the time it takes for an oscillation circuit to start oscillating after power is turned on, it is necessary to increase the capacity of the oscillation circuit and increase the energy supplied to the connected crystal resonator or ceramic oscillation element. However, this leads to an increase in power consumption, which is contradictory to low power consumption.
近年、情報処理速度がますます高速化されるに伴い、ま
た集積回路の大規模化に伴い、高速、低消費電力の発振
回路の要求が多い。特に、電池駆動の場合、低消費電力
化は不可欠であり、回路を使用しない、いわゆるスタン
バイモード時には、低消費電力が必須であシ、かつ回路
の使用状態では、できるだけ、速やかに発振を開始して
、動作状態に移行することが必要である。従来この両者
を両立させることが困難であった。In recent years, as information processing speeds have become increasingly faster and integrated circuits have become larger in scale, there has been a growing demand for high-speed, low power consumption oscillation circuits. In particular, low power consumption is essential in the case of battery drive, and low power consumption is essential when the circuit is not in use, so-called standby mode, and when the circuit is in use, oscillation must start as soon as possible. It is necessary to transition to an operational state. Conventionally, it has been difficult to achieve both.
発明が解決しようとする問題点
このように従来の回路では、相反する要求を満足させる
ことが困難であった。本発明は、かかる点に鑑みてなさ
れたもので、発振の立上り時間の短縮と低消費電力化を
同時に達成する回路の提供を目的としている。Problems to be Solved by the Invention As described above, it has been difficult to satisfy the conflicting demands with conventional circuits. The present invention has been made in view of this point, and an object of the present invention is to provide a circuit that simultaneously achieves shortening of oscillation rise time and low power consumption.
問題点を解決するための手段
本発明は上記問題点を解決するため、発振開始時には複
数個のインバータを駆動することで発振開始時間を短か
くし、発振が安定した後には、１個あるいはそれ以上の
インバータを除いた他のインバータの動作を禁止し、発
振消費電力を減少させるものである。Means for Solving the Problems In order to solve the above problems, the present invention shortens the oscillation start time by driving a plurality of inverters when oscillation starts, and after the oscillation is stabilized, one or more inverters are driven. The operation of all inverters other than the one inverter is prohibited to reduce oscillation power consumption.
本発明は複数個のインバータを有する発振回路と、発振
回路の発振開始を検出する回路と、発振が安定する迄の
時間以上の遅延を有する遅延信号を発生する遅延信号発
生回路と、その信号により、複数個のインバータのうち
、少くとも、１個のインバータの動作を禁止させる回路
とで構成される。The present invention provides an oscillation circuit having a plurality of inverters, a circuit for detecting the start of oscillation of the oscillation circuit, a delay signal generation circuit for generating a delay signal having a delay longer than the time required for the oscillation to stabilize, and , and a circuit for inhibiting the operation of at least one inverter among the plurality of inverters.
作用
本発明によると、発振開始時には、複数個のインバータ
を駆動させ、水晶又はセラミックに供給するエネルギを
大きくして発振開始時間を短縮し、また発振が安定した
後には、その発振回路を構成するインバータのうちの少
くとも１個は動作禁止状態にすることで、低消費電力化
を図る。According to the present invention, when oscillation starts, a plurality of inverters are driven to increase the energy supplied to the crystal or ceramic to shorten the oscillation start time, and after the oscillation is stabilized, the oscillation circuit is configured. By disabling at least one of the inverters, power consumption is reduced.
実施例
第１図は本発明の発振回路の一例を示すブロック図であ
る。第１図において１は、複数個の発振回路、３は発振
波形を分周、整形して、例えばクロックパルスを作り出
す回路、４は電源、６は接地電位、６は発振出力端子、
７，８は回路内各ノード部である。１０はその発振出力
６の発振波形を検出し、更に発振が安定する迄の時間遅
延をもった遅延信号を発生する遅延信号発生回路であり
、１６は発振制御回路である。Embodiment FIG. 1 is a block diagram showing an example of an oscillation circuit of the present invention. In FIG. 1, 1 is a plurality of oscillation circuits, 3 is a circuit that divides and shapes the oscillation waveform to generate, for example, a clock pulse, 4 is a power supply, 6 is a ground potential, 6 is an oscillation output terminal,
Reference numerals 7 and 8 are respective node portions within the circuit. 10 is a delay signal generation circuit which detects the oscillation waveform of the oscillation output 6 and further generates a delayed signal with a time delay until the oscillation is stabilized, and 16 is an oscillation control circuit.
第２図はこの回路に生じる各信号の一例であり、ｖ４は
電源端子４の電圧であり、ある値以上になると、発振が
開始することで、出力端子８にｖ６のような発振出力が
得られる。この発振を検出し、安定するまでの一定時間
後には、中間ノード部７にｖ７の信号が発生するものと
する。そして、ノード７の電圧ｖ７の信号により、複数
個の発振回路ｎ、・・・・・・”ｎ−＋・・・・・・ｎ
ｎ のうちの１個わるいは、それ以上を除いた残りの
発振回路の動作を禁止することで、低消費電力を達成す
る。ノード７の電圧ｖ７の信号により、発振回路の駆動
力が絞られるため、発振波形はｖ６のように途中から振
幅が減少した形状を示すが、この時の振幅は、第１図の
次段の分周整形回路３を駆動できる大きさがるれば十分
である。Figure 2 shows an example of each signal generated in this circuit, where v4 is the voltage at power supply terminal 4, and when it exceeds a certain value, oscillation starts and an oscillation output like v6 is obtained at output terminal 8. It will be done. It is assumed that a signal v7 is generated at the intermediate node section 7 after a certain period of time after this oscillation is detected and stabilized. Then, a plurality of oscillation circuits n,..."n-+...n
Low power consumption is achieved by prohibiting the operation of the remaining oscillation circuits except for one or more of the n oscillation circuits. Since the driving force of the oscillation circuit is reduced by the signal of voltage v7 at node 7, the oscillation waveform shows a shape in which the amplitude decreases from the middle like v6, but the amplitude at this time is as shown in the next stage in Fig. 1. It is sufficient that the size is large enough to drive the frequency dividing and shaping circuit 3.
更に具体的回路例を第３図に示す。図では発振回路は、
並列２個のインバータより構成される場合を示す。１１
．２１はＰチャネルトランジスタ、１２．２２はＮチャ
ネルトランジスタであシ、相補対トランジスタ１１と１
２．同２１と２２でインバータを形成している。１３．
１４は容量、１６は水晶又はセラミック発振子、１７は
ＡＮＤ回路である。８はその出力、７，９はその入力で
あり、同出力８は遅延信号発生回路の出力として供給さ
れる。A more specific example of the circuit is shown in FIG. In the figure, the oscillation circuit is
A case is shown in which it is composed of two inverters in parallel. 11
．． 21 is a P-channel transistor, 12.22 is an N-channel transistor, and a complementary pair of transistors 11 and 1.
2. The same 21 and 22 form an inverter. 13.
14 is a capacitor, 16 is a crystal or ceramic oscillator, and 17 is an AND circuit. 8 is its output, 7 and 9 are its inputs, and the output 8 is supplied as the output of the delayed signal generation circuit.
発振開始時には、最初遅延信号発生回路１ｏの出力端子
７の電位は４Ｌ１”（第２図のｖ７参照）とするとき、
発振回路の各インバータをみると、相補対トランジスタ
１１．１２および同２１．２２とも動作状態となり、発
振は急速に立上り、時間短縮化をはかる。発振開始後あ
る遅延時間後、遅延信号発生回路１０の出力端子７の電
位ｖ７は１１Ｈ”に変化するため、インバータ構成の相
補対トランジスタ２１．２２は動作禁止状態となり、発
振の駆動力は抑えられ、消費電力が減少する。At the start of oscillation, when the potential of the output terminal 7 of the delay signal generation circuit 1o is initially set to 4L1'' (see v7 in FIG. 2),
Looking at each inverter of the oscillation circuit, complementary pair transistors 11, 12 and 21, 22 are both in operation, and oscillation starts up rapidly, thereby shortening the time. After a certain delay time after the start of oscillation, the potential v7 of the output terminal 7 of the delayed signal generation circuit 10 changes to 11H'', so the complementary pair transistors 21 and 22 in the inverter configuration become disabled, and the driving force for oscillation is suppressed. , power consumption is reduced.
ここで、相補対トランジスタ１１．１２のインバータ構
成での消費電力を最小値に設計することで、低消費電力
発振回路が達成される。Here, a low power consumption oscillation circuit is achieved by designing the power consumption of the inverter configuration of the complementary pair of transistors 11 and 12 to a minimum value.
本発明はＣＭＯ８回路部分を除いて、残シの回路構成の
要素は、Ｎ−ＭＯＳ 、Ｐ−ＭＯＳあるいはバイポーラ
で構成される回路のいずれの場合にも同様に適用できる
。The present invention can be similarly applied to any case where the remaining circuit configuration elements, except for the CMO8 circuit portion, are configured with N-MOS, P-MOS, or bipolar.
発明の効果
以上述べてきたように、本発明によれば、発振開始時間
を短縮化し、かつ使用時の消費電力を最小限にすること
が出来、高速、低消費電力の回路には極めて有効である
。Effects of the Invention As described above, according to the present invention, oscillation start time can be shortened and power consumption during use can be minimized, making it extremely effective for high-speed, low-power consumption circuits. be.
第１図は本発明の一実施例における発振回路を路側であ
る。
′１・・・・・・発振回路部、３・・・・・・分周整形
回路、４・・・・・・電源、５・・・・・・接地電位、
６・・・・・・発振回路出力、１０・・・・・・遅延信
号発生回路、１６・・・・・・発振制御回路、１７・・
・・・ＡＮＤ回路、１１．２１・・・・・・Ｐチャネル
トランジスタ、１２．２２・・・・・・Ｎチャネルトラ
ンジスタ、１３．１４・・・・・・容量、１６・・・・
・・水晶又はセラミック発振子。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第２
図
吟崩FIG. 1 shows an oscillation circuit according to an embodiment of the present invention on the roadside. '1... Oscillation circuit section, 3... Frequency dividing and shaping circuit, 4... Power supply, 5... Ground potential,
6...Oscillation circuit output, 10...Delay signal generation circuit, 16...Oscillation control circuit, 17...
...AND circuit, 11.21...P channel transistor, 12.22...N channel transistor, 13.14...Capacity, 16...
...Crystal or ceramic resonator. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Zuginpo
Claims (1)
回路の発振波形を検出し、その発振が安定するまでの時
間以上の遅延信号を発生させる遅延信号発生回路と、そ
の遅延信号により、前記複数個のインバータのうちの少
くとも１個の動作を禁止させる手段をそなえた発振回路
。An oscillation circuit composed of a plurality of inverters, a delay signal generation circuit that detects the oscillation waveform of the oscillation circuit and generates a delayed signal longer than the time required for the oscillation to stabilize, and the delayed signal An oscillation circuit comprising means for inhibiting the operation of at least one of the inverters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6901486A JPS62225005A (en) | 1986-03-27 | 1986-03-27 | Oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6901486A JPS62225005A (en) | 1986-03-27 | 1986-03-27 | Oscillation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62225005A true JPS62225005A (en) | 1987-10-03 |
Family
ID=13390310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6901486A Pending JPS62225005A (en) | 1986-03-27 | 1986-03-27 | Oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62225005A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04200009A (en) * | 1990-11-29 | 1992-07-21 | Toshiba Corp | Oscillator circuit |
| JPH11265367A (en) * | 1998-03-18 | 1999-09-28 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1986
- 1986-03-27 JP JP6901486A patent/JPS62225005A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04200009A (en) * | 1990-11-29 | 1992-07-21 | Toshiba Corp | Oscillator circuit |
| JPH11265367A (en) * | 1998-03-18 | 1999-09-28 | Hitachi Ltd | Semiconductor integrated circuit device |
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