JPS62225004A - Oscillation circuit - Google Patents
Oscillation circuitInfo
- Publication number
- JPS62225004A JPS62225004A JP6901386A JP6901386A JPS62225004A JP S62225004 A JPS62225004 A JP S62225004A JP 6901386 A JP6901386 A JP 6901386A JP 6901386 A JP6901386 A JP 6901386A JP S62225004 A JPS62225004 A JP S62225004A
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- circuit
- output
- voltage
- oscillation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 55
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 6
- 230000003111 delayed effect Effects 0.000 claims description 4
- 238000009412 basement excavation Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、発振開始の時間が早く、かつ消費電力の小さ
な発振回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an oscillation circuit that starts oscillation quickly and consumes little power.
従来の技術
従来、発振回路の電源投入後の開始時間を短かくするに
は、発振回路の能力を大きくし、接続される水晶振動子
や、セラミック発振素子に供給するエネルギを大きくす
ることが必要であるが、このことは消費電力を大きくす
ることにつながり、低消費電力とは相反する。Conventional technology Conventionally, in order to shorten the start time of an oscillation circuit after power is turned on, it is necessary to increase the capacity of the oscillation circuit and increase the energy supplied to the connected crystal resonator or ceramic oscillation element. However, this leads to an increase in power consumption, which is contradictory to low power consumption.
近年情報処理速度が益々高速化され、かつ消費電力は益
々減少することが要求される。特に電池電源を使用する
場合には、低消費電力化は不可欠であり、また、回路は
、使用しない時はスタンバイモードに設定され、発振回
路もストップ状態にして、極力消費電流を少なくする。In recent years, information processing speeds have been increasing, and power consumption has been required to be reduced. Especially when using battery power, low power consumption is essential, and the circuit is set to standby mode when not in use, and the oscillation circuit is also stopped to reduce current consumption as much as possible.
一方、回路の使用状態では、出来るだけ、すみやかに発
振を開始して動作状態に移行することが必要である。On the other hand, when the circuit is in use, it is necessary to start oscillation and transition to an operating state as quickly as possible.
従来この両者を両立させることが困難であった。Conventionally, it has been difficult to achieve both.
発明が解決しようとする問題点
このように従来の回路では、相反する要求を満足させる
ことが困難であった。本発明は、発振の立上り時間の短
縮と、低消費電力化を同時に達成する回路の提供を目的
としている。Problems to be Solved by the Invention As described above, it has been difficult to satisfy the conflicting demands with conventional circuits. An object of the present invention is to provide a circuit that simultaneously achieves shortening of oscillation rise time and low power consumption.
即ち、本発明は、上記問題点を解決するため、発振開始
時には、発振回路に大きな電流を供給することで、発振
開始時間を短かくし、発振が安定した後には、発振回路
に供給する電流を制限して、低消費電力化を達成する回
路を提供する。That is, in order to solve the above problems, the present invention shortens the oscillation start time by supplying a large current to the oscillation circuit when oscillation starts, and after the oscillation is stabilized, the current supplied to the oscillation circuit is reduced. To provide a circuit that achieves low power consumption by limiting power consumption.
問題点を解決するだめの手段
本発明は、発振回路と、この発振回路の発振開始を検出
する回路と、発振が安定するまでの時間以上の遅延信号
を発生する回路と、その信号により、発振回路と電流供
給源との間に挿入された可変抵抗回路を制御して、その
抵抗値を変化させる回路とで構成された発振回路である
。Means for Solving the Problems The present invention comprises an oscillation circuit, a circuit for detecting the start of oscillation of the oscillation circuit, a circuit for generating a delayed signal longer than the time required for the oscillation to stabilize, and a circuit for detecting the oscillation by the signal. This is an oscillation circuit consisting of a circuit that controls a variable resistance circuit inserted between the circuit and a current supply source to change its resistance value.
作用
本発明によると、発振開始時には、可変抵抗回路の抵抗
値を小さくして、発振回路に供給する電流を大きくし、
発振開始時間を短かくし、また発振が安定した後は、そ
の抵抗値を大きくすることで、その電流値を、発振維持
電流値の最小値近傍捷で絞り込み、消費電流が最小限に
制御される。According to the present invention, at the start of oscillation, the resistance value of the variable resistance circuit is decreased to increase the current supplied to the oscillation circuit,
By shortening the oscillation start time and increasing the resistance value after oscillation has stabilized, the current value is narrowed down to around the minimum value of the oscillation sustaining current value, and the current consumption is controlled to the minimum. .
実施例
第1図は、本発明の発振回路の一実施例を示すブロック
図である。第1図において、1は発掘回路、2は可変抵
抗制御回路、4は電源、6は接地電源、6は発振回路出
力端子、1oは発振が安定する迄の時間遅延をもった信
号発生回路c以下、発振検出、遅延回路と呼ぶ)さらに
、8はその出力信号である。Embodiment FIG. 1 is a block diagram showing an embodiment of the oscillation circuit of the present invention. In Figure 1, 1 is an excavation circuit, 2 is a variable resistance control circuit, 4 is a power supply, 6 is a ground power supply, 6 is an oscillation circuit output terminal, and 1o is a signal generation circuit c with a time delay until oscillation is stabilized. (hereinafter referred to as an oscillation detection and delay circuit) Furthermore, 8 is its output signal.
第2図は信号波形の一例であり、電源電圧v4がある値
以上になると発振を開始し、出力端子6に出力波形v6
が得られる。この発振を検出し、安定するまでの遅延時
間経過後、信号発生回路10に端子電圧v8の信号が発
生するものとする。FIG. 2 shows an example of a signal waveform, and when the power supply voltage v4 reaches a certain value or more, oscillation starts, and an output waveform v6 is output to the output terminal 6.
is obtained. It is assumed that after this oscillation is detected and a delay time until stabilization has elapsed, a signal of terminal voltage v8 is generated in the signal generating circuit 10.
信号発生回路1oの端子電圧v8の信号により第1図中
の可変抵抗制御回路2の抵抗値を増大させ、発振4幅を
減少させ、パワーダウンを図る。The resistance value of the variable resistance control circuit 2 shown in FIG. 1 is increased by the signal of the terminal voltage v8 of the signal generation circuit 1o, and the oscillation width is decreased, thereby powering down.
この時の振幅は次段の分周回路を駆動できる大きさがあ
れば良い。The amplitude at this time only needs to be large enough to drive the next-stage frequency divider circuit.
更に具体的回路例を第3図に示す。A more specific example of the circuit is shown in FIG.
第3図では0M08回路の場合を示す。11 。FIG. 3 shows the case of a 0M08 circuit. 11.
21.22はPチャネルトランジスタ、12はNチャネ
ルトランジスタであり、この対により発掘回路のインバ
ータ部分を形成する。13.14は容量、15は水晶ま
たはセラミックの発振子である。21.22は並列に接
続されたPチャネルトランジスタであり、可変抵抗回路
を構成する。21 and 22 are P-channel transistors, and 12 is an N-channel transistor, and this pair forms an inverter portion of the excavation circuit. 13 and 14 are capacitors, and 15 is a crystal or ceramic oscillator. 21 and 22 are P-channel transistors connected in parallel and constitute a variable resistance circuit.
発振開始時には、信号発生回路1oの出力端子8の電圧
v8は第2図のように、II L”レベルであり、並列
のPチャネルトランジスタ21.22は両方ともオン状
態で、低抵抗状態である。発振が開始して、ある遅延時
間後に信号発生回路1oの出力端子8の電圧は、“H″
に変化するため、これによって駆動されるPチャネルト
ランジスタ22はオフ状態となり、発掘回路に供給され
る電流は、トランジスタ21を通してのみの値となる。At the start of oscillation, the voltage v8 at the output terminal 8 of the signal generating circuit 1o is at the II L" level as shown in FIG. 2, and the parallel P-channel transistors 21 and 22 are both on and in a low resistance state. After a certain delay time after oscillation starts, the voltage at the output terminal 8 of the signal generation circuit 1o becomes "H".
As a result, the P-channel transistor 22 driven by this is turned off, and the current supplied to the excavation circuit has a value only through the transistor 21.
ここでトランジスタ21のオン抵抗値を、最小発振維持
電流に設計することにより、安定発振後の消費電流を最
小値に抑えることが可能となる。By designing the on-resistance value of the transistor 21 to be the minimum oscillation sustaining current, it is possible to suppress the current consumption after stable oscillation to the minimum value.
なお、この回路構成はNMO8、PMO3)ランジスタ
構成の反転した回路にも適用できる。Note that this circuit configuration can also be applied to a circuit with an inverted transistor configuration (NMO8, PMO3).
発明の効果
以上述べてきたように、本発明によれば、発振開始時間
を短縮化し、かつ、使用時の消費電力を小さくすること
ができ、高速、低消費電力の回路には極めて有効である
。Effects of the Invention As described above, according to the present invention, it is possible to shorten the oscillation start time and reduce power consumption during use, which is extremely effective for high-speed, low power consumption circuits. .
第1図は本発明の一実施例における発振回路ブは0MO
3を用いた場合の実施例回路図である。
101.・・発振回路部、2・・・・・・可変抵抗側脚
部、10・・・・・・信号発生回路、4・・・・・・電
源、5・・・・・・接地電位、6・・・・・・発振出力
端子、8・・・・・・信号発生回路出力端子、11..
21.22・・・・・Pチャネルトランジスタ、12・
・・・・・Nチャネルトランジスタ、13.14・・・
・・・容量、16・・・・・・発振素子(水晶又はセラ
ミック)。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第2図
第3図Figure 1 shows that the oscillation circuit block in one embodiment of the present invention is 0MO.
FIG. 3 is an example circuit diagram in the case where No. 3 is used. 101. ...Oscillation circuit section, 2...Variable resistance side leg section, 10...Signal generation circuit, 4...Power supply, 5...Ground potential, 6 ...Oscillation output terminal, 8...Signal generation circuit output terminal, 11. ..
21.22...P channel transistor, 12.
...N-channel transistor, 13.14...
...Capacitance, 16...Oscillation element (crystal or ceramic). Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3
Claims (1)
延信号発生回路と、その遅延信号により、前記発振回路
と電流供給源との間に挿入された抵抗制御回路の抵抗値
を変化させる手段をそなえた発振回路。A delayed signal generation circuit detects the start of oscillation of an oscillation circuit and generates a delayed signal, and means for changing the resistance value of a resistance control circuit inserted between the oscillation circuit and a current supply source using the delayed signal. Equipped with an oscillation circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6901386A JPS62225004A (en) | 1986-03-27 | 1986-03-27 | Oscillation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6901386A JPS62225004A (en) | 1986-03-27 | 1986-03-27 | Oscillation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62225004A true JPS62225004A (en) | 1987-10-03 |
Family
ID=13390280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6901386A Pending JPS62225004A (en) | 1986-03-27 | 1986-03-27 | Oscillation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62225004A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002007302A1 (en) * | 2000-07-17 | 2002-01-24 | Toyo Communication Equipment Co., Ltd. | Piezoelectric oscillator |
-
1986
- 1986-03-27 JP JP6901386A patent/JPS62225004A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002007302A1 (en) * | 2000-07-17 | 2002-01-24 | Toyo Communication Equipment Co., Ltd. | Piezoelectric oscillator |
US6791424B2 (en) | 2000-07-17 | 2004-09-14 | Toyo Communication Equipment Co., Ltd. | Piezoelectric oscillator |
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