JPS62216364A - Hetero junction bipolar transistor - Google Patents
Hetero junction bipolar transistorInfo
- Publication number
- JPS62216364A JPS62216364A JP5974386A JP5974386A JPS62216364A JP S62216364 A JPS62216364 A JP S62216364A JP 5974386 A JP5974386 A JP 5974386A JP 5974386 A JP5974386 A JP 5974386A JP S62216364 A JPS62216364 A JP S62216364A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitter
- sic
- conductivity type
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 125000005842 heteroatom Chemical group 0.000 title abstract 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 12
- 239000013078 crystal Substances 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 44
- 238000000137 annealing Methods 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
珪素（Ｓｉ）等の在来の半導体層でコレクタ層とベース
層を形成し、その」二に該半導体層より禁制帯幅（ギヤ
ツブ）の大きい（８９＝ ２．２ ｅＶ） β−炭化
珪素（β−３ｉＣ、または３Ｃ−３ｉＣ）層を形成し、
この層をエミッタとしたワイドギャップエミッタのへテ
ロ接合バイポーラトランジスタ（ＨＢＴ）を提起し、高
速、高電力用素子として用いる。[Detailed Description of the Invention] [Summary] A collector layer and a base layer are formed with a conventional semiconductor layer such as silicon (Si), and secondly, a material having a forbidden band width (gear) larger than that of the semiconductor layer (89= 2.2 eV) forming a β-silicon carbide (β-3iC or 3C-3iC) layer,
A wide-gap emitter heterojunction bipolar transistor (HBT) using this layer as an emitter is proposed and used as a high-speed, high-power device.
本発明は半導体性能指標の高いβ−３ｉＣをワイドギャ
ップエミッタとして用いたＨＢＴに関する。The present invention relates to an HBT using β-3iC, which has a high semiconductor performance index, as a wide gap emitter.
次期高速バイポーラ大規模集積回路（ＶＬＳＩ）用素子
としてＩＩＢＴが検討されている。IIBT is being considered as a device for next-generation high-speed bipolar large-scale integrated circuits (VLSI).
１）８Ｔは通常のホモ接合バイポーラトランジスタに比
べ、エミッタを高濃度にドープしなくてもエミッタ注入
効率を十分大きくできる。1) Compared to ordinary homojunction bipolar transistors, 8T can sufficiently increase emitter injection efficiency without doping the emitter to a high concentration.
通常のＨＢＴは混晶半導体を用い、各層の混晶比を変え
ることにより、ギャップを制御して形成しているが、在
来の珪素（Ｓｉ）素子のエミッタをワイドギャップの物
質で形成したワイドギャップエミッタトランジスタがあ
る。Normal HBTs use a mixed crystal semiconductor and are formed by controlling the gap by changing the mix crystal ratio of each layer. There is a gap emitter transistor.
ワイドギャップエミッタの主な利点は、エミッタ注入効
率を」二げ、ベース抵抗を下げることができることであ
る。The main advantages of wide-gap emitters are that they can increase emitter injection efficiency and lower base resistance.
〔従来の技術と発明が解決しようとする問題点〕従来の
ワイトギャソプエミノタの物質として、例えばアルミニ
ウムガリウム砒素（八ＩＧａＡｓ）、ガリウム砒素（Ｇ
ａＡｓ）等を用いた。[Prior art and problems to be solved by the invention] Conventional materials such as aluminum gallium arsenide (GaAs) and gallium arsenide (G
aAs) etc. were used.
この場合の問題点は、ワイドギヤツブエミッタ物質の最
高使用温度が３１より低（、従って大電力用トランジス
タには適さなかった。The problem in this case was that the maximum operating temperature of the wide gear tube emitter material was lower than 31°C (therefore, it was not suitable for high power transistors).
上記問題点の解決は、一導電型半導体層（１）上に、他
導電型半導体層（２）、一導電型β−炭化珪素層（３）
を順次成長してなり、一導電型半導体層（１）をコレク
タ領域、他導電型半導体層（２）をベース領域、一導電
型β−炭化珪素層（３）をエミッタ領域とする本発明に
よるＩＩＢＴにより達成される。The solution to the above problem is to form a semiconductor layer of one conductivity type (1), a semiconductor layer of another conductivity type (2), and a β-silicon carbide layer of one conductivity type (3).
According to the present invention, the semiconductor layer (1) of one conductivity type is used as a collector region, the semiconductor layer (2) of another conductivity type is used as a base region, and the β-silicon carbide layer (3) of one conductivity type is used as an emitter region. Achieved by IIBT.
本発明はワイトギャソプエミソタ層としてβ−５ｉＣを
用い、素子特性を改善する。The present invention improves device characteristics by using β-5iC as a Wight Gassop emitter layer.
ＳｉＣは六方晶系等のα−３ｉＣと、立方晶系のβ−Ｓ
ｉＣと力くあるが、ｌノイｉ゛ギャップ上ミッタ層形成
にはＳｉと同一品系のβ−５ｉＣを用いる。SiC consists of hexagonal system α-3iC and cubic system β-S.
Although it is strongly referred to as iC, β-5iC, which is the same product as Si, is used to form the transmitter layer above the lnoi gap.
ＳｉＣの結晶成長は、一般に高温成長を必要とし困難で
あるが、本発明者により単結晶ＳｉＣをｌ０ｆ）０°Ｃ
程度で、約２００Ｐａの減圧下で気相成長する技術を開
発した。Crystal growth of SiC generally requires high-temperature growth and is difficult, but the inventor has developed single-crystal SiC at
We have developed a technology for vapor phase growth under reduced pressure of approximately 200 Pa.
また、本発明者により単結晶ＳｉＣのボール（Ｉｌａｌ
ｌ）易動度はＳｉと同程度、あるいはそれ以」二の値を
もち、また、ＳｉＣ／Ｓｉヘテロ接合の整流比が大きく
、拡散電流は主として接合を流れることを実験的に確か
めた。In addition, the inventor has also developed a single crystal SiC ball (Ilal
l) It has been experimentally confirmed that the mobility is on the same level as, or even higher than, that of Si, and that the rectification ratio of the SiC/Si heterojunction is large, and that the diffusion current mainly flows through the junction.
これらの結果より、単結晶β−５ｉＣエミツタバイポー
ラトランジスタは高いエミッタ効率をもぢ、換言すれば
低ベース抵抗をもら、ν１、Ｓｉ用の高速バイポーラト
ランジスタとして適していることが分かった。From these results, it was found that the single crystal β-5iC emitter bipolar transistor has high emitter efficiency, in other words, low base resistance, and is suitable as a high speed bipolar transistor for ν1, Si.
第５図はＳｉＣワイドエミッタハイポーラトランジスタ
のエネルギハンド構造図である。FIG. 5 is a diagram showing the energy hand structure of a SiC wide emitter hyperpolar transistor.
図において、Ｅｃ、ＥＶ、ＥＦはそれぞれ伝導帯の下端
、価電子帯の上端、フェルミ準位を示し、黒丸で示され
る電子と白丸で示される正孔の流れを矢印で表す。In the figure, Ec, EV, and EF indicate the lower end of the conduction band, the upper end of the valence band, and the Fermi level, respectively, and the flow of electrons indicated by black circles and holes indicated by white circles are indicated by arrows.
エミッタ領域がワイドギャップであるため生ずる障壁に
より、正孔のエミッタへの注入が起こり難い様子を模式
的に矢印で示している。The arrows schematically show how holes are difficult to be injected into the emitter due to the barrier caused by the wide gap in the emitter region.
その結果、−・−スミ流を低下さ−Ｕ“、エミッタの注
入効率が増加する。As a result, the emitter injection efficiency is increased by reducing the smear flow.
つぎに、参考のためにβ−３ｉＣの電気的緒特性を、Ｓ
ｉ１ガリウム砒素（ＧａＡｓ）と比較してつぎに示す。Next, for reference, the electrical characteristics of β-3iC are shown in S
A comparison with i1 gallium arsenide (GaAs) is shown below.
いま、
飽和電子速度： νｓ （ｃｍ ｓ−’）破壊電界強度
：ＥＣ（シｃｍ−’）
誘電率
熱伝導率 ：λ （’Ｗｃｍ−’°Ｃ−１）ジョンソ
ン指標（高周波大電力指標）
： ＺＪ （Ｖ” ｓ−”）
キース指標（小型化指標）
： ＺＫ（Ｗ ｓ−’°Ｃ−１）
（ここに、ジョンソン指標ＺＪ 、キース指標Ｚうは半
導体性能指標で、上記の元を有する）とすると、つぎの
ようになる。Now, Saturated electron velocity: νs (cm s-') Breakdown electric field strength: EC (cm-') Dielectric constant thermal conductivity: λ ('Wcm-'°C-1) Johnson index (high frequency high power index): ZJ (V"s-") Keith index (miniaturization index): ZK (W s-'°C-1) (Here, Johnson index ZJ, Keith index Z is a semiconductor performance index, which has the above element ), it becomes as follows.
特性 Ｓｉ ＧａＡｓ β−５ｉｌ：
ｌＸｌＯ７２ＸｉＯ７２ＸｌＯ’
Ｅｃ ２Ｘ］０’ ３ＸＩＯ５５Ｘ］０６
ε １２ １） ９．７λ
１．５ ０．５ ５．ＯＺＪ ３
．２Ｘ１０” １．９Ｘ１０”８．０ＸＩＯ”ＺＫ６
．７Ｘ１０’ ３．２Ｘ１０７３．１Ｘ１０”」１表
に示されるように、β−５ｉＣはＳｉ 、 ＧａＡｓよ
り、ｚｌ、Ｚ、ともに１〜３桁優れていることが分かる
。Characteristics Si GaAs β-5il:
lXlO72XiO72XlO' Ec 2X]0' 3XIO55X]06
ε 12 1) 9.7λ
1.5 0.5 5. OZJ 3
．． 2X10” 1.9X10”8.0XIO”ZK6
．． 7X10'3.2X1073.1X10''1 As shown in Table 1, it can be seen that β-5iC is superior to Si and GaAs in both zl and Z by 1 to 3 orders of magnitude.
〔実施例〕
第１図は本発明の一実施例によるβ−３ｉＣワイドギヤ
ソブエミソタバイボーラトランジスタの構造を示す断面
図である。[Embodiment] FIG. 1 is a sectional view showing the structure of a β-3iC wide-gear semi-stable bipolar transistor according to an embodiment of the present invention.
図はｎｐｎ）ランジスタの例をを示す。The figure shows an example of an npn) transistor.
図において、４はｎ型珪素（ｎ−５ｉ）基板で、ここに
深さ １μｍのｎ゛型コレクタコンタクト領域５をイオ
ン注入により形成する。In the figure, reference numeral 4 denotes an n-type silicon (n-5i) substrate, on which an n-type collector contact region 5 with a depth of 1 μm is formed by ion implantation.
イオン注入条件は、砒素イオン（Ａｓ”）を用い、エネ
ルギ１２０ＫｅＶ、 ｌｊ−ズ量１０１７ｃｍ−２で
ある。The ion implantation conditions were as follows: arsenic ions (As'') were used, the energy was 120 KeV, and the lj-phase amount was 1017 cm-2.
この上に、一導電型半導体層として厚さ１μｍ、抵抗率
１Ωｃｍのｎ−５ｉ層ｌを成長する（コレクタ領域）。On top of this, an n-5i layer l having a thickness of 1 μm and a resistivity of 1 Ωcm is grown as a semiconductor layer of one conductivity type (collector region).
ｎＳｉ層】の表面に、他導電型半導体層としてイオン注
入により厚さ１０００人のｎ型珪素（ｐ−３ｉ）層２を
形成する（ベース領域）。On the surface of the nSi layer, an n-type silicon (p-3i) layer 2 with a thickness of 1000 nm is formed as a semiconductor layer of another conductivity type by ion implantation (base region).
イオン注入条件は、硼素イオン（Ｂ゛）を用い１．１ネ
ルギ４０ ＫｅＶ、 ｌ−ズ量１０１３ｃｍ−２であ
る。The ion implantation conditions are as follows: boron ions (B') are used, 1.1 energy is 40 KeV, and the l-ise amount is 1013 cm-2.
つぎに、ｐ−Ｓｉ層２の」二に厚さ４０００人の二酸化
珪素（ＳｉＯｚ）層６を被着し、エミツタ窓７を開口す
る。Next, a silicon dioxide (SiOz) layer 6 with a thickness of 4,000 wafers is deposited on the top of the p-Si layer 2, and an emitter window 7 is opened.
つぎに１．減圧化学気相成長（ＬＰＧＶＤ）法により、
基板全面に厚さ２０００人のβ−３ｉＣ層を成長し、イ
オン注入により、β−３ｉＣ層にｌ・−プしてｎ型にす
る。Next 1. By low pressure chemical vapor deposition (LPGVD) method,
A β-3iC layer with a thickness of 2000 μm is grown over the entire surface of the substrate, and the β-3iC layer is made into an n-type by ion implantation.
つぎに、通常のりソグラフイによりパターニングしてエ
ミツタ窓７を覆って一導電型β ＳｉＣ層としてｎ型β
−３ｉＣ層３を形成する（１ミツタ領域）・
β−３ｉＣのＣＶＤ条件は、ソースガスとして三塩化シ
ラン（ＳｉＨＣｈ）とプロパン（Ｃｓ Ｈｅ ）、キャ
リアガスとして水素（１）□）を用い、これらを２００
Ｐδに減圧し、１０００℃で熱分解して行う。Next, the emitter window 7 is patterned by ordinary glue lithography to form a one-conductivity type β SiC layer and an n-type β SiC layer.
Forming the -3iC layer 3 (1 Mitsuta region) - CVD conditions for β-3iC include using silane trichloride (SiHCh) and propane (Cs He ) as the source gas and hydrogen (1)□) as the carrier gas. 200
The pressure is reduced to Pδ and thermal decomposition is carried out at 1000°C.
イオン注入条件は、Ａｓ’を用い、エネルギ１２０Ｋｅ
Ｖ 、 ドーズ量Ｉ Ｑ １６ ｃ ｍ −２である
。The ion implantation conditions were As' and an energy of 120Ke.
V and the dose IQ 16 cm −2.
最後に、エミッタコンタク１一層として、多結晶珪素（
ポリＳｉ） Ｎをβ−３ｉＣ層３を覆って成長し、パタ
ーニングしてポリＳｉ層８を形成する。Finally, as the emitter contact 1 layer, polycrystalline silicon (
Poly-Si)N is grown over the β-3iC layer 3 and patterned to form a poly-Si layer 8.
つぎに、本発明人によるβ−５ｉＣの特性の測定結果を
第２〜４図に示す。Next, the measurement results of the characteristics of β-5iC by the present inventor are shown in FIGS. 2 to 4.
以下に記載のアニールはいずれもドライ窒素中で３０分
行う。All annealing described below is performed in dry nitrogen for 30 minutes.
第２図はドーズ量をパラメータとしてβ−５ｉＣの抵抗
率とアニール温度の関係図である。FIG. 2 is a diagram showing the relationship between the resistivity and annealing temperature of β-5iC using the dose as a parameter.
同一ドーズ量に対してアニール温度が高いほど抵抗率は
減少し、結晶性は悪くなる。The higher the annealing temperature is for the same dose, the lower the resistivity and the worse the crystallinity.
第３図はアニール温度をパラメータとしてβ−５ｉＣの
ホール易動度とキャリア濃度の関係図である。FIG. 3 is a diagram showing the relationship between hole mobility and carrier concentration of β-5iC using annealing temperature as a parameter.
アニール温度が１０００℃において、キャリア濃度が１
０１７ｃｍ−３で、ボール易動度は約４５０ ｃｍ２Ｖ
−’ｓ−’と高い値が得られた。When the annealing temperature is 1000℃, the carrier concentration is 1
017 cm-3, the ball mobility is about 450 cm2V
A high value of -'s-' was obtained.
図中、破線でＳｉ単結晶の場合を示す。In the figure, the broken line indicates the case of Si single crystal.
第４図はＡｓのドーズ量をパラメータとしてβ−５ｉＣ
のホール易動度とアニール温度の関係図である。Figure 4 shows β-5iC using the As dose as a parameter.
FIG. 2 is a diagram showing the relationship between hole mobility and annealing temperature.
同一ドーズ量に対してアニール温度が高いほどボール易
動度は減少し、結晶性は悪くなる。The higher the annealing temperature is for the same dose, the lower the ball mobility and the worse the crystallinity.
以上第２〜４図に示される特性のβ−５ｉＣが得られた
ことにより、これをワイドギャップエミッタとして用い
たバイポーラトランジスタはつぎのような特徴をもつ。Since β-5iC having the characteristics shown in FIGS. 2 to 4 has been obtained, a bipolar transistor using this as a wide gap emitter has the following characteristics.
（１）ワイドギャップエミッタの作用により、へ−スミ
流を低下さ・ｌることが可能。(1) Due to the action of the wide gap emitter, it is possible to reduce the Hesmi flow.
（高入力抵抗のトランジスタが得られる）（１−１）従
って、トランジスタのファンイン、ファンアウトを大き
くできる。(A transistor with high input resistance can be obtained) (1-1) Therefore, the fan-in and fan-out of the transistor can be increased.
（１−２）また、ベース電流の低下によりアルミニウム
（ＡＩ）配線中を流れる電流密度を低減できる。(1-2) Furthermore, the current density flowing through the aluminum (AI) wiring can be reduced by lowering the base current.
従って、Ａ１層を薄くでき、基板表面の段差が小さくな
るため、層間絶縁層に対する要求が緩和され、高集積化
に適する。Therefore, the A1 layer can be made thinner and the step difference on the substrate surface can be reduced, so that the requirements for the interlayer insulating layer are relaxed and it is suitable for high integration.
（１−３）ベース電極数、形状の制限が緩和される。(1-3) Restrictions on the number and shape of base electrodes are relaxed.
（２）エミツタ層のβ−５ｉＣは、ベース層上に低温Ｃ
ＶＤ法で成長され、かつワイドギヤツブエミッタである
ため比較的低濃度で形成できるため、ベース層を薄く形
成でき、その分だけトランジスタ作用にあずかるベース
内に注入された小数キャリア（第１図の例では電子）の
輸送効率が改善できる。(2) The β-5iC of the emitter layer is a low-temperature C on the base layer.
Since it is grown by the VD method and is a wide gear emitter, it can be formed with a relatively low concentration. Therefore, the base layer can be formed thinly, and the minority carriers injected into the base that participate in the transistor action (as shown in Figure 1) can be formed thinly. For example, the transport efficiency of electrons can be improved.
以上詳細に説明したようにβ−５ｉＣは、（１） β
−５ｉＣのキャリアの易動度はＳｉと同程度、またはそ
れ以上の値をもつ。As explained in detail above, β-5iC is (1) β
The mobility of −5iC carriers is comparable to or higher than that of Si.
（２） β−３ｉＣ／Ｓｉ接合の整流比は大きく、リ
ーク電流が小さい。(2) The β-3iC/Si junction has a large rectification ratio and a small leakage current.
という性質を有し、ワイドギャップエミッタとして実用
上十分使用できることが分かった。It was found that it has the following properties and can be used practically as a wide gap emitter.
さらに、本発明のワイトギャソプエミソタバイボーラト
ランジスタは、β−３ｉＣの最高使用温度が約５００℃
と高いため、トランジスタの使用温度はＳｉのそれによ
ってきまり、従来のワイドギャップエミッタハイポーラ
トランジスタに比し、高電力用として適している。Furthermore, the WightGasop emisotabibolar transistor of the present invention has a maximum operating temperature of β-3iC of approximately 500°C.
Therefore, the operating temperature of the transistor is determined by that of Si, making it more suitable for high power applications than conventional wide-gap emitter hyperpolar transistors.
第１図は本発明の一実施例によるβ−５ｉＣワイドギャ
ソプエミソタハイボーラトランジスタの構造を示す断面
図、
第２図はドーズ量をパラメータとしてβ−５ｉＣの抵抗
率とアニール温度の関係図、
第３図はアニール温度をパラメータとしてβ−３ｉＣの
ホール（ｌｌａｌｌ）易動度とキャリア濃度の関係図・
第４図はＡｓのドーズ量をパラメータとしてβ−ＳｉＣ
のホール易動度とアニール温度の関係図、第５図はＳｉ
Ｃワイドギャソプエミノタバイボーラトランジスタのエ
ネルギバンド構造図である。
図において、
■は一導電型半導体層でｎ−Ｓｉ層
（コレクタ領域）、
２は他導電型半導体層でｐ−Ｓｉ層
（ベース領域）、
３は一導電型β−３ｉＣ層でｎ型β−ＳｉＣ層（エミッ
タ領域）、
４はｎ−５ｉ基板、
５はｎ１型コレクタコンタクト領域、
６はＳｉ０２層、
７はエミツタ窓、
８ばポリＳｉ層
μ」
奪FIG. 1 is a cross-sectional view showing the structure of a β-5iC wide gas pemi-sota high-bolar transistor according to an embodiment of the present invention. FIG. 2 is a relationship between the resistivity and annealing temperature of β-5iC using the dose as a parameter. , Figure 3 shows the relationship between the hole mobility and carrier concentration of β-3iC using the annealing temperature as a parameter. Figure 4 shows the relationship between β-3iC hole mobility and carrier concentration using the annealing temperature as a parameter. Figure 4 shows the relationship between β-SiC using the As dose as a parameter.
Figure 5 shows the relationship between hole mobility and annealing temperature for Si.
FIG. 2 is an energy band structure diagram of a C-wide gasopueminotabybolar transistor. In the figure, 1 is a semiconductor layer of one conductivity type, which is an n-Si layer (collector region), 2 is a semiconductor layer of another conductivity type, which is a p-Si layer (base region), and 3 is a β-3iC layer of one conductivity type, which is an n-type β layer. -SiC layer (emitter region), 4 is n-5i substrate, 5 is n1 type collector contact region, 6 is Si02 layer, 7 is emitter window, 8 is poly-Si layer μ''
Claims (1)
、一導電型β−炭化珪素層（３）を順次成長してなり、
一導電型半導体層（１）をコレクタ領域、他導電型半導
体層（２）をベース領域、一導電型β−炭化珪素層（３
）をエミッタ領域とすることを特徴とするヘテロ接合バ
イポーラトランジスタ。On one conductivity type semiconductor layer (1), another conductivity type semiconductor layer (2)
, one conductivity type β-silicon carbide layer (3) is grown sequentially,
One conductivity type semiconductor layer (1) is the collector region, the other conductivity type semiconductor layer (2) is the base region, and the one conductivity type β-silicon carbide layer (3) is the collector region.
) as an emitter region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5974386A JPH0770540B2 (en) | 1986-03-18 | 1986-03-18 | Heterojunction bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5974386A JPH0770540B2 (en) | 1986-03-18 | 1986-03-18 | Heterojunction bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62216364A true JPS62216364A (en) | 1987-09-22 |
| JPH0770540B2 JPH0770540B2 (en) | 1995-07-31 |
Family
ID=13122013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5974386A Expired - Fee Related JPH0770540B2 (en) | 1986-03-18 | 1986-03-18 | Heterojunction bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770540B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01143261A (en) * | 1987-11-27 | 1989-06-05 | Nec Corp | Semiconductor device |
| EP0390522A2 (en) * | 1989-03-29 | 1990-10-03 | Canon Kabushiki Kaisha | Bipolar transistor and photoelectric conversion apparatus using the same |
| US5247192A (en) * | 1991-09-30 | 1993-09-21 | Rohm Co., Ltd. | Heterojunction bipolar transistor |
| US5536952A (en) * | 1992-03-24 | 1996-07-16 | Sumitomo Electric Industries, Ltd. | Heterojunction bipolar transistor |
| US5668396A (en) * | 1992-11-27 | 1997-09-16 | Nec Corporation | Bipolar transistor having thin intrinsic base with low base resistance and method for fabricating the same |
| US5777363A (en) * | 1993-11-29 | 1998-07-07 | Texas Instruments Incorporated | Semiconductor device with composite drift region |
| JP2009054931A (en) * | 2007-08-29 | 2009-03-12 | Hitachi Ltd | Bipolar element and its manufacturing method |
-
1986
- 1986-03-18 JP JP5974386A patent/JPH0770540B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01143261A (en) * | 1987-11-27 | 1989-06-05 | Nec Corp | Semiconductor device |
| EP0390522A2 (en) * | 1989-03-29 | 1990-10-03 | Canon Kabushiki Kaisha | Bipolar transistor and photoelectric conversion apparatus using the same |
| US5708281A (en) * | 1989-03-29 | 1998-01-13 | Canon Kabushiki Kaisha | Semiconductor device and photoelectric conversion apparatus using the same |
| US5247192A (en) * | 1991-09-30 | 1993-09-21 | Rohm Co., Ltd. | Heterojunction bipolar transistor |
| US5536952A (en) * | 1992-03-24 | 1996-07-16 | Sumitomo Electric Industries, Ltd. | Heterojunction bipolar transistor |
| US5624853A (en) * | 1992-03-24 | 1997-04-29 | Sumitomo Electric Industries, Ltd. | Method for forming heterojunction bipolar transistors |
| US5668396A (en) * | 1992-11-27 | 1997-09-16 | Nec Corporation | Bipolar transistor having thin intrinsic base with low base resistance and method for fabricating the same |
| US5777363A (en) * | 1993-11-29 | 1998-07-07 | Texas Instruments Incorporated | Semiconductor device with composite drift region |
| JP2009054931A (en) * | 2007-08-29 | 2009-03-12 | Hitachi Ltd | Bipolar element and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0770540B2 (en) | 1995-07-31 |
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