JPS62188373A - Thin film transistor - Google Patents

Thin film transistor

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Publication number
JPS62188373A
JPS62188373A JP3033086A JP3033086A JPS62188373A JP S62188373 A JPS62188373 A JP S62188373A JP 3033086 A JP3033086 A JP 3033086A JP 3033086 A JP3033086 A JP 3033086A JP S62188373 A JPS62188373 A JP S62188373A
Authority
JP
Japan
Prior art keywords
beta
sic
layers
grown
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3033086A
Other languages
Japanese (ja)
Inventor
Yuji Furumura
雄二 古村
Fumitake Mieno
文健 三重野
Tsutomu Nakazawa
中沢　努
Kikuo Ito
伊藤　喜久雄
Masahiko Toki
雅彦 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3033086A priority Critical patent/JPS62188373A/en
Publication of JPS62188373A publication Critical patent/JPS62188373A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Abstract

PURPOSE:To obtain a device having a mobility of carrier larger, a leakage current less, the maximum allowable working temperature higher and a semiconductor efficiency index higher than those of conventional FETs consisting of a poly Si film or an a-Si film by forming element on beta-Si dioxide layers grown on an insulator. CONSTITUTION:Elements are formed on beta-Si carbide layers 4 grown on an insulator 3. For example, after an Si carbide layer 2 and the Si nitride layer 3 are grown in order on an Si substrate 1, a beta-SiC layer is grown by a CVD method and patterned and beta-SiC layers 4A and 4B, which demarcade transistor forming regions, are formed. Then, an impurity is doped to the beta-SiC layers 4A and 4B by ion implantation to form a P-channel forming region 4AC for an N-channel transistor and an N-channel forming region 4BC for a P-channel transistor. Then, gate electrodes 6A and 6B consisting of a poly Si film are formed through gate insulating layers 5A and 5B and an impurity is doped to the beta-SiC layers 4A and 4B by ion implantation using those gate electrodes 6A and 6B as masks to form N<+> source regions 4AS and 4AD and P<+> drain regions 4BS and 4BD.

Description

【発明の詳細な説明】 〔概要〕 薄膜トランジスタ（ＴＰＴ）として絶縁体−Ｌに成長さ
れたβ−炭化珪素（β−５ｉＣ）層に電界効果１−ラン
ジスタ（ＦＥＴ）等を形成し、従来のＴＰＴよりキャリ
ア易動度の大きい、リーク電流の少ない、最高使用温度
の高いデバイスを得る。[Detailed Description of the Invention] [Summary] As a thin film transistor (TPT), a field effect transistor (FET) etc. is formed on a β-silicon carbide (β-5iC) layer grown on an insulator-L, and the conventional TPT To obtain a device with higher carrier mobility, lower leakage current, and higher maximum operating temperature.

〔産業上の利用分野〕[Industrial application field]

本発明は半専体性能指標の高いβ−３ｉＣのＶＪ膜トラ
ンジスタに関する。The present invention relates to a β-3iC VJ membrane transistor with a high semi-dedicated performance index.

従来のＴＰＴは絶縁体上に成長された多結晶珪素（ポリ
Ｓｔ）層、または非晶質珪素（アモルファスＳｉ、　ａ
−５ｔ）層に形成され、通常の単結晶の珪素（Ｓｉ）の
ＦＥＴに比し、その性能は劣っていた。Conventional TPT consists of a polycrystalline silicon (polySt) layer grown on an insulator, or an amorphous silicon (amorphous Si, a
-5t) layer, and its performance was inferior to that of a normal single-crystal silicon (Si) FET.

ＴＰＴは例えば、液晶表示の７トリソクスの駆動用デバ
イスとして用いられている。TPT is used, for example, as a driving device for seven trisoxes in a liquid crystal display.

液晶表示のマトリックスは絶縁基板上に形成されるため
、その駆動用に、マトリックスと同様に絶縁基板上に形
成されるＴＰＴが用いられる場合が極めて多い。Since the matrix of a liquid crystal display is formed on an insulating substrate, a TPT, which is formed on an insulating substrate like the matrix, is very often used for driving the matrix.

この場合、液晶は高抵抗負荷のため駆動能力は小さくて
よく、また高速動作も不要のため、高性能のＴＰＴは要
求されなかった。In this case, since the liquid crystal has a high resistance load, only a small driving capacity is required, and high-speed operation is not required, so a high-performance TPT was not required.

しかしながら、近年、用途の多用化、高度化にともない
、ＴＰＴの高性能化が要望されるようになってきた。However, in recent years, as the applications have become more diverse and sophisticated, there has been a demand for higher performance TPT.

〔従来の技術と発明が解決しようとする問題点〕前記の
ように、従来のＴＰＴはポリＳｉ層、またはａ−３ｉ層
が用いられているが、これらの材料を用いた場合の問題
点は、つきのよってある。[Prior art and problems to be solved by the invention] As mentioned above, conventional TPT uses a poly-Si layer or an a-3i layer, but the problems when using these materials are as follows. , according to Tsukino.

（１）　　ギヤリアの易動度が小さい。(1) Gear rear mobility is low.

（２）ポリＳｔのグレインの界面準位が多いため、単結
晶Ｓｔの場合より、リーク電流が極端に大きい。(2) Since there are many interface levels of grains in poly-St, the leakage current is extremely larger than in the case of single-crystal St.

ａ−３ｉの場合はさらに大きい。In the case of a-3i, it is even larger.

（３）最高使用温度が約２００°Ｃと低い。(3) The maximum operating temperature is low at approximately 200°C.

〔問題点を解決するための手段〕[Means for solving problems]

−に記問題点の解決は、絶縁体上に成長されたβ−炭化
珪素層に形成してなる本発明による薄膜トランジスタに
より達成される。The problems described in (1) and (2) are solved by the thin film transistor according to the present invention formed in a β-silicon carbide layer grown on an insulator.

とくに、前記絶縁体に窒化珪素を用いると、成長核の生
成によりβ−炭化珪素の成長が容易である。In particular, when silicon nitride is used as the insulator, growth of β-silicon carbide is easy due to the generation of growth nuclei.

〔作用〕[Effect]

本発明は素子（トランジスタ等）形成層としてβ−５ｉ
Ｃを用い、素子特性を散着する。The present invention uses β-5i as an element (transistor, etc.) forming layer.
Using C, the element characteristics are scattered.

ＳｉＣは六方晶系のα−５ｉＣと、立方晶系のβ−５ｉ
Ｃとがあるが、素子形成にはＳｉと同一品系のβ−３ｉ
Ｃを用いる。SiC consists of hexagonal α-5iC and cubic β-5i
There is β-3i, which is the same product as Si, for element formation.
Use C.

ＳｉＣの結晶成長は、高温成長を必要とし回道１である
か、本発明人により多結晶ＳｉＣを１０００℃程度で気
相成長する技術を開発した。Crystal growth of SiC requires high-temperature growth, which is route 1, and the inventor has developed a technique for growing polycrystalline SiC in a vapor phase at about 1000°C.

ＳｉＣは単結晶化が困難であるが、　ＴＰＴに多結晶β
−３ｉＣを用いても、次表に示されるように、電気的特
性は従来のポリＳｉ、またはａＳｌより優れている。SiC is difficult to form into a single crystal, but polycrystalline β can be formed into TPT.
Even when -3iC is used, the electrical properties are superior to conventional poly-Si or aSl, as shown in the following table.

電子の易動度　リーク電流 （ｃｍ２シー’ｓ−’）　　　　（八　ｃｍ−２）多結
晶β−３ｉＣ１０〜５００　　　　＜　１０−’ポリ５
ｉＸａ−３ｉ　　　　　Ｏ，１〜１０　　１０−’　　
〜１０゜単結晶Ｓｉ　　　　　　〜１５００　　　１０
−”〜ＩＱ−１１このように、多結晶の場合でもβ−３
ｉＣの易動度が高いのは、成長温度がポリＳｉ、　ａ−
５ｔより高いため、グレイン界面の不純物が減少するた
めと考えられる。Electron mobility Leakage current (cm2 C's-') (8 cm-2) Polycrystalline β-3iC10~500 <10-' Poly5
iXa-3i O,1~10 10-'
~10゜Single crystal Si ~1500 10
−”~IQ-11 In this way, even in the case of polycrystalline β-3
The high mobility of iC is due to the growth temperature of poly-Si, a-
It is thought that this is because impurities at the grain interface are reduced because it is higher than 5t.

つぎに、参Ｊシのためにβ−５ｉＣの電気的諸特性を、
Ｓｉ１ガリウム砒素（ＧａＡｓ）と比較してつぎに示す
。Next, for reference, we will explain the electrical characteristics of β-5iC.
A comparison with Si1 gallium arsenide (GaAs) is shown below.

いま、 飽和電子速度：　　ＶＳ（ｃｍ　ｓ−’）破壊電界強度
：　　１４ｃ（Ｖ　ｃｍ−’）誘電率　　　：ε 熱伝導率　　：λ　（ＩＡ　ｃｍ−”Ｃ−’）ジョンソ
ン指標（高周波大電力指標） ：　　Ｚ、＋　（Ｖ２ｓ−”） キース指標（小型化指標） ：　　ＺＫ　（１＋ｌ　ｓ−’℃−′）（ここに、ジョ
ンソン指標Ｚ１、キース指標ＺＫは半導体性能指標で、
上記の元を有する）とすると、つぎのようになる。Now, Saturated electron velocity: VS (cm s-') Breakdown electric field strength: 14c (V cm-') Dielectric constant: ε Thermal conductivity: λ (IA cm-"C-') Johnson index (high frequency high power index) : Z, + (V2s-'') Keith index (miniaturization index): ZK (1+l s-'℃-') (Here, Johnson index Z1 and Keith index ZK are semiconductor performance indexes,
) having the above elements, we get the following.

特性　　　　Ｓｉ　　　　ＧａＡｓ　　　β−５ｉＣＩ
ＸＩＯ’　　　　２Ｘ１０’　　　　２ｘｌＯ’Ｅｃ　
　　　　　２ｘｌＯ５３Ｘ１０’　　　　５ＸＩＯ６８
１２１１９，７ λ　　　　　　　　１．５　　　　　　０．５　　　　
　５．０ＺＪ　　　　　３．２Ｘ１０”’　　１．９×
ｉｏ”８．０Ｘ１０２６ＺＫ　　　　　６．７Ｘ１０’
　　　３．２Ｘ１０’　　３．ｌＸ１０Ｒ上表に示され
るように、β−３ｉＣはＳｉ　、　ＧａＡｓより、Ｚ４
、Ｚｘともに１〜３桁優れていることが分かる。Characteristics Si GaAs β-5iCI
XIO'2X10'2xlO'Ec
2xlO53X10' 5XIO68
12119,7 λ 1.5 0.5
5.0ZJ 3.2X10”' 1.9×
io"8.0X1026ZK 6.7X10'
3.2X10' 3. lX10R As shown in the above table, β-3iC is more effective than Si or GaAs,
It can be seen that both Zx and Zx are superior by one to three orders of magnitude.

〔実施例〕〔Example〕

第１図は本発明によるβ−５ｉＣのＴＰＴの構造を示す
断面図である。FIG. 1 is a cross-sectional view showing the structure of a β-5iC TPT according to the present invention.

図の左はｎチャネルトランジスタ、右はｐチャネルトラ
ンジスタを示す。The left side of the figure shows an n-channel transistor, and the right side shows a p-channel transistor.

図において、■はＳｉ基板で、この上に厚さ１１００ｎ
の二酸化珪素（Ｓｉ（ｈ）層２、厚さ１１００ｎの窒化
珪素（Ｓｉ：＋Ｎａ）層３を順次成長する。In the figure, ■ is a Si substrate with a thickness of 1100 nm on top of this.
A silicon dioxide (Si(h) layer 2 and a silicon nitride (Si:+Na) layer 3 having a thickness of 1100 nm are sequentially grown.

つぎに、化学気相成長（ＣＶＤ）法により、恭仮全面に
厚さ２００ｎｍのβ−３ｉＣ層を成長し、通常のりソグ
ラフイによりバターニングして、トランジスタ形成領域
を画定するβ−５ｉＣ層４八、４Ｂを形成する。Next, a β-3iC layer with a thickness of 200 nm is grown on the entire surface by chemical vapor deposition (CVD), and patterned by ordinary lamination to form a β-5iC layer 48 that defines the transistor formation region. , 4B.

β−３ｉＣのＣＶＩ］条件は、ソースガスとして三塩化
シラン（ＳｉＨ（：ｈ）とプロパン＜ｃ３１１１１）、
キャリアガスとして水素（Ｈ２）を用い、これらを２０
０Ｐａに減圧し、１０００℃で熱分解して行う。CVI of β-3iC] The conditions were: trichlorosilane (SiH (:h) and propane<c31111) as the source gas;
Using hydrogen (H2) as a carrier gas, these
The pressure is reduced to 0 Pa and thermal decomposition is carried out at 1000°C.

つぎに、イオン注入により、β−３ｉＣ層４八、４Ｂに
ドーピングして、 ｎチャネルトランジスタに対しては、ｐ型のチャネル形
成領域４ＡＣを形成する。Next, the β-3iC layers 48 and 4B are doped by ion implantation to form a p-type channel formation region 4AC for an n-channel transistor.

ｐチャネルトランジスタに対しては、ｎ型のチャネル形
成領域４８Ｃを形成する。For a p-channel transistor, an n-type channel formation region 48C is formed.

つぎに、ｎ、ｐチャネルトランジスタに対してそれぞれ
ゲート絶縁層５八、５Ｂを介して、ポリＳｉよりなるゲ
ート電極６Ａ、６Ｂを形成する。Next, gate electrodes 6A and 6B made of poly-Si are formed for n- and p-channel transistors via gate insulating layers 58 and 5B, respectively.

つぎに、ケート電極６＾、６Ｂをマスクにしたイオン注
入により、β−５ｉＣ層４＾、４Ｂにドーピングして、 ｎチャネルトランジスタに対しては、ｎ＋型のソース、
ドレイン領域４八Ｓ、４八りを形成する。Next, the β-5iC layers 4^, 4B are doped by ion implantation using the gate electrodes 6^, 6B as masks, and for the n-channel transistor, an n+ type source,
Drain regions 48S and 48R are formed.

ｐチャネルトランジスタに文１１シては、ｐ′型のソー
ス、ドレイン領域４ＢＳ　、４ＢＤを形成する。In the p-channel transistor, p'-type source and drain regions 4BS and 4BD are formed.

イオン注入の条件は、つきのとおりである。The conditions for ion implantation are as follows.

領域　　ドース量　　エネルギ　　イオン（ｃｍ−２）
　　　（ｋｅＶ） ｎ　“　　：　　　　　２ｘｌＯ１６１２０八Ｓ゛ｎ　
　　　：　　　　　４Ｘ１０”　　　　　　１２０　　
　　　　　　　　　八Ｓ゛ｐ″″　：　　　２Ｘ１０１
６４０　　　　　　Ｂ”ｐ　　：　　　４ｘ１０１３４
０　　　　　　Ｂ゛つぎに、ｎチャネルトランジスタに
対しては、ニッケル（Ｎｉ）層でオーミック電極、すな
わちソース、ドレイン電極７Ｓ、７Ｄを形成する。Area Dose Energy Ion (cm-2)
(keV) n “: 2xlO161208S゛n
: 4X10" 120
8 S゛p″″: 2X101
640 B”p: 4x10134
0B Next, for the n-channel transistor, ohmic electrodes, that is, source and drain electrodes 7S and 7D are formed using a nickel (Ni) layer.

ｐチャネルトランジスタ ウム（ＡＩ）層でオーミック電極、すなわちソース、ド
レイン電極８Ｓ、８Ｄを形成する。Ohmic electrodes, that is, source and drain electrodes 8S and 8D are formed using a p-channel transistor (AI) layer.

以上により、β−ＳｉＣのＴＰＴが形成される。Through the above steps, a β-SiC TPT is formed.

基板に、ＳｔＪｔ　／　ｓｉｏｚ／ｓ＋構造を用いたの
は、Ｓｉ．Ｎ４上には前記のようにＳｉＣの成長核が生
成しやすいためである。The StJt/sioz/s+ structure was used for the substrate because Si. This is because SiC growth nuclei are likely to be generated on N4 as described above.

また、硬いＳｉ３Ｎ４に対し、ＳｉＯ□を挟んでストレ
スを緩和した。Additionally, stress was alleviated by sandwiching SiO□ against hard Si3N4.

以下に、本発明人によるβ−ＳｉＣの特性の測定結果を
第２〜４図に示す。Below, the measurement results of the characteristics of β-SiC by the present inventor are shown in FIGS. 2 to 4.

以下に記載のアニールはいずれもドライ窒素中で３０分
行う。All annealing described below is performed in dry nitrogen for 30 minutes.

第２図はドーズ量をパラメータとして多結晶β−ＳｉＣ
の抵抗率とアニール温度の関係図である。Figure 2 shows polycrystalline β-SiC using the dose as a parameter.
FIG. 3 is a relationship diagram between resistivity and annealing temperature.

同一ドーズ量に対してアニール温度が高いほど抵抗率は
減少し、結晶性は悪くなる。The higher the annealing temperature is for the same dose, the lower the resistivity and the worse the crystallinity.

第３図はアニール温度をパラメータとして多結晶β−Ｓ
ｉＣのホール（ｌｌａｌｌ）易動度とキャリア濃度の関
係図である。Figure 3 shows polycrystalline β-S with annealing temperature as a parameter.
FIG. 2 is a diagram showing the relationship between iC hole (llall) mobility and carrier concentration.

アニール温度が１０００°Ｃにおいて、キャリア濃度が
１０１７ｃｍ−１で、ホール易動度は約４５０　ｃｍ２
Ｖ−’ｓ−’と高い値が得られた。When the annealing temperature is 1000 °C, the carrier concentration is 1017 cm-1, and the hole mobility is about 450 cm2.
A high value of V-'s-' was obtained.

図中、点線でＳｉ単結晶の場合を示す。In the figure, the dotted line indicates the case of Si single crystal.

第４図はＡｓのドーズ量をパラメータとして多紀ｉ晶β
−ＳｉＣのボール易動度とアニール温度の関係図である
。Figure 4 shows the Taki i-crystal β using the As dose as a parameter.
- It is a relationship diagram of SiC ball mobility and annealing temperature.

同一ドース量に対してアニール温度が高いほどホール易
動度は減少し、結晶性は悪くなる。The higher the annealing temperature is for the same dose, the more the hole mobility decreases and the crystallinity worsens.

つぎに、素子形成に必要なエツチングの選択性と、β−
ＳｉＣの成長装置について第５図と第６図で説明する。Next, we will discuss the etching selectivity necessary for device formation and β-
The SiC growth apparatus will be explained with reference to FIGS. 5 and 6.

第５図はβ−ＳｉＣと八１に対するエツチングレートと
圧力との関係図である。FIG. 5 is a diagram showing the relationship between etching rate and pressure for β-SiC and 81.

この場合のエツチングは、エツチングガスとして三弗化
窒素（ＮＦ３）を用い、周波数１３．５６ＭＩｌｚの電
力を２００Ｗ加えて行った。Etching in this case was carried out using nitrogen trifluoride (NF3) as an etching gas and applying a power of 200 W at a frequency of 13.56 MIlz.

図より分かるように、減圧すると選択比が大きくとれる
。As can be seen from the figure, the selection ratio can be increased by reducing the pressure.

この、選択性を利用して八１をマスクとしてβ−ＳｉＣ
のエツチングができる。By using this selectivity and using 81 as a mask, β-SiC
Can be etched.

第６図（１）、（２）はそれぞれβ−ＳｉＣの成長装置
のブロック図と、成長室内の側断面図である。FIGS. 6(1) and 6(2) are a block diagram of a β-SiC growth apparatus and a side sectional view of the inside of the growth chamber, respectively.

第６図（１）において、６１は成長室、６２ば５ｉｌｌ
Ｃｈバブリング装置、６３はＣ３Ｉ＋　８容器、６４は
１１□導入Ｉ］、６５ハ８ＫＩＩｚの発振器、６６ばワ
ークコ・イル、〔；７はメカニカルブースタポンプ、６
８はロータリポンプである。In Figure 6 (1), 61 is a growth chamber, 62 is a 5ill
Ch bubbling device, 63 is C3I+ 8 container, 64 is 11□Introduction I], 65 is 8KIIz oscillator, 66 is work coil, [;7 is mechanical booster pump, 6
8 is a rotary pump.

第６図（２）において、成長室６１内に、ガス流と垂直
に複数のＳｉＣ被覆のグラファイト製のザセブタ６９が
並置され、ザセプタ６９に設けられた溝（とくに図示せ
ず）に基板７０が保持される。In FIG. 6(2), a plurality of SiC-coated graphite zasepta 69 are arranged in parallel perpendicularly to the gas flow in a growth chamber 61, and a substrate 70 is inserted into a groove (not particularly shown) provided in the zasepta 69. Retained.

実施例においては、ＴＰＴ単体の構成について説明した
が、ＴＰＴを含む半導体装置についても発明の要旨は変
わらない。In the embodiments, the configuration of a single TPT has been described, but the gist of the invention does not change for a semiconductor device including a TPT.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によるβ−３ｉＣのＴ
ＰＴは、従来のポリＳｉ、またはａ−３ｔのＴＰＴより
、 （１）　　キャリアの易動度が大きい。As explained in detail above, the T of β-3iC according to the present invention
PT has (1) greater carrier mobility than conventional poly-Si or a-3t TPT.

（２）　　リーク電流が小さい。(2) Leakage current is small.

（３）最高使用温度が約５００°Ｃと高い。(3) The maximum operating temperature is high at approximately 500°C.

この結果、さらに従来の３１、またはＧａ／Ｉｓよりも
半導体性能指標の高いデバイスが得られるようになった
。As a result, it has become possible to obtain a device with a higher semiconductor performance index than the conventional 31 or Ga/Is.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明によるβ−ＳｉＣのＴＰＴの構造を示す
断面図、 第２図はドーズ量をパラメータとして多結晶β−５ｉＣ
の抵抗率とアニール温度の関係図、第３図はアニール温
度をパラメータとして多結晶β−５ｉＣのホール（ｌｌ
ａｌｌ）易動度とキャリア濃度の関係図、 第４図はへＳのドーズ量をパラメータとして多結晶β−
５ｉＣのボール易動度とアニール温度の関係図、 第５図はβ−３ｉＣとＡＩに対するエツチングレートと
圧力との関係図、 第６図（１）、（２）はそれぞれβ−３ｉＣの成長装置
のブロック図と、成長室内の側断面図である。 図において、 １はＳｉ基板、 ２は５ｔ（ｈ層、 ３はＳｉ３Ｎ４層、 ４Ａ、　４Ｂはβ−３ｉＣ層、 ５八、５Ｂはゲート客色縁層、 ６＾、６Ｂはゲート電極、 ４＾Ｃ４ＢＣはチャネル形成領域、 ４八Ｓ　　、　　４ＡＤ　　、　　４ＢＳ　　、　　４
ＢＤ　　はソース、ドレイン領域、 ７Ｓ、　７Ｄ、　８Ｓ、　８Ｄはソース、ドレイン電極
７二−／ｌ／望し虻（・Ｃ）Figure 1 is a cross-sectional view showing the structure of β-SiC TPT according to the present invention, and Figure 2 is a polycrystalline β-5iC using the dose as a parameter.
Figure 3 shows the relationship between the resistivity and annealing temperature of polycrystalline β-5iC using the annealing temperature as a parameter.
all) Relationship diagram between mobility and carrier concentration, Figure 4 shows polycrystalline β-
Figure 5 is a diagram of the relationship between ball mobility and annealing temperature for 5iC. Figure 5 is a diagram of the relationship between etching rate and pressure for β-3iC and AI. Figures 6 (1) and (2) are the growth apparatus for β-3iC. FIG. 2 is a block diagram of the system and a side cross-sectional view of the interior of the growth chamber. In the figure, 1 is the Si substrate, 2 is the 5T (h layer, 3 is the Si3N4 layer, 4A, 4B are the β-3iC layers, 58, 5B are the gate color edge layers, 6^, 6B are the gate electrodes, 4^ C4BC is the channel forming region, 48S, 4AD, 4BS, 4
BD is the source and drain region, 7S, 7D, 8S, 8D are the source and drain electrodes

Claims (2)

【特許請求の範囲】[Claims] （１）絶縁体上に成長されたβ−炭化珪素層に形成して
なることを特徴とする薄膜トランジスタ。(1) A thin film transistor characterized in that it is formed on a β-silicon carbide layer grown on an insulator. （２）前記絶縁体が窒化珪素であることを特徴とする特
許請求の範囲第１項記載の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the insulator is silicon nitride.
JP3033086A 1986-02-14 1986-02-14 Thin film transistor Pending JPS62188373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3033086A JPS62188373A (en) 1986-02-14 1986-02-14 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3033086A JPS62188373A (en) 1986-02-14 1986-02-14 Thin film transistor

Publications (1)

Publication Number Publication Date
JPS62188373A true JPS62188373A (en) 1987-08-17

Family

ID=12300798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3033086A Pending JPS62188373A (en) 1986-02-14 1986-02-14 Thin film transistor

Country Status (1)

Country Link
JP (1) JPS62188373A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6459851A (en) * 1987-08-31 1989-03-07 Fujitsu Ltd Manufacture of soi wafer
US5216264A (en) * 1989-06-07 1993-06-01 Sharp Kabushiki Kaisha Silicon carbide MOS type field-effect transistor with at least one of the source and drain regions is formed by the use of a schottky contact
US5264721A (en) * 1989-04-29 1993-11-23 Fujitsu Limited Insulated-gate FET on an SOI-structure
US5326991A (en) * 1991-09-24 1994-07-05 Rohm Co., Ltd. Semiconductor device having silicon carbide grown layer on insulating layer and MOS device
US5342174A (en) * 1992-11-02 1994-08-30 Lasko Metal Products, Inc. Foot for fans
US5583369A (en) * 1992-07-06 1996-12-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6459851A (en) * 1987-08-31 1989-03-07 Fujitsu Ltd Manufacture of soi wafer
US5264721A (en) * 1989-04-29 1993-11-23 Fujitsu Limited Insulated-gate FET on an SOI-structure
US5216264A (en) * 1989-06-07 1993-06-01 Sharp Kabushiki Kaisha Silicon carbide MOS type field-effect transistor with at least one of the source and drain regions is formed by the use of a schottky contact
US5326991A (en) * 1991-09-24 1994-07-05 Rohm Co., Ltd. Semiconductor device having silicon carbide grown layer on insulating layer and MOS device
US5518953A (en) * 1991-09-24 1996-05-21 Rohm Co., Ltd. Method for manufacturing semiconductor device having grown layer on insulating layer
US5583369A (en) * 1992-07-06 1996-12-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US5342174A (en) * 1992-11-02 1994-08-30 Lasko Metal Products, Inc. Foot for fans

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