JPS62210725A - Output buffer circuit system - Google Patents
Output buffer circuit systemInfo
- Publication number
- JPS62210725A JPS62210725A JP61052432A JP5243286A JPS62210725A JP S62210725 A JPS62210725 A JP S62210725A JP 61052432 A JP61052432 A JP 61052432A JP 5243286 A JP5243286 A JP 5243286A JP S62210725 A JPS62210725 A JP S62210725A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- output buffer
- output
- current noise
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000872 buffer Substances 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 abstract 1
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は大規模論理集積回路に係り、特に多数個のビン
が同時に動作するｅＭＯ８論理回路に好適な出力バヅフ
ァ回路方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to large-scale logic integrated circuits, and particularly to an output buffer circuit system suitable for an eMO8 logic circuit in which a large number of bins operate simultaneously.
Ｎ形ＭＯＳトランジスタによるプツシニブル出力バッフ
ァはｒＭＯ８ＬＳＩ設計入門Ｊ（１９８４年産業因書発
行の２０１頁に記載のように、従来より知られており、
厖動力の高い出力回路として用いられて来たが、同時駆
動による電源ノイズに対する配慮がされていなかった。Pushinable output buffers using N-type MOS transistors have been known for a long time, as described in rMO8LSI Design Introduction J (Industrial Issues, 1984, p. 201).
Although it has been used as an output circuit with high power, no consideration was given to power supply noise caused by simultaneous driving.
上記従来技術は第２図にて見られる様に、バス入力Ａ１
〜Ａｎが同時には入ることにより、バス出力Ｂ１〜Ｂｓ
が同時に動作し、大きな充放電電流が電源ＶＤＤ及び接
地Ｖｓｓへの抵抗Ｒやインダク４ンスＬの共通給電イン
ピーダンスを介して流れ、波形Ｄυ及びＳＳに示す電流
ノイズが発生し、これがその他の出力バッファに混入す
る。従って出力バヅファの入力Ｃ１及び入力Ｃ２に対応
しない擬パルスが出力υ１及びＬ）２に出て次段での誤
動作を招く。従って同時駆動本数の制限や、電源ＶＤＤ
及び接地Ｖｓｓのピン数追加等の問題があった。As shown in FIG. 2, the above conventional technology has bus input A1.
~An are input at the same time, so that the bus outputs B1 to Bs
operate at the same time, and a large charge/discharge current flows through the common power supply impedance of resistor R and inductor L to the power supply VDD and ground Vss, generating current noise shown in waveforms Dυ and SS. be mixed into. Therefore, pseudo pulses that do not correspond to the inputs C1 and C2 of the output buffer are output to the outputs υ1 and L)2, causing malfunctions in the next stage. Therefore, it is necessary to limit the number of drives simultaneously, and to
There were also problems such as adding the number of grounding Vss pins.
本発明の目的は、電流ノイズの影響を受けない出力バッ
ファ回路方式を提供することにある。An object of the present invention is to provide an output buffer circuit system that is not affected by current noise.
上記目的は、出力バッファの終段トランジスタをＮ形Ｍ
Ｏ８）ランジメタ２個によるプッシュプル構成とし、電
源ＶＤＤ側のＮ形ＭＯＳトランジスタはソースフナロワ
動作させるので、このゲート駆動電圧が電流ノイズの影
響を受けない様にするため終段トランジスタとは別電源
とすることと、接地側の電流ノイズの影響を受けない様
にするため。For the above purpose, the final stage transistor of the output buffer is N type
O8) A push-pull configuration is used with two range metals, and the N-type MOS transistor on the power supply VDD side operates as a source-to-lower, so in order to prevent this gate drive voltage from being affected by current noise, a separate power supply is used from the final stage transistor. Also, to avoid being affected by current noise on the ground side.
同時駆動以外のその他の出力パルス信号の極性は通常時
ハイレベル、信号時ローレベルとし、かつ信号時の時間
位相はバス信号等の同時駆動信号とは離すことにより達
成される。This is achieved by setting the polarity of the output pulse signals other than the simultaneous drive to be high level during normal operation and low level during signal operation, and to separate the time phase during signal operation from the simultaneous drive signal such as a bus signal.
〔作用〕
出カバ９７丁のバヅファトランジスタを２個のＮ形ＭＯ
Ｓトランジスタでプツシニブル構成することにより、電
源ＶＤＤ側のＮ形ＭＯＳトランジスタはソースフナロワ
動作を行う。オン時の出力ハイレベルは上記トランジス
タのゲート電圧により決定されるので、同時駆動による
電源ｖＤＤの電流ノイズを出さない様、ゲートを駆動す
る前段回路のハイレベルは前記電源とは別な電流ノイズ
のない電源ＶＤりより作ることにより、出力バッファの
ハイレベルは電流ノイズが発生しない。一方ローレベル
は接地Ｖｓｓが出力そのものであるため、さげられない
ため、ノイズによる誤動作を招くパルス信号は全て１通
常時ハイレベルにし、信号時ローレベルとし、この信号
時の位相は、同時駆動たよる電流ノイズと重ならない様
に動作させることにより、電流ノイズの悪影響を全て排
除することが出来る。[Function] 97 out-covered buffer transistors are connected to two N-type MO
By configuring the S transistor in a push-nable configuration, the N-type MOS transistor on the power supply VDD side performs a source-funnel-lower operation. Since the output high level when turned on is determined by the gate voltage of the above transistor, the high level of the front stage circuit that drives the gate is determined by the current noise separate from the power supply so as not to generate current noise of the power supply vDD due to simultaneous driving. By making the output buffer higher than the power supply VD, current noise does not occur at the high level of the output buffer. On the other hand, the low level cannot be lowered because the ground Vss is the output itself, so all pulse signals that cause malfunction due to noise are set to 1 high level during normal operation and low level during signal operation. By operating in such a way that it does not overlap with current noise, it is possible to eliminate all the negative effects of current noise.
［実施例］
以下１本発明の一実施例を第１図により説明する。第１
図は半導体周辺部と各部の波形を一諸に示す。半導体周
辺部１に出カバ９ファ回路を多数個配置し、各出カバリ
ファは、半導体内部よりインバータ５を介してＮ形出カ
バー／７アトランジスタ３のゲートへ、さらにインバー
タ４を介してＮ形出力バッファトランジスタ２のゲート
へ接続する。２つの出力バッファトランジスタを直列接
続し、プツシニブル構成とし、ソースドレイン接続点を
出力とする。出力バッファトランジスタ２のドレインは
電源ＶＤＤ２ Ｋ接続し、−男前段のインバータ４の給
電は電源ＶＤＩＮより行う。多数のバス入力Ａ１−Ａｎ
Ｋ同じ波形が入力され、出力８１〜Ｂ３が同時駆動す
ると、電源Ｖｌ）Ｄ２及びＶｓｓｌｃは、電源共通イン
ピーダンス抵抗Ｒ及びインダクタンスＬＫより、電流ノ
イズが半導体内部の電源ＤＤ２及びＳＳｋ発生するが、
インバータ４の電源であるＤＤｌのノイズは極めて小さ
い。従り【コントロール用のパルス信号Ｃ１及びＣ２を
通常ハイレベルに−ｊると、バスの同時駆動により電源
電圧Ｌ）Ｄ２ Ｋノイズが生じても、トランジスタ２の
ゲート電圧は電源ＩＪＬ）１より供給するため、出力Ｄ
１及び１）２Ｊ＜はノイズが発生しない。さらにコント
ロール信号Ｃ１及びＣ２がローパルスとなる時間位相が
、バスの同時切換と重ならない様にすることにより、ロ
ーパルス時においても、接地ＳＳのノイズを出力しない
ので、出力Ｄ１及びＤ２は全ての電流ノイズを出さない
［発明の効果］
本発明によれば、バス信号等の同時切換時において、そ
の他の出力信号に電流ノイズを発生するのを抑止可能と
なるので、半導体論理回路の出力ビンの同時駆動本数の
制限、及び配置の制限を緩和することが出来る。従って
電源ピン数及び接地ピン数を少くする事及び電源給電イ
ンピーダンスの影響が小さくなるため、キップサイズの
縮小化やパッケージの低価格化が容易になる効果がある[Example] An example of the present invention will be described below with reference to FIG. 1st
The figure shows the peripheral part of the semiconductor and the waveforms of each part. A large number of output cover 9-fa circuits are arranged in the semiconductor peripheral area 1, and each output cover circuit is connected from inside the semiconductor to the gate of the N-type output cover/7-a transistor 3 via the inverter 5, and further to the gate of the N-type output cover/7a transistor 3 via the inverter 4. Connected to the gate of output buffer transistor 2. Two output buffer transistors are connected in series to form a push-nable configuration, and the source-drain connection point is used as an output. The drain of the output buffer transistor 2 is connected to the power supply VDD2K, and power is supplied to the inverter 4 at the front stage from the power supply VDIN. Multiple bus inputs A1-An
When the same waveform is input and the outputs 81 to B3 are driven simultaneously, the power supplies Vl)D2 and Vsslc generate current noise from the power supply common impedance resistor R and inductance LK inside the semiconductor power supplies DD2 and SSk,
The noise of DDl, which is the power source of the inverter 4, is extremely small. Therefore, [when the control pulse signals C1 and C2 are normally set to high level, the gate voltage of transistor 2 is supplied from the power supply IJL)1 even if power supply voltage L)D2K noise occurs due to the simultaneous driving of the buses. Therefore, the output D
1 and 1) No noise occurs when 2J<. Furthermore, by making sure that the time phase when the control signals C1 and C2 become low pulses does not overlap with the simultaneous switching of the buses, ground SS noise is not output even during low pulses, so outputs D1 and D2 are free from all current noise. [Effects of the Invention] According to the present invention, it is possible to suppress the generation of current noise in other output signals when simultaneously switching bus signals, etc. Restrictions on the number and arrangement can be relaxed. Therefore, by reducing the number of power supply pins and ground pins, and by reducing the influence of power supply impedance, it becomes easier to reduce the chip size and lower the price of the package.
【図面の簡単な説明】
第１図は本発明の一実施例の半導体周辺部の出力バッフ
ァ回路方式と各部電圧波形を示す図、第２図は従来技術
による半導体周辺部の出力バッファ回路と各部電圧波形
を示す図である。
１・・・半導体周辺部。
２・・・出力バッファトランジスタ。
６・・・出力バリフチトランジスタ。
４・・・インノく一タ
５・・・インバータ。
第 １ 図
第 ２ 図[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing the output buffer circuit system and voltage waveforms of each part in the semiconductor peripheral part according to an embodiment of the present invention, and FIG. 2 is a diagram showing the output buffer circuit of the semiconductor peripheral part and each part according to the prior art FIG. 3 is a diagram showing voltage waveforms. 1...Semiconductor peripheral area. 2...Output buffer transistor. 6...Output variable width transistor. 4... Inno Kuichita 5... Inverter. Figure 1 Figure 2
Claims (1)
Ｄ＿２と接地Ｖ＿Ｓ＿Ｓの間に、第１のＮ形ＭＯＳトラ
ンジスタと第２のＮ形ＭＯＳトランジスタを直列に接続
し、前記第１トランジスタのソースをＶ＿Ｓ＿Ｓに、第
２トランジスタのドレインをＶ＿Ｄ＿Ｄ＿２に接続し、
プッシュプル構成の出力バッファ回路とし、前記出力バ
ッファの第２トランジスタのゲートに接続するＣＭＯＳ
駆動回路の電源を、第１の電源Ｖ＿Ｄ＿Ｄ＿１に接続し
、同時駆動以外の出力を通常時ハイレベルで使用し、信
号時のみローレベルとし、かつ前記電流切換ノイズと異
なる時間位相で動作させることを特徴とする出力バッフ
ァ回路方式。1. First power supply V_D_D_1 and second power supply V_D_
A first N-type MOS transistor and a second N-type MOS transistor are connected in series between D_2 and ground V_S_S, the source of the first transistor is connected to V_S_S, the drain of the second transistor is connected to V_D_D_2,
A CMOS having a push-pull configuration as an output buffer circuit and connected to the gate of the second transistor of the output buffer.
The power supply of the drive circuit is connected to the first power supply V_D_D_1, the outputs other than those for simultaneous driving are used at a high level during normal times, are set at a low level only when a signal is being used, and the outputs are operated at a time phase different from the current switching noise. Features an output buffer circuit system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61052432A JPS62210725A (en) | 1986-03-12 | 1986-03-12 | Output buffer circuit system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61052432A JPS62210725A (en) | 1986-03-12 | 1986-03-12 | Output buffer circuit system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62210725A true JPS62210725A (en) | 1987-09-16 |
| JPH0531964B2 JPH0531964B2 (en) | 1993-05-13 |
Family
ID=12914592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61052432A Granted JPS62210725A (en) | 1986-03-12 | 1986-03-12 | Output buffer circuit system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62210725A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63234623A (en) * | 1987-03-23 | 1988-09-29 | Toshiba Corp | Semiconductor integrated circuit |
| JPS6441314A (en) * | 1987-08-06 | 1989-02-13 | Nec Corp | Semiconductor integrated circuit |
| EP0317476A2 (en) * | 1987-11-17 | 1989-05-24 | International Business Machines Corporation | Noise control in an integrated circuit chip |
| JP2000206493A (en) * | 1999-01-13 | 2000-07-28 | Hitachi Ltd | Liquid crystal display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS572213A (en) * | 1980-06-05 | 1982-01-07 | Kanebo Keshohin Kk | Cosmetic |
-
1986
- 1986-03-12 JP JP61052432A patent/JPS62210725A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS572213A (en) * | 1980-06-05 | 1982-01-07 | Kanebo Keshohin Kk | Cosmetic |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63234623A (en) * | 1987-03-23 | 1988-09-29 | Toshiba Corp | Semiconductor integrated circuit |
| JPH0473893B2 (en) * | 1987-03-23 | 1992-11-24 | ||
| JPS6441314A (en) * | 1987-08-06 | 1989-02-13 | Nec Corp | Semiconductor integrated circuit |
| EP0317476A2 (en) * | 1987-11-17 | 1989-05-24 | International Business Machines Corporation | Noise control in an integrated circuit chip |
| JP2000206493A (en) * | 1999-01-13 | 2000-07-28 | Hitachi Ltd | Liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0531964B2 (en) | 1993-05-13 |
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