JPS6218898U - - Google Patents

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の構成ブロツク図、第２図は本
考案の構成による主要信号のタイミング図、第３
図、第４図は本考案で用いる遅延回路例の回路図
、第５図は従来同期式マスクＲＯＭのブロツク図
、第６図は同期式デコード回路の例。 Ａ_ｉ……入力アドレス信号、ａ_ｉ，_ｉ……ア
ドレス入力回路の出力信号、……外部入力動
作開始信号、ＤＳ，……出力ラツチ出力信号
、ＤＬ……出力ラツチ信号、……アドレス入
力回路待期設定信号、_ｐ……デコード回路等プ
リチヤージ信号、Ｏ_ｉ……出力信号、Ｔ_１……Ｐ
型トランジスタ、Ｔ_２……Ｎ型トランジスタ。 Figure 1 is a block diagram of the configuration of the present invention, Figure 2 is a timing diagram of main signals according to the configuration of the present invention, and Figure 3 is a block diagram of the configuration of the present invention.
4 is a circuit diagram of an example of a delay circuit used in the present invention, FIG. 5 is a block diagram of a conventional synchronous mask ROM, and FIG. 6 is an example of a synchronous decoding circuit. A _i ...Input address signal, _ai , _i ...Output signal of address input circuit,...External input operation start signal, DS,...Output latch output signal, DL...Output latch signal,...Address input circuit Standby setting signal, _p ...precharge signal for decoding circuit, etc., _Oi ...output signal, _T1 ...P
type transistor, _T2 ...N type transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同期式デコード回路と、センスアンプ、出力デ
ータラツチ回路とを含む同期式マスクＲＯＭにお
いて、前記出力データラツチ回路のデータセツト
完了を検出し、少なくとも前記同期式デコード回
路のプリチヤージを開始する信号と、該デコード
回路に入力されるアドレス信号を待期状態にする
アドレス制御信号とを出力するデータセツト検出
回路を有し、前記プリチヤージ開始信号を前記ア
ドレス制御信号より、前記アドレス信号が待期状
態になる時間以上遅らせて出力させることを特徴
とする同期式ＲＯＭ。 In a synchronous mask ROM including a synchronous decoding circuit, a sense amplifier, and an output data latch circuit, a signal for detecting completion of data setting of the output data latch circuit and starting precharging of at least the synchronous decoding circuit, and the decoding circuit a data set detection circuit that outputs an address control signal that puts an address signal input to a standby state into a standby state, and delays the precharge start signal from the address control signal by at least the time when the address signal becomes a standby state. A synchronous ROM characterized in that it outputs data simultaneously.