JPS62159914A - Ecl compatible output circuit - Google Patents
Ecl compatible output circuitInfo
- Publication number
- JPS62159914A JPS62159914A JP61002451A JP245186A JPS62159914A JP S62159914 A JPS62159914 A JP S62159914A JP 61002451 A JP61002451 A JP 61002451A JP 245186 A JP245186 A JP 245186A JP S62159914 A JPS62159914 A JP S62159914A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- voltage
- output
- current
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic
- H03K19/09436—Source coupled field-effect logic [SCFL]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]
- H03K19/018542—Interface arrangements of Schottky barrier type [MESFET] with at least one differential stage
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明なＧａＡｓ ＬＳＩ等に用いられるＥＣＬ コン
パチブル出力回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an ECL compatible output circuit used in GaAs LSI and the like.
（従来の技術）
一般ＪこＤＣＦＬ、ＢＦＬなどを用いたＧａＡｓＬ８Ｉ
においては、その内部論理レベルは電源電圧によって一
部に定められてしまう。(Prior art) GaAsL8I using general JCO DCFL, BFL, etc.
, its internal logic level is determined in part by the power supply voltage.
このため、その出力レベルを既存のＥＣＬなどとコンパ
チブルとする為に出力振幅を電源電圧と無関係に設定す
ることのできる５ＣＦＬが用いられることが多い。Therefore, in order to make the output level compatible with existing ECLs, etc., a 5CFL whose output amplitude can be set independently of the power supply voltage is often used.
このような５ＣＦＬの具体例としては例えば昭和５８年
四学全連合大会３〜１５０頁１’−ＧａＡｓティジタル
集積回路」（発表者、東坂浅光）に記載のものが知られ
ている。As a specific example of such a 5CFL, the one described in "GaAs Digital Integrated Circuit" (presenter: Asamitsu Higashizaka), page 3-150 of the 1981 Four Academic Union Conference, is known.
第２図に従来技術によるＢＣＬコンパチブル出力回路の
一例を示す。FIG. 2 shows an example of a BCL compatible output circuit according to the prior art.
第２図において負荷抵抗２００．２０１を流れる電流を
それぞれＬ−Ｉ−とするとマへの２つの電流の和は常に
ＦＥＴ２０２を流れる電流ＩＣに等しい。In FIG. 2, if the currents flowing through the load resistors 200 and 201 are L-I-, the sum of the two currents flowing through the FET 202 is always equal to the current IC flowing through the FET 202.
ここでＦＥＴ２０４のゲート端子２０５にＦＥＴ２０６
のゲート端子に接続された基準電圧電源２０７の電圧Ｖ
ｒａ ｆ以上の電圧が加えられるとｌｉ’ＥＴ２０２を
流れる電流ＩＣはナベてＰＢＴ ２０４−Ｉ−流れ出力
端子２０８にはハイレベルＶ０菖が出力される。Here, FET206 is connected to the gate terminal 205 of FET204.
The voltage V of the reference voltage power supply 207 connected to the gate terminal of
When a voltage higher than ra f is applied, the current IC flowing through the li'ET 202 becomes flat and a high level V0 signal is output to the PBT 204-I-flow output terminal 208.
この為第２図に示した出力回路の／鴬イレベルｖＯ１１
は抵抗２０３の抵抗値Ｒによって次式の如く定められる
。For this reason, the output circuit shown in Fig. 2 has a level vO11 of
is determined by the resistance value R of the resistor 203 as shown in the following equation.
Ｖ ＝−ＲＩ ・・・・・・・・・ （１
）ｏｎ （
一方、ゲート端子２０５にＶｒｅｆ以下の電圧が加えら
れた場合にはＦＩＴ ２０２−Ｆ流れる電流ＩＣはすべ
てＰＥＴ ２０６を流れこの時の出力電圧ｖＯＬは負荷
抵抗２００の抵抗値ＲＬによって次式の如く与えられる
。V = -RI ・・・・・・・・・ (1
) on (On the other hand, when a voltage lower than Vref is applied to the gate terminal 205, all the current IC flowing through the FIT 202-F flows through the PET 206, and the output voltage vOL at this time is calculated by the following formula based on the resistance value RL of the load resistor 200. It is given as follows.
Ｖｏｔ、＝−（Ｒ＋Ｒｔ、） Ｉ（・・・−”・・
（２）（発明が解決しようとする問題点）
第２図においてＰＥＴ ２０２の伝達コンダクタンス並
びに閾値電圧をそれぞれβ、■！とするとＰＥＴ ２０
２を流れる電流ＩＣは次式によって得ら□
れるシ
雪
ｌｃ；β・Ｖ、 ・・・・・・・・・ （３）
上式を（１）、（２）式に代入すると
■。ヨ＝Ｊｌ、・β・Ｖ、Ｆ ・・・・・・・
・・ （４）ＹＯＬ ”−Ｇ＋ＲＬ）β■Ｉ ・・・
・・・・・・（５）一般−ＣＧａＡｓ Ｍｇ２ ＦＦｆ
Ｔは現状ではＶ、のバラツキが大き、〈このため第（４
）、 （５）式から明らかな、ようｌこ第２図に示した
出力回路はＶｏｉ＋ｅＶｏＬともに■、のバラツキに対
する依存度が大きい。Vot, =-(R+Rt,) I(...-"...
(2) (Problems to be Solved by the Invention) In FIG. 2, the transfer conductance and threshold voltage of the PET 202 are β and ■!, respectively. Then PET 20
The current IC flowing through 2 is obtained by the following formula: lc; β・V, ...... (3)
Substituting the above equation into equations (1) and (2) yields ■. Yo=Jl,・β・V,F・・・・・・・
・・・ (4)YOL”-G+RL)β■I ・・・
・・・・・・(5) General-CGaAs Mg2 FFf
Currently, T has large variations in V,
), It is clear from equation (5) that the output circuit shown in FIG. 2 is highly dependent on the variation in both Voi+eVoL.
第３図（ａ）は第２図に示した出力回路のＦＥＴ２０２
に代わシ抵抗値Ｒ，を有する抵抗３００８用いた例を示
す。Figure 3(a) shows the FET 202 of the output circuit shown in Figure 2.
An example will be shown in which a resistor 3008 having a resistance value R is used instead.
図中、第２図と同一番号を付したものは第２図と同一の
構成要素を示している。In the figure, the same numbers as in FIG. 2 indicate the same components as in FIG. 2.
なお、第３図（ａ）におかては説明を簡略にする為に第
２図に示したレベルシフト用抵抗２０３は省略されてい
る。Note that in FIG. 3(a), the level shift resistor 203 shown in FIG. 2 is omitted to simplify the explanation.
第３図中）は第３図（ａ）に示した出力回路の入出力特
性を示す。3) shows the input/output characteristics of the output circuit shown in FIG. 3(a).
図中、３０１および３０２はそれぞれ第３図−）に示し
た出力端子３０３および３０４の出力電圧を示す。In the figure, 301 and 302 indicate the output voltages of the output terminals 303 and 304 shown in FIG. 3-), respectively.
第３図（ａ）において入力端子２０５に加えられる電圧
がＶｒｅｆに比して十分率さな領域３０５＃こおいて社
Ｆｇ’ｌ’ ２０４はカットオフ状態、ＦＢ’ｌ’ ２
０６は飽和状態にあム出入端子３０４の電圧Ｖ。Ｌはは
は次式によって表わすことができる。In FIG. 3(a), in a region 305# where the voltage applied to the input terminal 205 is sufficiently high compared to Vref, the company Fg'l' 204 is in a cut-off state, and FB'l' 2
06 is the voltage V of the AM input/output terminal 304 in the saturated state. L can be expressed by the following equation.
ＶＯＬ＝ （Ｖｒｅｆ ’ｓｓ ）・（ＲＬ／Ｒ８）
・・・−４６）また入力端子２０５に加えられる電圧
がＶｒｅｆ の近傍の領域３０６においてはＰＦＩＴ
２０４．２０６とも番こ飽和状態となる。VOL= (Vref'ss)・(RL/R8)
...-46) Also, in the region 306 where the voltage applied to the input terminal 205 is Vref, the PFIT
Both 204 and 206 are saturated.
更に入力端子２０５に加えられる“電圧力Ｖｒｅｆに対
して大きな領域３０７において祉ＦＦ１Ｔ ２０６は力
、トオフ状態、Ｆｌｉ！Ｔ ２０４は飽和状態となりＰ
ＥＴ ２０４を流れる電流１．は入力端子２０５に（５
）ン＼
加えられる電圧Ｖｉｎによって次式の如く表すことがで
きる。Furthermore, in a region 307 that is large with respect to the voltage force Vref applied to the input terminal 205, the FF1T 206 is in a power-off state, and the Fli!T 204 is in a saturated state, P
Current flowing through ET 2041. is input to the input terminal 205 (5
)n\ It can be expressed as the following equation by the applied voltage Vin.
Ｉｍ ” （Ｖ ｔｎ −Ｍｇ１４ ） ／ ＩＲｓ
・・・・・・ （７）したがって、第３図（ａ）−
こ示す出力回路ｌこおいては第３図（ｂ）の３０１＃こ
示す如＜Ｖｉｎの増加にともなって出力端子２０５の電
圧が下降し電流ｌ諺と！−の和ｌｃは第２図に示した出
力回路と異なり常に一定の値に保つことはできない。
。Im” (Vtn-Mg14)/IRs
...... (7) Therefore, Figure 3 (a) -
In this output circuit 1, as shown in 301# in FIG. 3(b), as Vin increases, the voltage at the output terminal 205 decreases and the current decreases. Unlike the output circuit shown in FIG. 2, the sum lc of - cannot always be kept at a constant value.
.
仁の為第２図に示した抵抗２０３によるレベルシフトを
第３図（ａ）に示した出力回路に適用すると出力端子３
０４のハイレベルｖｏＭは次式の如く表わされ入力電圧
Ｖｉｎに依存する値となる。For convenience, if the level shift by the resistor 203 shown in FIG. 2 is applied to the output circuit shown in FIG. 3(a), the output terminal 3
The high level voM of 04 is expressed as the following equation and has a value that depends on the input voltage Vin.
■。ｍ ”−（■ｉ、ｎ−■ｓｓ ）゛・（ｉ／Ｒａ）
・・・・・・（８）本発明の目的はハイレベル出力電圧
Ｖ。ｕｔ が入力電圧Ｗｉｎ に依存せず、ｔたＶテ
のバラツキに対する出力電圧への影響の少ないＥＣＬ：
ｙンパチプル出力回路を提供することにある。■. m ”-(■i, n-■ss)゛・(i/Ra)
(8) The object of the present invention is high level output voltage V. ECL in which ut does not depend on the input voltage Win and the output voltage is less affected by variations in t:
The object of the present invention is to provide a multiple output circuit.
脈１．・
（問題を解決するための手段）
本発明によればゲート端子に入力信号を加えられドレイ
ン端子を第１の電源に接続された第１のＦＥＴと、ゲー
ト端子に基準電圧を加えられ前記第１のＦＥＴのソース
端子にソース端子を接続された第２のＦＥＴと、前記第
２のＦＥＴのドレイン端子と、前記第１の電源との間に
設けられた負荷抵抗と、前記第２のＦＥ’Ｊ’のソース
端子と第２の電源との間に設けられたソース抵抗とから
構成される５ＣＦＬ回路において、前記負荷抵抗の一部
もしくは全部に常時一定の電流を流す手段を更に付加し
たことを特徴とするＥＣＬコンパチブル出力回路が得ら
れる。Pulse 1. - (Means for solving the problem) According to the present invention, a first FET is provided with an input signal applied to its gate terminal and whose drain terminal is connected to a first power supply, and a first FET with a reference voltage applied to its gate terminal. a second FET whose source terminal is connected to the source terminal of the first FET; a load resistor provided between the drain terminal of the second FET and the first power supply; In a 5CFL circuit consisting of a source resistor provided between the source terminal of 'J' and a second power supply, a means is further added to cause a constant current to flow through part or all of the load resistor. An ECL compatible output circuit is obtained.
（作用）
本発明はＦＥＴを用いた定電流源にかわってソース抵抗
を用い、かつゲート端子に基準電圧が加えられたＰＥＴ
の負荷抵抗に常時一定の電流を流すことによって出力電
圧のレベルシフトを行なっておルこれによって入力電圧
Ｖｉｎや閾値電圧■、のバラツキに対する出力電圧の変
動を軽減しようとするものである。(Function) The present invention uses a source resistor instead of a constant current source using an FET, and a PET with a reference voltage applied to the gate terminal.
The level shift of the output voltage is carried out by constantly flowing a constant current through the load resistance of the circuit, thereby attempting to reduce fluctuations in the output voltage due to variations in the input voltage Vin and the threshold voltage (2).
（実施例） 次にこの発明の実施例を図面を参照して説明する。(Example) Next, embodiments of the invention will be described with reference to the drawings.
第１図は本発明の実施例を示す。FIG. 1 shows an embodiment of the invention.
図中、第２図、第３図と同一番号を付したものは第２図
、第３図と同一の構成要素を示す。In the drawings, the same numbers as in FIGS. 2 and 3 indicate the same components as in FIGS. 2 and 3.
第１図において入力端子２０５に基準電圧ｖｒｅｆ以上
の電圧が加えられるとＦＥＴ ２０６Ｆｉカツトオフ状
態となりＦＥＴ２０４のみに入力電圧■ｉｏによって次
式の如く定まる電流１．が流れる。In FIG. 1, when a voltage higher than the reference voltage vref is applied to the input terminal 205, the FET 206Fi is cut off, and the current 1. flows.
Ｌ＝（Ｖｉｎ−Ｖ’ｓｓ）／Ｒｅ ・−川・・（９
）このとき負荷抵抗２００にはＦｇＴｌｏｏによって定
まる一定の電流■・が流れておハこれにより出力端子２
０８には次式で与えられるハイレベル出力電圧Ｖ。アが
表われる。L=(Vin-V'ss)/Re ・-river...(9
) At this time, a constant current determined by FgTloo flows through the load resistor 200, which causes the output terminal 2 to
08 is a high level output voltage V given by the following formula. A appears.
Ｖ ｏｎ ＝ Ｒｔ、 Ｉ−””−” （＋（また
場合には負荷抵抗２００にはｌ”ＥＴｌｏｏを流れる電
流１．とソース抵抗３００を流れる電流ｌｃ の和が流
れるローレベル出力電圧Ｖ。Ｌは次式によって与えられ
る。V on = Rt, I-""-" (+(In this case, the load resistor 200 has a low-level output voltage V. L where the sum of the current 1. flowing through l"ETloo and the current lc flowing through the source resistor 300 flows. is given by the following equation.
ＶｏＬ＝ −（ｌｏ ＋Ｉｃ） １（１Ｈ・＝ ａυ
ここでＰＵＴｌｏｏの伝達コンダクタンス、閾値をそれ
ぞれβ、■、とすると電流値ｌ。は次式で表れずことが
できる。VoL= −(lo +Ic) 1(1H・= aυ
Here, if the transfer conductance and threshold value of PUTloo are β and ■, respectively, the current value is l. can be expressed in the following equation.
冨
ＩＯ＝β■Ｔ ・・・・・・・・・・・ ０４
さらにＦＥＴ２０４を流れる電流１ｃＦｉ基準電圧Ｖｒ
ｅｆを用いて、次のように表わせる。Fuji IO=β■T ・・・・・・・・・・・・ 04
Further, current 1cFi flowing through FET 204 and reference voltage Vr
Using ef, it can be expressed as follows.
Ｉ ｃ ＝ （ｖｒｅｆ −Ｖｓｓ ） ／ ｌ（ｓ
’・・・・・・・・ 峙ここで式＜ＩＬ （１３１を
式ａａ、Ｕに代入するとｖｏｓ −−ＲＬ７９ｖ、、
ｚ ・・・・・・・・・・・・ （Ｊ＜式ａａ、
ａｓと式（４）、 ＋５３とを比較すれば本発明ｔこよ
る出力回路は第２図に示した従来町による出力回路に対
してＶ、ｒのバラツキ１こ対する出力レベルの変動が少
ないことがわかる。Ic = (vref −Vss) / l(s
'・・・・・・・・・ where the expression <IL (Substituting 131 into the expression aa, U, vos --RL79v,,
z ・・・・・・・・・・・・ (J<expression aa,
Comparing as, equation (4), and +53, it can be seen that the output circuit according to the present invention exhibits less fluctuation in output level relative to the variation in V and r compared to the conventional output circuit shown in Fig. 2. I understand.
更にまた本発明による出力回路はｌＦＥＴ２０４を流れ
る′電流１．とけ無関係にハイレベル出力Ｖ。Furthermore, the output circuit according to the present invention has a current 1. High level output V regardless of melting.
を足めることができ入力電圧ｖ１ｎの影響を受けること
がなり０
（発明の効果）
以上述べたように本発明によればＶｌ、のバラツキや入
力電圧による国力電圧レベルの変動の少ない１（ＣＬコ
ンパチブル出力回路が得られる。(Effects of the Invention) As described above, according to the present invention, it is possible to add 1( A CL compatible output circuit is obtained.
第１図は本発明の実施例を示す図、第２図は従来技術に
よるＥＣＬコンパチブル出力回路の第１の具体例を示す
因、第３図は従来技術によるＥＣＬコンパチブル出力回
路の第２の具体例を示す図である。図において２０４．
２０６および１００はノーマリ７１ 図
１００，２０４．２０６： ／−７１，Ｉｔン型ＭＥＮ
ＦＥＴ７１−２ 図
ＳＳFIG. 1 shows an embodiment of the present invention, FIG. 2 shows a first specific example of an ECL compatible output circuit according to the prior art, and FIG. 3 shows a second specific example of an ECL compatible output circuit according to the prior art. It is a figure which shows an example. In the figure, 204.
206 and 100 are normal 71 Figure 100, 204.206: /-71, It-type MEN
FET71-2 Figure SS
Claims (1)
電源に接続された第１のＦＥＴと、ゲート端子に基準電
圧を加えられ前記第１のＦＥＴのソース端子にソース端
子を接続された第２のＦＥＴと、前記第２のＦＥＴのド
レイン端子と、前記第１の電源との間に設けられた負荷
抵抗と、前記第２のＦＥＴのソース端子と第２の電源と
の間に設けられたソース抵抗とから構成されるＳＣＦＬ
回路において、前記負荷抵抗の一部もしくは全部に常時
一定の電流を流す手段を更に付加したことを特徴とする
ＥＣＬコンパチブル出力回路。a first FET to which an input signal is applied to the gate terminal and whose drain terminal is connected to a first power supply; and a second FET to which a reference voltage is applied to the gate terminal and whose source terminal is connected to the source terminal of the first FET. FET, a load resistor provided between the drain terminal of the second FET and the first power source, and a load resistor provided between the source terminal of the second FET and the second power source. SCFL consisting of source resistance
An ECL compatible output circuit characterized in that the circuit further includes means for constantly flowing a constant current through part or all of the load resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61002451A JPS62159914A (en) | 1986-01-09 | 1986-01-09 | Ecl compatible output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61002451A JPS62159914A (en) | 1986-01-09 | 1986-01-09 | Ecl compatible output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62159914A true JPS62159914A (en) | 1987-07-15 |
Family
ID=11529645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61002451A Pending JPS62159914A (en) | 1986-01-09 | 1986-01-09 | Ecl compatible output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62159914A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983853A (en) * | 2012-11-26 | 2013-03-20 | 电子科技大学 | Analog squaring circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5911032A (en) * | 1982-07-12 | 1984-01-20 | Hitachi Ltd | Signal level variation compensating circuit of logical circuit |
| JPS6068645A (en) * | 1983-09-26 | 1985-04-19 | Toshiba Corp | Logic circuit |
-
1986
- 1986-01-09 JP JP61002451A patent/JPS62159914A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5911032A (en) * | 1982-07-12 | 1984-01-20 | Hitachi Ltd | Signal level variation compensating circuit of logical circuit |
| JPS6068645A (en) * | 1983-09-26 | 1985-04-19 | Toshiba Corp | Logic circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983853A (en) * | 2012-11-26 | 2013-03-20 | 电子科技大学 | Analog squaring circuit |
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