JPS5811768B2 - Comparator circuit - Google Patents
Comparator circuitInfo
- Publication number
- JPS5811768B2 JPS5811768B2 JP53025644A JP2564478A JPS5811768B2 JP S5811768 B2 JPS5811768 B2 JP S5811768B2 JP 53025644 A JP53025644 A JP 53025644A JP 2564478 A JP2564478 A JP 2564478A JP S5811768 B2 JPS5811768 B2 JP S5811768B2
- Authority
- JP
- Japan
- Prior art keywords
- mos
- comparator circuit
- input
- output
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
この発明は、コンプリメンタリ・ＭＯＳ−ＩＣ〔以下Ｃ
−ＭＯ８ＩＣと略称する〕を用いたコンパレータ回路に
関する。[Detailed Description of the Invention] This invention relates to a complementary MOS-IC [hereinafter referred to as C
The present invention relates to a comparator circuit using a MO8IC.
近年安価なＣ−ＭＯＳ ＩＣが市場に出まわっている。In recent years, inexpensive C-MOS ICs have appeared on the market.
そこで、この発明は、この安価なＣ−ＭＯＳ ＩＳを用
いることによりコストの低いコンパレータ回路を提供す
るものである。Therefore, the present invention provides a low-cost comparator circuit by using this inexpensive C-MOS IS.
通常のＣ−ＭＯＳインバータの特性は、第１図の入・出
力特性に示すように電源電圧ＶＤＤの１／２の点が遷移
電圧ＶＴＲとなっており、このＣ−ＭＯＳインバータを
コンパレータとして用いた場合、コンパレータは上記遷
移電圧ＶＴＲを閾値として動作する。The characteristics of a normal C-MOS inverter are that, as shown in the input/output characteristics in Figure 1, the point at 1/2 of the power supply voltage VDD is a transition voltage VTR, and this C-MOS inverter is used as a comparator. In this case, the comparator operates using the transition voltage VTR as a threshold value.
ところがこの遷移電圧ＶＴＲには、製造上のばらつきが
あり、通常電源電圧ＶＤＤの３３から６７％の範囲内に
ある。However, this transition voltage VTR has manufacturing variations, and is normally within a range of 33 to 67% of the power supply voltage VDD.
したがってＣ−ＭＯＳインバータの入力に直列抵抗の分
割比による固定バイアスを用いた場合には、遷移電圧Ｖ
ＴＲの変化がコンパレータを作動させる閾値に直接影響
するという問題が生じる。Therefore, when a fixed bias based on the division ratio of series resistors is used at the input of a C-MOS inverter, the transition voltage V
A problem arises in that changes in TR directly affect the threshold that activates the comparator.
ところで、ＩＣの同一チップ内に存在するＣ−ＭＯＳイ
ンバータ相互の間では、電源電圧ＶＤＤに対して遷移電
圧ＶＴＲが同一となる特性がある。By the way, there is a characteristic that the transition voltage VTR is the same with respect to the power supply voltage VDD between the C-MOS inverters existing in the same chip of an IC.
そこで、この発明のコンパレータ回路では、この特性を
利用して上記問題を解決し、コストの低いコンパレータ
回路を実現したものであって、以下図面に基づいて詳細
に説明すると、第２図は、この発明のコンパレータ回路
を示す回路図であって、入力信号はコンデンサＣを介し
て第１のＣ−ＭＯＳインバータＩＮ１へ入力され、この
第１のＣ−ＭＯＳインバータの出力側から出力信号が取
り出されている。Therefore, the comparator circuit of the present invention utilizes this characteristic to solve the above problem and realize a low-cost comparator circuit. It is a circuit diagram showing a comparator circuit of the invention, in which an input signal is input to a first C-MOS inverter IN1 via a capacitor C, and an output signal is taken out from the output side of this first C-MOS inverter. There is.
電源の一方の端子と第１のＣ−ＭＯＳインバータＩＮ１
の入力側との間には、第１、第２、第３の抵抗Ｒ１，Ｒ
２，Ｒ３からなる直列抵抗電路が接続されている。One terminal of the power supply and the first C-MOS inverter IN1
The first, second, and third resistors R1, R
A series resistance circuit consisting of R2 and R3 is connected.
次に第２のＣ−ＭＯＳインバータＩＮ２が、第１の抵抗
Ｒ１と第２の抵抗Ｒ２との接続点に入力側を、そして第
２の抵抗Ｒ２と第３の抵抗Ｒ３との接続点に出力側をそ
れぞれ接続されている。Next, the second C-MOS inverter IN2 outputs the input side to the connection point between the first resistor R1 and the second resistor R2, and the output side to the connection point between the second resistor R2 and the third resistor R3. The sides are connected to each other.
そして第１のＣ−ＭＯＳインバータＩＮ１と第２のＣ−
ＭＯＳインバータ■Ｎ２とは、同−ＩＣ内の２個のイン
バータを用いている。And the first C-MOS inverter IN1 and the second C-
The MOS inverter N2 uses two inverters in the same IC.
上記のように構成されたこの発明のコンパレータ回路に
おいて、第１図の入・出力特性図上曲線Ａで示すような
遷移電圧ＶＴＲが電源電圧ＶＤＤの５０％である標準特
性を有するＣ−ＭＯＳＩＣを用いた場合の無人力信号時
の第１のＣ−ＭＯＳインバータＩＮ１の入力側電位すな
わちバイアス電位は、第１図の入・出力特性図上におい
て、曲線Ａと、第１の抵抗Ｒ１の抵抗値と、第１、第２
の抵抗Ｒ１，Ｒ２の抵抗値の和の比Ｒ１／（Ｒ１＋Ｒ２
）＝ａ／ｂから決定される直線ｒとの交点Ｐ０の出力電
圧ｖｏ１となる。In the comparator circuit of the present invention configured as described above, a C-MOSIC having a standard characteristic in which the transition voltage VTR is 50% of the power supply voltage VDD as shown by curve A on the input/output characteristic diagram in FIG. In this case, the input side potential, that is, the bias potential of the first C-MOS inverter IN1 at the time of an unmanned signal is equal to the curve A and the resistance value of the first resistor R1 on the input/output characteristic diagram in FIG. and the first and second
The ratio of the sum of the resistance values of resistors R1 and R2 is R1/(R1+R2
) = output voltage vo1 at the intersection point P0 with the straight line r determined from a/b.
次に、上記各抵抗を固定してＣ−ＭＯＳ ＩＣを、第１
図の入・出力特性図上曲線Ｂで示すような遷移電圧ＶＴ
Ｒが電源電圧ＶＤＤの３３％である特性を有するＣ−Ｍ
ＯＳ ＩＣを用いた場合の第１のＣ−ＭＯＳインバータ
ＩＮ１の入力側電位は、第１図の入・出力特性図上にお
いて、交点ＰＬの出力電圧ＶＯ２となり、遷移電圧ＶＴ
Ｒの減少分にほぼ匹敵する量だけバイアス電位も変化す
る。Next, each of the above resistors is fixed and the C-MOS IC is connected to the first
Transition voltage VT as shown by curve B on the input/output characteristic diagram in the figure
C-M having the characteristic that R is 33% of the power supply voltage VDD
When an OS IC is used, the input side potential of the first C-MOS inverter IN1 becomes the output voltage VO2 at the intersection PL on the input/output characteristic diagram in FIG. 1, and the transition voltage VT
The bias potential also changes by an amount approximately equal to the decrease in R.
同様に、上記各抵抗を固定してＣ−ＭＯＳＩＣを曲線Ｃ
で示すような遷移電圧ＶＴＲが電源電圧ＶＤＤの６７％
である特性を有するＣ−ＭＯＳＩＣを用いた場合には、
入力側電位は、交点ＰＨの出力電圧ＶＯ３となって、や
はりバイアス電位は遷移電圧ＶＴＲの変化分に追従して
変化する。Similarly, with each of the above resistances fixed, the C-MOSIC is plotted by the curve C.
The transition voltage VTR as shown in is 67% of the power supply voltage VDD.
When using a C-MOSC with the following characteristics,
The input side potential becomes the output voltage VO3 at the intersection PH, and the bias potential also changes following the change in the transition voltage VTR.
このように、この発明のコンパレータ回路によると、標
準特性のＣ−ＭＯＳ ＩＣにおいて第１、第２の抵抗Ｒ
１，Ｒ２によってバイアス点を決定すると遷移電圧ＶＴ
Ｒの変化が自動的に補償されるので、コンパレータ回路
の閾値設定が容易に行なえ、さらに２個のインバータが
同−ＩＣ内にあれば、遷移電圧ＶＴＲの温度依存性をも
改善することができる。As described above, according to the comparator circuit of the present invention, in a C-MOS IC with standard characteristics, the first and second resistors R
When the bias point is determined by 1 and R2, the transition voltage VT
Since changes in R are automatically compensated, the threshold value of the comparator circuit can be easily set, and if two inverters are included in the same IC, the temperature dependence of the transition voltage VTR can also be improved. .
なお、上記２個のインバータ■Ｎ１．■Ｎ２は、特性が
ほぼ同じであれば同−ＩＣ内にある必要はなくまた、イ
ンバータはＮＡＮＤゲートなど他のＣ−ＭＯＳゲートで
もよく、さらにＲ１／Ｒ２が大である程改善されること
は明らかである。Note that the above two inverters ■N1. ■N2 does not need to be in the same IC as long as the characteristics are almost the same, and the inverter can be another C-MOS gate such as a NAND gate. Furthermore, the larger R1/R2 is, the better the improvement will be. it is obvious.
第１図は、この発明のコンパレータ回路に用いるＣ−Ｍ
ＯＳインバータの入出力特性図、第２図は、この発明の
コンパレータ回路を示す回路図である。
ＩＮｌ、ＩＮ２・・・・・・第１、第２のＣ−ＭＯＳゲ
ート（インバータ）、Ｒ１，Ｒ２，Ｒ３・・・・・・抵
抗。FIG. 1 shows a C-M used in the comparator circuit of the present invention.
FIG. 2, an input/output characteristic diagram of the OS inverter, is a circuit diagram showing a comparator circuit of the present invention. INl, IN2...first and second C-MOS gates (inverters), R1, R2, R3...resistance.
Claims (1)
Ｓゲートと、入力側と電源との間および入力側と出力側
との間にそれぞれ抵抗が接続されかつその出力側を抵抗
を介して上記第１のＣ−ＭＯＳゲートの入力側へ接続さ
れた第２のＣ−ＭＯＳゲートとよりなることを特徴とす
るコンパレータ回路。1 first C-MO that sets a threshold value as a comparator
A resistor was connected between the S gate, the input side and the power supply, and between the input side and the output side, and the output side was connected to the input side of the first C-MOS gate through the resistor. A comparator circuit comprising a second C-MOS gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53025644A JPS5811768B2 (en) | 1978-03-07 | 1978-03-07 | Comparator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53025644A JPS5811768B2 (en) | 1978-03-07 | 1978-03-07 | Comparator circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54118157A JPS54118157A (en) | 1979-09-13 |
| JPS5811768B2 true JPS5811768B2 (en) | 1983-03-04 |
Family
ID=12171532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53025644A Expired JPS5811768B2 (en) | 1978-03-07 | 1978-03-07 | Comparator circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5811768B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0437989B2 (en) * | 1984-02-02 | 1992-06-23 | Konishiroku Photo Ind |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60105320A (en) * | 1983-11-14 | 1985-06-10 | Nippon Telegr & Teleph Corp <Ntt> | Level converting circuit |
| WO2007116468A1 (en) * | 2006-03-31 | 2007-10-18 | Fujitsu Limited | Threshold value correcting circuit, integrated circuit with threshold value correcting function, and circuit board with threshold value correcting function |
-
1978
- 1978-03-07 JP JP53025644A patent/JPS5811768B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0437989B2 (en) * | 1984-02-02 | 1992-06-23 | Konishiroku Photo Ind |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54118157A (en) | 1979-09-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2741022B2 (en) | Power-on reset pulse generation circuit | |
| JPH0812986B2 (en) | Delay circuit | |
| JPS5811768B2 (en) | Comparator circuit | |
| JPS6346444B2 (en) | ||
| JPS6052380B2 (en) | Bipolar voltage detection circuit | |
| JPS591005B2 (en) | Schmidt trigger circuit | |
| KR900001813B1 (en) | Schmittrigger circuit | |
| JP3426594B2 (en) | Input buffer circuit | |
| JP2506524B2 (en) | Constant voltage circuit | |
| JPH0316648B2 (en) | ||
| JPS6027967Y2 (en) | voltage detection device | |
| JPS62254073A (en) | Cmos power-on detection circuit | |
| JP2927112B2 (en) | Test circuit | |
| JPH0312325B2 (en) | ||
| JPH0140283Y2 (en) | ||
| JP2545374B2 (en) | Differential amplifier circuit having constant current source circuit | |
| JPS6210917A (en) | Differential amplifier type hysteresis comparator circuit | |
| JP3526103B2 (en) | Hysteresis circuit of voltage detector | |
| JP2536649Y2 (en) | Reset signal input circuit | |
| JPH09135157A (en) | Power-on reset circuit | |
| JP2536648Y2 (en) | Reset signal input circuit | |
| JP2705085B2 (en) | Decoder test circuit | |
| JPS6013572B2 (en) | Transient state detection device | |
| JPH04347925A (en) | Power-on reset circuit | |
| JPH0426249B2 (en) |