JPS62145876A

JPS62145876A - Protecting diode for compound semiconductor device

Info

Publication number: JPS62145876A
Application number: JP28832585A
Authority: JP
Inventors: Tetsuo Asano; 哲郎浅野
Original assignee: Sanyo Electric Co Ltd
Current assignee: Sanyo Electric Co Ltd
Priority date: 1985-12-20
Filing date: 1985-12-20
Publication date: 1987-06-29
Anticipated expiration: 2010-05-01
Also published as: JPH0740571B2

Abstract

PURPOSE:To improve the noise index of a compound semiconductor device by ion implanting deeper in depth and thicker in impurity concentration in second diffused region than in a first diffused region to punch the second region through the first region. CONSTITUTION:A second diffused region 4 punches through a first diffused region 3 by ion implanting deeper in depth and thicker in impurity concentration in the second region 4 than in the first region 3. This, since a capacity is generated only by a vertical junction 5, a capacity value can be very much reduced to largely improve a noise index NF. Since a series resistance generated between a source electrode 3 and a gate 1 electrode can be reduced, a current at breakdown time can be abruptly fed.

Description

【発明の詳細な説明】（イ）産業上の利用分野本発明は、化合物半導体装置の耐サージ性を高めるため
に、化合物半導体装置と一部に形成する保護ダイオード
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a protection diode formed in a part of a compound semiconductor device in order to improve the surge resistance of the compound semiconductor device.

（ロ）従来の技術化合物半導体装置、例えばガリウムーヒ素電界効果トラ
ンジスタ（以下ＧａＡｓＭ　Ｅ　Ｓ　Ｆ　Ｅ　Ｔという
。）は低雑音、高利得など優れた特性をもつマイクロ波
帯増幅素子として実用化が盛んにすすめられている。し
かしながら、ＧａＡｓＭＥＳＦＥＴはゲートがショット
キ接合のためゲート・ソース間、ゲート・ドレイン間に
サージエネルギが加わった場合に、ショットキ接合が破
壊されやすい。従って最近ではＧａＡｓを用いてＧａＡ
ｓＭＥＳＦＥＴと保護ダイオードをモノリシック集積化
するなどの対策がなされている（例えば信学技報５ＳＤ
８２−１３２．７５頁乃至７９頁が詳しい、）。(b) Conventional technology Compound semiconductor devices, such as gallium-arsenide field effect transistors (hereinafter referred to as GaAsMESFETs), are being put into practical use as microwave band amplification elements with excellent characteristics such as low noise and high gain. Recommended. However, since the gate of a GaAs MESFET is a Schottky junction, the Schottky junction is easily destroyed when surge energy is applied between the gate and source or between the gate and drain. Therefore, recently, GaAs has been used to
Countermeasures such as monolithic integration of sMESFETs and protection diodes have been taken (for example, IEICE Technical Report 5SD).
82-132.See pages 75 to 79 for details).

ところで前述した保護ダイオードとしては一般に第３図
に示す如く、ＧａＡｓ基板（３２）にイオン注入等で形
成されたＮ型の拡散領域（３３）と、前記Ｎ型の拡散領
域（３３）の一部と接合するように形成きれたＰ＋型の
拡散領域（３４〉とにより構成され、ＧａＡｓＭＥｓＦ
ＥＴのゲート・ソース間に接続された形でモノリシック
集積化されていた。By the way, as shown in FIG. 3, the aforementioned protection diode generally includes an N-type diffusion region (33) formed in a GaAs substrate (32) by ion implantation, etc., and a part of the N-type diffusion region (33). It is composed of a P+ type diffusion region (34) formed so as to be in contact with the GaAsMEsF
It was monolithically integrated, connected between the gate and source of the ET.

（ハ）発明が解決しようとする問題点衛士の如き構成の保護ダイオード（３１）に於いて、Ｐ
”Ｎ接合のうちＰ＋の拡散領域（３４）の底面の一部と
Ｎ型の拡散領域（３３）で形成されている部分の面積が
大きいために寄生容量が増加し雑音指数（ＮＦ）を大巾
に劣化させる原因となっていた。(c) Problems to be solved by the invention In the protection diode (31) having a configuration similar to that of a guard, P
``Because the area of the part of the N junction formed by the part of the bottom of the P+ diffusion region (34) and the N type diffusion region (33) is large, the parasitic capacitance increases and the noise figure (NF) increases. This caused severe deterioration.

（ニ）問題点を解決するための手段本発明は上述した問題点に鑑みてなされ、化合物半導体
基板（２）に形成される化合物半導体装置の保護ダイオ
ード（１）に於いて、前記半導体基板（２）に形成され
る一導電型の第１の拡散領域（３）と、該第１の拡散領
域（３）の一部にイオン注入により形成される逆導電型
の第２の拡散領域（４）とを備え、該第２の拡散領域（
４）の深さと不純物濃度を前記第１の拡散領域（３）よ
り深く、濃くイオン注入することにより該第２の拡散領
域（４）は前記第１の拡散領域（３）を突抜けることで
解決するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a protection diode (1) for a compound semiconductor device formed on a compound semiconductor substrate (2). 2), and a second diffusion region (4) of the opposite conductivity type formed by ion implantation into a part of the first diffusion region (3). ), and the second diffusion region (
4) By implanting ions deeper and more densely than the first diffusion region (3), the second diffusion region (4) can penetrate through the first diffusion region (3). It is something to be solved.

（＊）作用前記第１の拡散領域（３）の一部に第１の拡散領域（３
）より深く濃くイオン注入し突抜けるように形成すると
、従来例（第３図）で示したＰｌの拡散領域（３４）の
底面の一部とＮ型の拡散領域（３３）で形成される容量
は全く発生せず、第１図に示す縦の接合部（５）のみで
容量は発生するので容量値を非常に小さくすることがで
きる。(*) Effect A first diffusion region (3) is formed in a part of the first diffusion region (3).
) If ions are implanted deeper and more densely to form a penetrating shape, a capacitance formed by a part of the bottom of the Pl diffusion region (34) and the N-type diffusion region (33) shown in the conventional example (Fig. 3) will be formed. Since no capacitance is generated at all, and capacitance is generated only at the vertical junction (5) shown in FIG. 1, the capacitance value can be made very small.

（へ）実施例以下に本発明の実施例を図面を参照しながら説明する。(f) Example Embodiments of the present invention will be described below with reference to the drawings.

第１図は本発明による保護ダイオード（１）の一実施例
であり、第２図に示した如＜ＧａＡｓデュアルゲートＭ
ＥＳＦＥＴのゲート１　（Ｇ、）に接続された保護ダイ
オード（２１）の断面図を示すものである。FIG. 1 shows an embodiment of the protection diode (1) according to the present invention, and as shown in FIG.
1 shows a cross-sectional view of a protection diode (21) connected to the gate 1 (G,) of the ESFET.

第１図に示す如く、少なくとも化合物半導体基板（２）
例えば半絶縁性ＧａＡｓ基板に形成される一導電型（Ｎ
型）の第１の拡散領域（３）がある。As shown in FIG. 1, at least a compound semiconductor substrate (2)
For example, one conductivity type (N
There is a first diffusion region (3) of type 1).

ここではＧａＡｓ基板（２）上に例えばＣＶＤ法等を用
いてシリコン酸化膜（６）を約５０００人被覆し、Ｎ型
の第１の拡散領域（３）に対応するシリコン酸化膜（６
）を開口し、シリコンイオン（Ｓｉ”　）をドーズ量５
Ｘ１０　”Ｃｍ””、加速電圧１００ＫｅＶの条件でイ
オン注入しＮ型の第１の拡散領域（３）を形成する。Here, approximately 5,000 silicon oxide films (6) are coated on the GaAs substrate (2) using, for example, the CVD method, and the silicon oxide film (6) corresponding to the N-type first diffusion region (3) is coated with a silicon oxide film (6).
), and silicon ions (Si”) were added at a dose of 5.
Ion implantation is performed under the conditions of X10 "Cm"" and an acceleration voltage of 100 KeV to form an N-type first diffusion region (3).

次に前記第１の拡散領域（３）のほぼ中央にイオン注入
により形成される逆導電型の第２の拡散領域（４）があ
り、該第２の拡散領域（４）は前記第１の拡散領域（３
）を突抜ける。Next, there is a second diffusion region (4) of the opposite conductivity type formed by ion implantation approximately in the center of the first diffusion region (3), and the second diffusion region (4) is similar to that of the first diffusion region (4). Diffusion area (3
) to break through.

従って前記第２の拡散領域（４）で２分割されたＮ型の
第１の拡散領域（３）（３）とＰ型の第２の拡散領域（
４）　とで第２図におけるゲート１（Ｇｌ）に接続され
た２つのダイオードがＮＰＮ型で形成きれゲート１（Ｇ
ｌ）の保護ダイオード（１）として構成される。Therefore, the second diffusion region (4) is divided into two parts: an N-type first diffusion region (3) (3) and a P-type second diffusion region (
4) With and, the two diodes connected to gate 1 (Gl) in Fig. 2 are formed of NPN type.
l) is configured as a protection diode (1).

本発明の特徴とするところは、前記第１の拡散領域（３
）の一部にイオン注入により形成される逆導電型の第２
の拡散領域（４）であり、該第２の拡散領域（４）の深
さと不純物濃度を第１の拡散領域（３）より深く、濃く
イオン注入し、前記第２の拡散領域（４）は前記第１の
拡散領域（３）を突抜けることにある。The feature of the present invention is that the first diffusion region (3
) of opposite conductivity type formed by ion implantation in a part of the
The depth and impurity concentration of the second diffusion region (4) are deeper and more concentrated than the first diffusion region (3), and the second diffusion region (4) is The purpose is to penetrate through the first diffusion region (3).

つまりここでは前記ＧａＡｓ基板（２）上に同様にシリ
コン酸化膜（６）を被覆し直し、前記Ｐ型の第２の拡散
領域（４）に対応する領域のシリコン酸化膜を除去し、
開口部に亜鉛イ“オン（Ｚ、”）をドーズ量Ｉ　Ｘ　１
０　”ｃｍ−”、加速電圧３６０ＫｅＶの条件で注入す
る。That is, here, the silicon oxide film (6) is similarly recoated on the GaAs substrate (2), and the silicon oxide film in the region corresponding to the P-type second diffusion region (4) is removed.
Zinc ion (Z, ”) is applied to the opening at a dose of I x 1
0 "cm-" and an acceleration voltage of 360 KeV.

従って前記第１の拡散領域（３）の略中夫にイオン注入
により突抜けるように形成す・・ると、従来例（第３図
）で示したＰ型の拡散領域（３４）の底面の一部とＮ型
の拡散領域（３３）で形成される如き容量は全く発生し
ない。そのため第１図に示す縦の接合部のみで容量は発
生するので容量値を非常に小さくできる。Therefore, if the first diffusion region (3) is formed by ion implantation so as to penetrate through it, the bottom surface of the P-type diffusion region (34) shown in the conventional example (Fig. 3) can be formed. No capacitance such as that formed between the part and the N-type diffusion region (33) is generated. Therefore, since capacitance is generated only at the vertical junction shown in FIG. 1, the capacitance value can be made very small.

またイオン注入で形成するためＰ型の第２の拡散領域（
４）の幅を非常に小さくできるためソース電極とゲート
１電極間に生じるシリーズ抵抗を小さくできる。In addition, since it is formed by ion implantation, a P-type second diffusion region (
4) Since the width of the electrode can be made very small, the series resistance generated between the source electrode and the gate 1 electrode can be made small.

以上はＮＰＮ型のダイオードで説明したが、第４図に示
す如＜ＰＮ型のダイオード（４１〉等でも良い。Although the above description has been made using an NPN type diode, a PN type diode (41) as shown in FIG. 4 may also be used.

（ト）発明の効果本発明は以上の説明からも明らかな如く、前記第１の拡
散領域（３）の一部にイオン注入により形成される逆導
電型の第２の拡散領域（４）が前記第１の拡散領域（３
）を突抜けると、容量値を非常に小きくできるため雑音
指数（ＮＦ）を大幅に向上させることができる。(G) Effects of the Invention As is clear from the above description, the present invention includes a second diffusion region (4) of an opposite conductivity type formed by ion implantation in a part of the first diffusion region (3). The first diffusion region (3
), the capacitance value can be made very small and the noise figure (NF) can be greatly improved.

またソース電極とゲート１電極間に生じるシリーズ抵抗
を小さくできるため、ブレーク・ダウン時の電流を急激
に流すことができる。Further, since the series resistance generated between the source electrode and the gate 1 electrode can be reduced, current can be rapidly caused to flow at the time of breakdown.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第４図は本発明の実施例であり化合物半導体
装置の保護ダイオードを示す断面図、第２図はデュアル
・ゲートＭＥＳＦＥＴに保護ダイオードを設けた時の接
続図、第３図は従来の保護ダイオードの断面図である。（１）は化合物半導体装置の保護ダイオード、（２）は
基板、（３）は第１の拡散領域、（４〉は第２の拡散領
域、（５）は接合部、（６）はシリコン酸化膜である。第１図第２図1 and 4 are embodiments of the present invention, and are cross-sectional views showing protection diodes for compound semiconductor devices, FIG. 2 is a connection diagram when a protection diode is provided in a dual-gate MESFET, and FIG. 3 is a conventional FIG. 3 is a cross-sectional view of a protection diode. (1) is a protection diode of a compound semiconductor device, (2) is a substrate, (3) is a first diffusion region, (4> is a second diffusion region, (5) is a junction, and (6) is a silicon oxide It is a membrane. Figure 1 Figure 2

Claims

【特許請求の範囲】[Claims]

（１）化合物半導体基板に形成される化合物半導体装置
の保護ダイオードに於いて、前記半導体基板に形成され
る一導電型の第１の拡散領域と、該第１の拡散領域の一
部にイオン注入により形成される逆導電型の第２の拡散
領域とを備え、該第２の拡散領域の深さと不純物濃度を
前記第１の拡散領域より深く、濃くイオン注入すること
により、前記第２の拡散領域は前記第１の拡散領域を突
抜けることを特徴とした化合物半導体装置の保護ダイオ
ード。(1) In a protection diode for a compound semiconductor device formed in a compound semiconductor substrate, ion implantation is performed into a first diffusion region of one conductivity type formed in the semiconductor substrate and a part of the first diffusion region. and a second diffusion region of opposite conductivity type formed by the second diffusion region, and by implanting ions to make the depth and impurity concentration of the second diffusion region deeper and more concentrated than the first diffusion region, the second diffusion region is A protection diode for a compound semiconductor device, wherein the region penetrates through the first diffusion region.