JPS62109462U - - Google Patents

Info

Publication number
JPS62109462U
JPS62109462U JP20151385U JP20151385U JPS62109462U JP S62109462 U JPS62109462 U JP S62109462U JP 20151385 U JP20151385 U JP 20151385U JP 20151385 U JP20151385 U JP 20151385U JP S62109462 U JPS62109462 U JP S62109462U
Authority
JP
Japan
Prior art keywords
circuit
output
decoding
wiring body
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20151385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20151385U priority Critical patent/JPS62109462U/ja
Publication of JPS62109462U publication Critical patent/JPS62109462U/ja
Pending legal-status Critical Current

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Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Control Of Voltage And Current In General (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のトリミング機能付半導体集積
回路を定電圧回路に用いた回路図、第2図a〜c
は第1図の回路内のコンタクト部の集積回路基板
上での断面図である。 18a……SiO、19a,19b……ポリ
シリコン、20a……領域、21a……出力調整
部、21b……デコーダ、22……出力設定部、
23〜25……コンタクト部。
Fig. 1 is a circuit diagram in which the semiconductor integrated circuit with trimming function of the present invention is used in a constant voltage circuit, and Fig. 2 a to c
2 is a cross-sectional view of a contact portion in the circuit of FIG. 1 on an integrated circuit board; FIG. 18a... SiO2 , 19a, 19b...polysilicon, 20a...region, 21a...output adjustment section, 21b...decoder, 22...output setting section,
23-25...Contact part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 設定データを記憶する記憶回路と、該記憶回路
の出力を復号回路と、該復号回路の出力を受けて
、出力が可変される出力設定回路とを有する半導
体集積回路において、前記記憶回路の一端に接続
された第1の配線体と、特定電位に接続された第
2の配線体と、前記第1、第2の配線体間に配設
されレーザ光により破壊される絶縁層とを有する
ことを特徴とするトリミング機能付半導体集積回
路。
A semiconductor integrated circuit comprising a memory circuit for storing setting data, a decoding circuit for decoding the output of the memory circuit, and an output setting circuit whose output is varied in response to the output of the decoding circuit, at one end of the memory circuit. A first wiring body connected to the wiring body, a second wiring body connected to a specific potential, and an insulating layer disposed between the first and second wiring bodies and destroyed by a laser beam. A semiconductor integrated circuit with a featured trimming function.
JP20151385U 1985-12-26 1985-12-26 Pending JPS62109462U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20151385U JPS62109462U (en) 1985-12-26 1985-12-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20151385U JPS62109462U (en) 1985-12-26 1985-12-26

Publications (1)

Publication Number Publication Date
JPS62109462U true JPS62109462U (en) 1987-07-13

Family

ID=31165036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20151385U Pending JPS62109462U (en) 1985-12-26 1985-12-26

Country Status (1)

Country Link
JP (1) JPS62109462U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009087293A (en) * 2007-10-03 2009-04-23 Nec Electronics Corp Stabilized power supply circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009087293A (en) * 2007-10-03 2009-04-23 Nec Electronics Corp Stabilized power supply circuit

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