JPS62108184A - Digital timepiece device - Google Patents

Abstract

PURPOSE:To obtain the time synchronized with the other timepiece device by inputting a synchronizing signal from the other timepiece to a titled device and allowing the synchronizing signal to follow up the stepping of an internal calender timepiece circuit. CONSTITUTION:The synchronizing signal 12 and a relational discrimination signal 13 from a calender timepiece circuit 5 are respectively applied to a synchronizing signal interruption detection circuit 1 and an advance/delay discrimination circuit 2. The signal is monitored by the signal 13 in the circuit 1 and the presence/absence of the synchronizing signal are continuously judged for several seconds. The synchronizing signal interruption signal is applied to a frequency dividing control circuit 3 in the stage of the absence thereof. The signal 13 and the signal 12 are compared in the circuit 2. Whether there is the signal 2 in the first half of the signal 13 or whether there is the signal 12 in the second half is discriminated and the advance/delay signal is applied to the circuit 3. The circuit 3 applies a command signal 16 for the frequency division by 1/n to a variable frequency dividing circuit 4 by the signal 14 and the signal 15 when the synchronizing signal is interrupted. Said circuit applies a command signal 18 for the frequency division by 1/(n-1) when there is the synchronizing signal and the delay is discriminated. The time synchronized with the other timepiece deice is thus obtd.

Description

【発明の詳細な説明】 １産業上の利用分野゛１ 本発明はデジタル時計装置に関し、特に他の時計装置と
同期した時刻を発生するデジタル時計装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION 1. Field of Industrial Application 1. The present invention relates to a digital clock device, and particularly to a digital clock device that generates time synchronized with other clock devices.

〔従来の技術〕[Conventional technology]

第２図は従来のデジタル時計装置の一例を示すブロック
図で、カレンダ時計回路３１とクロック発振器３２とか
らなり、時刻初期人力３４によりカレンダ時計回路３１
を初期設定し、その後の時刻の歩進はクロック発振器３
２からのクロックパルスで行ない時刻出力３３を得るよ
うになっていた。FIG. 2 is a block diagram showing an example of a conventional digital clock device, which includes a calendar clock circuit 31 and a clock oscillator 32.
is initialized, and the subsequent time increments are performed by clock oscillator 3.
The clock pulse from 2 is used to obtain a time output 33.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のデジタル時計装置では、時刻の歩進をク
ロック発振器のクロックで行なっているので、時計の精
度はクロック発振器の精度で決定され、他の時計装置と
の間に狂いが生じる欠点がある。In the conventional digital clock device described above, the time is advanced by the clock of the clock oscillator, so the precision of the clock is determined by the precision of the clock oscillator, which has the disadvantage that it may deviate from other clock devices. .

〔問題点を解決するための手段〕[Means for solving problems]

本発明のデジタル時計装置は、クロック発振器と、カレ
ンダ時計回路と、外部からの同期信号と前記カレンダ時
計回路からの比較判定信号によりそれぞれ同期信号の断
検出および進み／遅れ判定を行なう検出手段および判定
手段と、その検出および判定結果に基づき前記クロック
発振器からのクロックを分周する可変分周回路の分周率
を制御する制御手段とを備え、前記可変分周回路の出力
により前記カレンダ時計回路を歩進させている。The digital clock device of the present invention includes a clock oscillator, a calendar clock circuit, and a detection means and determination device for detecting disconnection of a synchronization signal and determining lead/lag, respectively, based on an external synchronization signal and a comparison determination signal from the calendar clock circuit. and control means for controlling the frequency division ratio of a variable frequency divider circuit that divides the clock from the clock oscillator based on the detection and determination results, and the calendar clock circuit is controlled by the output of the variable frequency divider circuit. We are making progress.

〔実施例〕〔Example〕

次に、本発明について、第１図を参照して説明する。 Next, the present invention will be explained with reference to FIG.

第１図は本発明のデジタル時計装置の一実施例を示すブ
ロック図である。FIG. 1 is a block diagram showing an embodiment of the digital timepiece device of the present invention.

同図において、デジタル時計装置は、外部からの同期信
号１２と内蔵するカレンダ時計回路５から作る比較判定
信号１３により同期信号の断を検出する同期信号断検出
回路１と、進み遅れを判定する進み／遅れ判定回路２と
、同期信号断と進み遅れの判定の結果に基づき可変分周
回路４の分周率を制御する分周制御回路３と、クロック
発振器６とからなる。In the figure, the digital clock device includes a synchronization signal disconnection detection circuit 1 that detects disconnection of the synchronization signal based on a comparison judgment signal 13 generated from an external synchronization signal 12 and a built-in calendar clock circuit 5, and a synchronization signal disconnection detection circuit 1 that detects disconnection of the synchronization signal by using a comparison judgment signal 13 generated from an external synchronization signal 12 and a built-in calendar clock circuit 5. It consists of a /delay determination circuit 2, a frequency division control circuit 3 that controls the frequency division ratio of the variable frequency division circuit 4 based on the results of determination of synchronization signal disconnection and lead/lag, and a clock oscillator 6.

続いて本実施例の動作について説明する。Next, the operation of this embodiment will be explained.

外部からの１分周期の同期信号１２とカレンダ時計回路
５からのパルス幅比率１対１で１分周期の比較判定信号
１３がそれぞれ同期信号断検出回路１と進み、／′遅れ
′同定回路２に与えられる。同期信号断検出回路１では
比較判定信号１３により同期信号１２を監視し、数分間
連続して同期信号の有／無を判断して無のときは同期信
号断信号１４を分周制御回路３に与える。進み／遅れ判
定回路２ではパルス幅比率１対１の比較判定信号１３と
同期信号１２を比較し、比較判定信号１３の前半に同期
信号１２があるか、後半に同期信号１２があるかを判定
して進み／遅れ信号１５を分周制御回路３に与える０分
周制御回路３は同期信号断信号１４と進み／遅れ信号１
５により可変分周回路４に対し、同期信号断のときは１
、−’　ｎ分周指令信号１６を、同期信号が有りかつ進
みの判定のときは１／（ｎ＋１）分周指令信号１７を、
同期信号が有りかつ遅れの判定のときは１／（ｎ−１）
分周指令信号１８を与える。可変分周回路４はクロック
発振器６からのクロックを分周制御回路３からの前記分
周指令信号に従って１．／ｎまたは１／（ｎ＋１）また
は１／（ｎ−１＞の分周含し、時計歩進クロックパルス
１１をカレンダ時計回路５に与える。カレンダ時計回路
５は時計歩進クロックパルス１１により、秒１分９時１
日、曜日１月。A synchronization signal 12 with a period of 1 minute from the outside and a comparison judgment signal 13 with a period of 1 minute with a pulse width ratio of 1:1 from the calendar clock circuit 5 are each advanced to the synchronization signal disconnection detection circuit 1, and the /'delay' identification circuit 2 given to. The synchronization signal disconnection detection circuit 1 monitors the synchronization signal 12 using the comparison judgment signal 13, continuously judges the presence/absence of the synchronization signal for several minutes, and when there is no synchronization signal, sends the synchronization signal disconnection signal 14 to the frequency division control circuit 3. give. The lead/lag determination circuit 2 compares the comparison determination signal 13 with a pulse width ratio of 1:1 and the synchronization signal 12, and determines whether the synchronization signal 12 is present in the first half of the comparison determination signal 13 or the synchronization signal 12 is present in the second half. The 0 frequency division control circuit 3 sends the lead/lag signal 15 to the frequency division control circuit 3, which outputs the synchronization signal disconnection signal 14 and the lead/lag signal 1.
5 sets the variable frequency divider circuit 4 to 1 when the synchronizing signal is disconnected.
, -'n frequency division command signal 16, 1/(n+1) frequency division command signal 17 when there is a synchronization signal and advance is determined,
1/(n-1) when there is a synchronization signal and there is a delay
A frequency division command signal 18 is given. The variable frequency divider circuit 4 divides the clock from the clock oscillator 6 into 1. /n or 1/(n+1) or 1/(n-1>) and applies a clock advance clock pulse 11 to the calendar clock circuit 5.The calendar clock circuit 5 uses the clock advance clock pulse 11 to 1 minute 9:01
Day, day of the week, January.

年の歩進を行なう。また、カレンダ時計回路５は時刻初
期入力２０により初期設定ができると共に、時刻出力１
９を出力する。Make yearly progress. Further, the calendar clock circuit 5 can be initialized by a time initial input 20, and also has a time output 1.
Outputs 9.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、他の時計がらの同期信号
を入力し、この同期信号に内部のカレンダ時計回路の歩
進を追従させることにより、他の時計装置と同期した時
刻を得ることができる効果がある。As explained above, the present invention makes it possible to obtain time synchronized with other clock devices by inputting a synchronization signal from another clock and having this synchronization signal follow the progress of the internal calendar clock circuit. There is an effect that can be done.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明のデジタル時計装置の一実施例を示すブ
ロック図、第２図は従来のデジタル時計装置の一例を示
すブロック図である。 １・・・同期信号１ｔ７ｉ検出回路、２・・・進み、／
遅れ判定回路、３・・・分周制御回路、４・・・可変分
周回路、５３１・・・カレンダ時計回路、６．３２・・
・クロック発振器、１１・・・時計歩進クロックパルス
、１２・・・同期信号、１３・・・比較判定信号、１４
・・・同期信号断信号、１５・・・進み／遅れ信号、１
６・・・１．／ｎ分周指令信号、１７・・・１／　（ｎ
＋１）分周指令信号、１８・・・１／（ｎ−１）分周指
令信号、１９．３３・・・時刻出力、２０．３４・・・
時刻初期入力。FIG. 1 is a block diagram showing an embodiment of a digital timepiece device of the present invention, and FIG. 2 is a block diagram showing an example of a conventional digital timepiece device. 1... Synchronous signal 1t7i detection circuit, 2... Advance, /
Delay determination circuit, 3... Frequency division control circuit, 4... Variable frequency division circuit, 531... Calendar clock circuit, 6.32...
・Clock oscillator, 11... Clock step clock pulse, 12... Synchronization signal, 13... Comparison judgment signal, 14
... Synchronization signal disconnection signal, 15 ... Lead/lag signal, 1
6...1. /n frequency division command signal, 17...1/ (n
+1) Frequency division command signal, 18...1/(n-1) frequency division command signal, 19.33...Time output, 20.34...
Initial time input.

Claims (1)

【特許請求の範囲】[Claims] クロック発振器とカレンダ時計回路とを備えるデジタル
時計装置において、外部からの同期信号と前記カレンダ
時計回路からの比較判定信号によりそれぞれ同期信号の
断検出および進み／遅れ判定を行なう検出手段および判
定手段と、その検出および判定結果に基づき前記クロッ
ク発振器からのクロックを分周する可変分周回路の分周
率を制御する制御手段とを備え、前記可変分周回路の出
力により前記カレンダ時計回路を歩進させることを特徴
とするデジタル時計装置。In a digital clock device including a clock oscillator and a calendar clock circuit, a detection means and a determination means for detecting disconnection of a synchronization signal and determining whether the synchronization signal is ahead or behind, respectively, based on an external synchronization signal and a comparison determination signal from the calendar clock circuit; control means for controlling the frequency division ratio of a variable frequency divider circuit that frequency divides the clock from the clock oscillator based on the detection and determination results, and advances the calendar clock circuit by the output of the variable frequency divider circuit. A digital clock device characterized by: