JPS6197964A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6197964A JPS6197964A JP21991284A JP21991284A JPS6197964A JP S6197964 A JPS6197964 A JP S6197964A JP 21991284 A JP21991284 A JP 21991284A JP 21991284 A JP21991284 A JP 21991284A JP S6197964 A JPS6197964 A JP S6197964A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- charge
- silicon layer
- source region
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 28
- 239000010703 silicon Substances 0.000 abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 27
- 238000002844 melting Methods 0.000 abstract description 20
- 230000008018 melting Effects 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 12
- 229910052594 sapphire Inorganic materials 0.000 abstract description 12
- 239000010980 sapphire Substances 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 9
- 238000005086 pumping Methods 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 description 21
- 239000002184 metal Substances 0.000 description 21
- 238000000137 annealing Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 244000201986 Cassia tora Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000003610 charcoal Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- NCAIGTHBQTXTLR-UHFFFAOYSA-N phentermine hydrochloride Chemical compound [Cl-].CC(C)([NH3+])CC1=CC=CC=C1 NCAIGTHBQTXTLR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
- H01L29/78657—SOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔兄明の技術分野〕
本発明は半導体装置に関し、特にサファイア等の絶縁性
基板上に設けられた島状の半纏体層に改良を加えた５Ｏ
８（Ｓｉｌｉｃｏｎ Ｏｎ ５ａｐｐｉｒａ）構造のＭ
ＯＳ ！ トランジスタに係わる。[Detailed Description of the Invention] [Technical Field of Brother Mei] The present invention relates to a semiconductor device, and in particular to a 5O semiconductor device which is an improved island-shaped semi-solid layer provided on an insulating substrate such as sapphire.
8 (Silicon On 5appira) structure M
OS! Related to transistors.
周知の如く、ＳＯ８とかＳＯＩと呼ばれている絶縁性基
板の上にシリコンを気相成長させた基板を用いてＭＯ８
集積回路を製造されている。この場合、基板が絶縁され
ているため、完全な？イソレーションができ丞板に関係
した容量や寄生効果を大幅に低減することができ、高速
、かつ高性能な素子を得ることができるとされていた。As is well known, MO8 is produced using an insulating substrate called SO8 or SOI, in which silicon is grown in vapor phase.
Integrated circuits are manufactured. In this case, since the board is insulated, is it complete? It was believed that isolation could be achieved and the capacitance and parasitic effects related to the plate could be significantly reduced, making it possible to obtain high-speed, high-performance devices.
しかしながら、素子を微細化し、高速動作を行なわせた
場合、ＳＯ８構造のＭＯ８型トランノスタにおいては、
これに固有なテヤーノポンピング作用が起こり、絶縁性
基板を用いたことによる高速動作が損なわれることが明
らかになった（Ｃｈａｒｇｅ ｐｕｍｐｌｎｇ ｉｎ
５０８−ＭＯＳ Ｔｒａｎｓｉｓｔｏｒａ＋Ｎ、５ａａ
ａｋｉ、ＩＥ３． ｔｒａｎｍ−ＥＤ、１１ｏｔＥＤ
−２８，ＮＯＩ ｐ４８゜１９８１．１゜以下、テヤ
ーノボンビング作用とその影響について第２図き参照し
て説明する。However, when the element is miniaturized and operated at high speed, in the MO8 type trannostar with SO8 structure,
It has become clear that a unique Teyano pumping effect occurs, impairing the high-speed operation achieved by using an insulating substrate (Charge pumping in
508-MOS Transistora+N, 5aa
aki, IE3. tranm-ED, 11otED
-28, NOI p48゜1981.1゜The Teyano bombing action and its influence will be explained below with reference to Figure 2.
図中の１は、サファイアである。このサファイアｌ上に
は例えばｐｌの半纏体層２が設けられ、該半纏体層２に
Ｎ＋型のソース領域３、ドレイン狽域４が夫々離間して
設けられている。前記半導体層２上には、ゲート酸化膜
５を介してゲート電極６が設けられている。1 in the figure is sapphire. On this sapphire l, a semi-enveloped layer 2 of, for example, pl is provided, and an N+ type source region 3 and a drain entrapment region 4 are provided in the semi-enveloped layer 2, spaced apart from each other. A gate electrode 6 is provided on the semiconductor layer 2 with a gate oxide film 5 interposed therebetween.
こうした構造のＭＯ８型トラ／ノスタにおいて、ゲート
・ぐルスＶ。があるｆ直よシ大きくなると、チャネルを
形成しているソース、ドレイン領域３゜４とゲート酸化
膜５の界面にホール７が流れる。In the MO8 type Tora/Nosta with this structure, Gate Gurus V. When f becomes larger than a certain value, holes 7 flow to the interface between the source and drain regions 3.4 forming a channel and the gate oxide film 5.
そして、その後ｒ−）電極６がＯｖになシチャネルがオ
フされるとホール７が半導体層２に注入される、いわゆ
るチャージポンピング作用が生じる。その結果、注入さ
れたホール７によジンース、ドレイン領域３．４は逆バ
イアスさヘテヤーノの蓄積が起こって半導体Ｊｌｊ８の
電位が上昇する。これにより、トランジスタのしきい値
ｖｔｈの変化（基板バイアス効果）が引起こされる。こ
の効果は、ゲート長が短縮されてトランジスタが微細化
されるに伴い半導体層８の不純物一度が制くした場合、
特に顕著にあられれる。従って、例えばＳＯ８構造のＭ
Ｏ８型トランジスタでＣＭＯＳインバータ回路等を構成
し、そのゲート艮を縮小してもその遅延時間はチャーツ
ボ／ピング作用に起因した基板バイアス効果のためほと
んど改畳されない。Thereafter, when the r-) electrode 6 becomes Ov and the channel is turned off, holes 7 are injected into the semiconductor layer 2, resulting in a so-called charge pumping effect. As a result, the injected holes 7 cause accumulation of reverse bias in the drain region 3.4, and the potential of the semiconductor Jlj8 increases. This causes a change in the threshold voltage vth of the transistor (substrate bias effect). If this effect is suppressed once the impurities in the semiconductor layer 8 are suppressed as the gate length is shortened and transistors are miniaturized,
Especially noticeable. Therefore, for example, M of SO8 structure
Even if a CMOS inverter circuit or the like is configured with O8 type transistors and the gate size thereof is reduced, the delay time is hardly changed due to the substrate bias effect caused by the chartrebo/ping effect.
本発明は上記事情に鑑みてなされたもので、チャージポ
ンピング作用を抑制し、基板バイアス効果によるしきい
値変動を阻止し得る高速動作化、微細化可能な半導体装
置を提供することを目的とする。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that can operate at high speed and be miniaturized, which can suppress the charge pumping effect and prevent threshold fluctuations due to the substrate bias effect. .
本発明は、ソース領域とチャネル領域にまたがるように
４篭層を設け、これによりチャージポンピング作用で半
導体層に注入されたチャージをそこに蓄積させることな
く、速やかにソース領域に引き出し、もって主としてし
きい値変動の阻止を図ったことを骨子とする。The present invention provides four cage layers spanning the source region and the channel region, whereby charges injected into the semiconductor layer by a charge pumping action are quickly drawn out to the source region without being accumulated there. The main idea is to prevent threshold fluctuations.
以下、本発明の一実施例に係るＳＯＳ構造のＭＯ８型ト
ランジスタを製造工程順に第１図（、）〜（ｄ） ｔ−
参照して説明する。1(a) to (d) t-
Refer to and explain.
〔１〕まず、絶縁性基板としてのサファイア２ノ上にＷ
（タングステン）やＭｏ（モリブデンノ等の高融点金属
をス・セッタリング法等によシ薄ぐ（数１００Ｘ以下）
蒸着した。つづいて、写真蝕刻技術及びエツチング技術
によシ、所定形状の４電層としての高融点金属層２２を
形成した（第１図（、）図示）。次いで、サファイア２
１全面にシリコンを気相成長法などにより堆積し九この
結果、高融金属層２２上には多結晶シリコン層２３が形
成され、かつ前記金属層２２を除くサファイア２ノ上に
はシリコン層２４が形成された（第１図（ｂ）図示）。[1] First, W is placed on sapphire 2 as an insulating substrate.
High melting point metals such as (tungsten) and Mo (molybdenum) are diluted (several 100X or less) by the S-setterling method, etc.
Deposited. Subsequently, a high melting point metal layer 22 as a tetraelectric layer having a predetermined shape was formed by photolithography and etching (as shown in FIG. 1(,)). Next, Sapphire 2
As a result, a polycrystalline silicon layer 23 is formed on the high-melting metal layer 22, and a silicon layer 24 is formed on the sapphire 2 excluding the metal layer 22. was formed (as shown in FIG. 1(b)).
〔１１」次に、前記多結晶シリコ／層２３をレーデアニ
ール及びＥＢアニール等のアニール技術により準結晶化
し、シリコン層とした（第１図（ｃ）図示）。つづいて
、前記シリコン層２４を周知の仮術により島状とした。[11] Next, the polycrystalline silicon/layer 23 was quasi-crystalized by an annealing technique such as radar annealing and EB annealing to form a silicon layer (as shown in FIG. 1(c)). Subsequently, the silicon layer 24 was formed into an island shape using a well-known temporary technique.
次いで、この島状のシリコン層２４にＮ＋型のソース、
ドレイン領域２５．２６を形成した。この際、ソース領
域２５は、前記金属）ｔｇ２２がソース領域２５とチャ
ネル領域を形成するシリコン層２７にまたがるように位
置合わせした。この位置合わせは、従来のアライメント
技術で容易に行なうことができる。しかる後、チャネル
領域上にゲートｅ化膜２８を介してゲート電極２９を形
成し、所望のＳＯ８構造のＭＯ８型トランジスタを製造
した（第１図（ｄ）図示〕。Next, an N+ type source,
Drain regions 25 and 26 were formed. At this time, the source region 25 was aligned so that the metal tg22 spanned the source region 25 and the silicon layer 27 forming the channel region. This alignment can be easily accomplished using conventional alignment techniques. Thereafter, a gate electrode 29 was formed on the channel region via the gate e-oxide film 28, and an MO8 type transistor with a desired SO8 structure was manufactured (as shown in FIG. 1(d)).
本発明に係るＭＯ８型トランジスタは、第１図（ｄ）に
示す如く、高融点金属）ｄ２２をサファイア２１表面に
接しつつＮ＋型のソース領域２５とチャネル領域が形成
されるシリコン層２７にまたがるように設けた構造とな
っている。In the MO8 type transistor according to the present invention, as shown in FIG. 1(d), the high melting point metal d22 is placed in contact with the surface of the sapphire 21 and extends over the silicon layer 27 in which the N+ type source region 25 and channel region are formed. It has a structure set up in
しかして、本発明によれば、高融点金属層２２の存在に
よプ、チャージポンピング作用によってシリコン層２７
に注入されたチャージを、高融点金属層２２全通して速
やかにソース領域２５に流すことができる。従って、シ
リコンノ曽２７に前記チャージが蓄積されることなく、
基板バイアス効果によるしきい値変４ｈを阻止できる。According to the present invention, the presence of the high-melting point metal layer 22 causes the silicon layer 27 to rise due to the charge pumping action.
The charges injected into the source region 25 can quickly flow through the entire high melting point metal layer 22 to the source region 25. Therefore, the charge is not accumulated in the silicon noso 27,
It is possible to prevent the threshold value change 4h due to the substrate bias effect.
その結果、例えば０ＭＯ３のインバータにより論理回路
を構成した場合、その遅延時間に対する態形＃を回避で
きる。特に、高速動作をさせるためにゲート長をサブミ
クロンの長さにまで縮小した場合、トランジスタの・ぐ
ンテスルーを防止するためにシリコン層２７にイオン注
入によシネ縄物を添加するが、本発明によればシリコン
層２７の不純物濃度が高くてもチャーシボ／ピング作用
の影響を完全に抑えることができ、安定した効率のよい
高速動作を可能ならしめる。As a result, when a logic circuit is constructed using, for example, an 0MO3 inverter, form # for the delay time can be avoided. In particular, when the gate length is reduced to a sub-micron length for high-speed operation, a cylindrical material is added to the silicon layer 27 by ion implantation to prevent transistor throughput. According to the above, even if the impurity concentration of the silicon layer 27 is high, the influence of the charcoal/pumping effect can be completely suppressed, making stable, efficient, and high-speed operation possible.
なお、上記実施例では、高融点金属Ｍをサファイア上に
徽して設けた場合について述べたが、これに限らない。In addition, although the above-mentioned Example described the case where the high melting point metal M was provided on sapphire, it is not limited to this.
例えば、第３図（、）〜（（り Ｖｒ−示すように設け
てもよい。まず、サジアイア２１に跡３１ｔｌ−形成し
た（第３図（、）図示〕。つづいて、高融点金属層４層
３２、平坦化材としてのレノスト層３３を順次形成した
（第３図（ｂ）図示〕。次いで、エッチ・々ツク技術に
より溝３１内に高融点金属層３２′を残存させた。以下
、上記実施例と同様にしてＮ＋型のソース、ドレイン領
域２５゜２６及びゲート電極２９′ｆ、形成すれば、Ｓ
ＯＳ構造のＭＯ８型トランジスタを製造される（第３図
（Ｃ）図示少。また、高融点金属層は、第４図〜第６図
に示すように設けてもよい。以下順に説明する。For example, the traces 31tl- may be provided as shown in FIG. A layer 32 and a renost layer 33 as a planarizing material were sequentially formed (as shown in FIG. 3(b)).Next, the refractory metal layer 32' was left in the groove 31 by an etch-and-scratch technique.Hereinafter, If N+ type source and drain regions 25 and 26 and gate electrode 29'f are formed in the same manner as in the above embodiment, S
An MO8 type transistor having an OS structure is manufactured (FIG. 3(C), not shown).Furthermore, the high melting point metal layer may be provided as shown in FIGS.
第４図は、サファイア２１上に第１の島状のシリコン層
４１ｔ−形成した後、このシリコン層４ノ上に高融点金
属層４２ｆｃ形成し、ひきつづき上記実施例と同様に第
２の島状のシリコン層４３を形成するもので、前記金属
層４２は第１゜第２のシリコン層４１．４Ｊの積層の厚
み方向の中央より上側に配置される。FIG. 4 shows that after forming a first island-shaped silicon layer 41t on sapphire 21, a high melting point metal layer 42fc is formed on this silicon layer 4, and then a second island-shaped silicon layer 41t is formed on the silicon layer 4. The metal layer 42 is disposed above the center in the thickness direction of the stack of the 1st and 2nd silicon layers 41.4J.
第５図は、高融点金属層５ノを、第１．第２のシリコン
）ｄ’４１ 、４３の積層の厚み方向の中央より下側に
配置したものである。その形成方法は、第１のシリコン
層４ノを形成後、該シリコン層に溝５２を設け、更にこ
の溝５２に高融点金属Ｎ５１を残存させ、ひきつづき第
２のシリコン層４３を形成するものである。FIG. 5 shows the high melting point metal layer 5 in the first layer. (second silicon) d'41, 43 is placed below the center in the thickness direction of the stacked layers. The formation method is to form a first silicon layer 4, then provide a groove 52 in the silicon layer, leave high melting point metal N51 in this groove 52, and then form a second silicon layer 43. be.
第６図は、高融点金属１＠６１を島状のシリコン層２４
の界面に設けたものである。FIG. 6 shows a high melting point metal 1@61 in an island-like silicon layer 24.
It is provided at the interface of
上記実施例では、全面にシリコン全気相′成長後高融点
金属層上の多結晶シリコン層をアニール技術によυ単結
晶化する場合について述べたが、これに限らず、高融点
金属ＪＷＩを形成後ＣＶＤ法などにより全面に多結晶シ
リコン層を形成し、これをアニール技術で単結晶しても
よい。In the above embodiment, the case where the polycrystalline silicon layer on the high melting point metal layer is made into a single crystal by annealing technology after silicon is grown in full vapor phase on the entire surface is described, but this is not limited to this. After the formation, a polycrystalline silicon layer may be formed on the entire surface by a CVD method or the like, and this may be made into a single crystal by an annealing technique.
上記実施例では、導電層として高融点金属層を用いた場
合について述べたが、これに限らず、チャネル領域と高
融点金属層の接続抵抗が大きい場合には、従来技術を用
いて所定の部分に高濃度のイオン注入層を設ければよい
。In the above embodiment, a case is described in which a high melting point metal layer is used as the conductive layer, but this is not limited to this. If the connection resistance between the channel region and the high melting point metal layer is large, a predetermined portion can be formed using conventional technology. A high-concentration ion-implanted layer may be provided.
上記実施例では、ＷやＭｏ等からなる高融点金属層を用
いたが、これに限らず、高融点金属シリサイド層でもよ
い。In the above embodiment, a high melting point metal layer made of W, Mo, etc. is used, but the layer is not limited to this, and a high melting point metal silicide layer may also be used.
上記実施例では、絶縁性基板としてサファイアを用いた
場合について述べたが、これに限らず、例えばシリコン
基板上に酸化膜を形成したものでもよい。In the above embodiment, a case was described in which sapphire was used as the insulating substrate, but the present invention is not limited to this, and, for example, an oxide film formed on a silicon substrate may be used.
〔発明の効果」
以上詳述した如く本発明によれば、しきい値変動を阻止
し得る高速動作化、微細化可能な高信頼性のＳＯ８構造
のＭＯ８型トランジスタ等の半導体装置を提供できる。[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a semiconductor device such as an MO8 type transistor with an SO8 structure that can operate at high speed and can be miniaturized with high reliability, which can prevent threshold fluctuations.
第１図（、）〜（ｄ）は本発明の一実施例に係るＳＯ３
構造のＭＯ８型トランノスタ全製造工程順に示す断面図
、第２図は従来のＳＯ８構造のＭＯ８型トランジスタの
断面図、第３図（＆）〜（ｃ）は本発明の他の実施例に
係るＳＯＳ 構造のＭＯ８型トランソスタを製造工程順
に示す断面図、第４図〜第６図は夫々本発明に係る４電
層の他の配置の例を示す断面図である。
２ノ・・・サファイア、２２ 、３２ 、３２’ 、４
２．。
５１．６１・・・高融点金属層、２３・・・多結晶シリ
コン層、２４．４１．４３・・・シリコン層、２５・・
・Ｎ＋型のソース領域、２６・・・Ｎ＋型のドレイン領
域、２７・・・チャネル領域を形成するシリコン層、２
９・・・ゲート電極、３１．５２・・・溝。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図FIG. 1(,) to (d) show SO3 according to an embodiment of the present invention.
2 is a cross-sectional view of an MO8-type transistor with a conventional SO8 structure, and FIGS. 3 (&) to (c) are cross-sectional views of an MO8-type transistor according to another embodiment of the present invention. FIGS. 4 to 6 are cross-sectional views showing an MO8-type transistor having a structure in the order of manufacturing steps, and FIGS. 4 to 6 are cross-sectional views showing other examples of arrangement of four electric layers according to the present invention, respectively. 2 No... Sapphire, 22, 32, 32', 4
2. . 51.61... High melting point metal layer, 23... Polycrystalline silicon layer, 24.41.43... Silicon layer, 25...
・N+ type source region, 26... N+ type drain region, 27... silicon layer forming a channel region, 2
9...Gate electrode, 31.52...Groove. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2
Claims (1)
イン領域を有する島状の半導体層と、前記ソース、ドレ
イン領域間のチャネル領域上にゲート酸化膜を介して設
けられたゲート電極と、前記ソース領域とソース、ドレ
イン領域を除く半導体層にまたがって形成された導電層
とを具備することを特徴とする半導体装置。an insulating substrate, an island-shaped semiconductor layer provided on the substrate and having source and drain regions, a gate electrode provided on the channel region between the source and drain regions via a gate oxide film, and the A semiconductor device comprising a source region and a conductive layer formed across a semiconductor layer excluding the source and drain regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21991284A JPS6197964A (en) | 1984-10-19 | 1984-10-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21991284A JPS6197964A (en) | 1984-10-19 | 1984-10-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6197964A true JPS6197964A (en) | 1986-05-16 |
Family
ID=16742964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21991284A Pending JPS6197964A (en) | 1984-10-19 | 1984-10-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6197964A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0405063A2 (en) * | 1989-04-29 | 1991-01-02 | Fujitsu Limited | An insulated-gate fet on an soi-structure |
| US4984041A (en) * | 1989-07-28 | 1991-01-08 | Xerox Corporation | High voltage thin film transistor with second control electrode |
| US4984040A (en) * | 1989-06-15 | 1991-01-08 | Xerox Corporation | High voltage thin film transistor with second gate |
| US5264721A (en) * | 1989-04-29 | 1993-11-23 | Fujitsu Limited | Insulated-gate FET on an SOI-structure |
| US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
| US5428234A (en) * | 1992-07-20 | 1995-06-27 | Sony Corporation | Semiconductor device |
| US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
| EP1287563A1 (en) * | 2000-05-16 | 2003-03-05 | Infineon Technologies AG | Field effect transistor and method for producing a field effect transistor |
-
1984
- 1984-10-19 JP JP21991284A patent/JPS6197964A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
| US5565697A (en) * | 1988-06-28 | 1996-10-15 | Ricoh Company, Ltd. | Semiconductor structure having island forming grooves |
| EP0405063A2 (en) * | 1989-04-29 | 1991-01-02 | Fujitsu Limited | An insulated-gate fet on an soi-structure |
| US5264721A (en) * | 1989-04-29 | 1993-11-23 | Fujitsu Limited | Insulated-gate FET on an SOI-structure |
| US4984040A (en) * | 1989-06-15 | 1991-01-08 | Xerox Corporation | High voltage thin film transistor with second gate |
| US4984041A (en) * | 1989-07-28 | 1991-01-08 | Xerox Corporation | High voltage thin film transistor with second control electrode |
| US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
| US5428234A (en) * | 1992-07-20 | 1995-06-27 | Sony Corporation | Semiconductor device |
| EP1287563A1 (en) * | 2000-05-16 | 2003-03-05 | Infineon Technologies AG | Field effect transistor and method for producing a field effect transistor |
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