JPS6197768A - Memory address system - Google Patents

Abstract

PURPOSE:To offer a memory address system which can transfer data in a short time by adding the said system with a line address control circuit and a circuit which can specify a value Y of two-dimensional data to be shifted from the 1st memory to the 2nd one through a CPU. CONSTITUTION:Before the CPU5 gives to an address control circuit 3' an activating signal for transferring data from the 1st memory to the 2nd one, it supplies to the address control circuit 3' the address basic signal D of an address signal B which the address control circuit 3; transmits t the 1st memory and values L of X and Y of two-dimensional data to be shifted from the 1st memory to the 2nd one, and further supplies to a line address J which is necessary to transfer data from the 1st memory to the 2nd one. Here, when the CPU5 gives the activating signal for transferring data, data of one line in the X direction in the 1st memory is completely transferred.

Description

【発明の詳細な説明】 本発明は、情報処理ンステム等の出力装置として使用さ
れる印刷装置あるいは表示装ｊ＃等（以下印刷装置と称
す）のメそリアドレス本式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a main address system for a printing device or a display device (hereinafter referred to as a printing device) used as an output device of an information processing system or the like.

第１図はこの種の印刷装置等における従来のメモリアド
レス方式の構成を示すブロック図で、１は第１メモリ、
２は第２メモリ、３及び４はアドレス制御回路、６は中
央処理装置（以下０ＰＵＩ称す）である。FIG. 1 is a block diagram showing the configuration of a conventional memory addressing method in this type of printing device, etc., in which 1 is a first memory;
2 is a second memory, 3 and 4 are address control circuits, and 6 is a central processing unit (hereinafter referred to as 0PUI).

０ＰＵ５はアドレス制御回路３へ２次元のデータのＸＯ
値人と、アドレス制御回路３からアドレス信号Ｂｉ出力
させるためのアドレス基本信号りと、起動信号Ｐと、終
了指示信号Ｇｔ−送出し、他方アドレス制御回路４へ、
アドレス信号０金出力させるためのアドレス基本信号Ｅ
を送出する。0PU5 is the XO of two-dimensional data to the address control circuit 3.
A basic address signal for outputting an address signal Bi from the address control circuit 3, a start signal P, and a termination instruction signal Gt, to the other address control circuit 4.
Address basic signal E for outputting address signal 0 gold
Send out.

なお、アドレス制御回路８はアドレス制御回路４に含ま
せても差し支えないが、ここでは理解を容易にする几め
アドレス制御回路３とアト１／ス制御回路４を独立して
茨示した。Although the address control circuit 8 may be included in the address control circuit 4, the refined address control circuit 3 and the address control circuit 4 are shown separately here for ease of understanding.

さて、Ｗ、１メモリ１から第２メモリ２ヘデータを転送
させる起動信号Ｖをアドレス制御回路３が０ＰＵ５から
受けると、アドレス制御回路３はＸ方向のデータ転送が
終了するとその終了指示信号Ｇｔ−ＯＰＵ５へ送出する
。Now, when the address control circuit 3 receives the activation signal V from 0PU5 to transfer data from the W, 1 memory 1 to the second memory 2, the address control circuit 3 receives the termination instruction signal Gt-OPU5 when the data transfer in the X direction is completed. Send to.

この従来方式は０ＰＵ５が終了指示信号Ｇに基づいて第
２メモリ２の次のＹ方向の起点となるアドレス基本信号
Ｅｆ：与えなければならずアドレス制御回路４へ終了指
示信号Ｇが与えられるごとに次のＹ方向の起点となるア
ドレス基本信号１ｉｌｔ−計算する必要があり膨大な時
間がかかるという欠点があった。In this conventional method, 0PU5 has to give an address basic signal Ef which becomes the next Y-direction starting point of the second memory 2 based on the end instruction signal G, and every time the end instruction signal G is given to the address control circuit 4. There is a drawback that it is necessary to calculate the address basic signal 1ilt, which is the starting point of the next Y direction, and it takes an enormous amount of time.

そこで本発明は第１メモリから第２メモリへデータを転
送するのに多大な時間を要することなく転送させること
のできるメモリアドレス方式を提供しようとするもので
ある。Therefore, the present invention aims to provide a memory addressing system that allows data to be transferred from a first memory to a second memory without requiring a large amount of time.

即ち、本発明は鮮１と第２の２つのメモリと、前記第１
メモリに記憶した横方向Ｘ１縦方向Ｙの２次元の内容を
もったデータを前記第２メモリに移すためのアドレス制
御回路と、中央処理装置とを備え、該中央処理装置は前
記第１メモリから、移すべき前記２次元のデータの起点
のアドレスとＸ、Ｙの値と嬉２メモリ中に移すべきエリ
アの起点のアドレスとをアドレス制御回路に指示し、前
記アドレス制御回路はその指示によって横方向のＸの大
きざのデータを読出して第２メモリへ移すと共にＹ方向
のアドレスをアップ又はダウンするととを特徴とするメ
モリアドレス方式で、以下本発明の実施例について図面
に基づき説明すれば次の通りである。That is, the present invention includes two memories, the first and second memories, and the first memory.
The central processing unit includes an address control circuit for transferring data having two-dimensional contents in the horizontal direction X and vertical direction Y stored in the memory to the second memory, and the central processing unit transfers data from the first memory to the second memory. , the address of the starting point of the two-dimensional data to be transferred, the values of X and Y, and the address of the starting point of the area to be transferred into the second memory are instructed to the address control circuit, and the address control circuit moves in the horizontal direction according to the instructions. This is a memory addressing method characterized by reading the data of the size of X and moving it to the second memory, and also raising or lowering the address in the Y direction.Examples of the present invention will be described below based on the drawings as follows. That's right.

第２図は本発明の一実施例のブロック図で、１．２，４
．５は第１図に示した従来回路で、６が本発明にニジｇ
Ｔ友に追加したラインアドレス制御回路である。ライン
アドレス制御回路６がアドレス制御回路４の中に含まれ
ても差し支えないが。FIG. 2 is a block diagram of an embodiment of the present invention.
．． 5 is the conventional circuit shown in FIG. 1, and 6 is the conventional circuit shown in FIG.
This is a line address control circuit added to T-Friend. There is no problem even if the line address control circuit 6 is included in the address control circuit 4.

ここでは説明の便宜上ラインアドレス制御回路６を独立
して衣示した。Here, for convenience of explanation, the line address control circuit 6 is shown separately.

図中３′はアドレス制御回路で、このアドレス制御回路
３′はアドレス制御回路３に第１メモリ１から第２メモ
リ２へ移すべき２次元のデータのＹの値’１ｃＰＵ５か
ら指示できる回路を追加し皮ものである。In the figure, 3' is an address control circuit, and this address control circuit 3' adds a circuit to the address control circuit 3 that can give instructions from the Y value '1cPU5 of the two-dimensional data to be transferred from the first memory 1 to the second memory 2. It's a skinny thing.

さて、ＣＰｔＪ５ｔ’！第１メモリ１から第２メモリ２
ヘデータを転送させる起動信号Ｆｉアドレス制御回路３
′へ与える前にアドレス制御回路３′ヘアドレス制御回
路３′が第１メモリ１へ送出するアドレス信号Ｂのアド
レス基本信号りと第１メモリ１から第２メモリ２へ移す
べき２次元のデータのＸ。Well, CPtJ5t'! 1st memory 1 to 2nd memory 2
Activation signal for transferring data to Fi address control circuit 3
The address basic signal of the address signal B sent by the address control circuit 3' to the first memory 1 and the two-dimensional data to be transferred from the first memory 1 to the second memory 2 are X.

Ｙ１２）［Ｌとを与え、またライ／アドレス制御回路６
ヘアドレス基本信号Ｈと第１メモリ１から第２メモリ２
ヘデータを転送するときに必要な２イ／アドレスＪｔ−
与える。Y12) [L] and also the write/address control circuit 6
Hair address basic signal H and first memory 1 to second memory 2
2/Address Jt- required when transferring data to
give.

ここで０ＰＵ５が第１メモリ１からｆＪ２メモリ２ヘデ
ータを転送させる起動信号Ｖｆ与えると、第１メモリ１
のＸ方向の１行分の転送が終了すると、終了指示信号Ｇ
がアドレス制御回路３′からラインアドレス制御回路６
へ与えられる。Here, when 0PU5 gives a start signal Vf to transfer data from first memory 1 to fJ2 memory 2, first memory 1
When the transfer of one line in the X direction is completed, the end instruction signal G
is from the address control circuit 3' to the line address control circuit 6.
given to.

そしてラインアドレス制御回路６は第１メモリ１めＸ方
向の１行分が転送終了して得られる終了指示信号Ｇを受
けて第２メモリ２０次に必要なＹ方向のアドレス信号ｔ
−例えば第３図のよりな「あ」という文字を第１メモリ
１から第２メモリ２へ転送する場合、第１メモリ１から
Ｘ、Ｙの＋方向にデータを読んできて第２メモリ２へ同
様ＫＸ、Ｙの＋方向へ転送されなければならない几めに
、アドレス基本信号Ｈｔ−受けて発生し７’ｃＹ方向起
点アドレス信号に檜−らラインアドレス信号Ｊを７１０
算して次に必要なＹ方向起点アドレス信号Ｋｔ−発生さ
せるよう制御しているので０ＰＵ５は最初にアドレス制
御回路３′へは第１メモリ１から第２メモリ２へ移すべ
き２次元のデータのＸ、Ｙの値と、アドレス制＃回路３
′が第１メモリ１へ送出するアドレス信号Ｂのアドレス
基本信号Ｄｔ−アトｌ／ス制御回路３′に与える。一方
ラインアドレス制御回路６へはアドレス基本信号Ｈと第
１メモリ１から第２メモリ２ヘデータを転送するときに
必要なラインアドレスＪ’を与え、次にアドレス制御回
路３′へ第１メモリ１から第２メモリ２ヘデータを転送
させる起動信号Ｆｔ−与えるだけで、第１メモリ１から
第２メモリ２へ第１メモリ１のデータのＸ、Ｙの値に等
しいデータが転送される。Then, the line address control circuit 6 receives an end instruction signal G obtained when the transfer of one row in the X direction of the first memory 1 is completed, and sends a necessary address signal t in the Y direction to the second memory 20.
-For example, when transferring the character ``A'' shown in Figure 3 from the first memory 1 to the second memory 2, the data is read from the first memory 1 in the + direction of X and Y, and then transferred to the second memory 2. Similarly, in order to have to be transferred in the + direction of KX and Y, the line address signal J from Hinoki is generated in response to the address basic signal Ht- and is generated from 7'c as the starting point address signal in the Y direction.
Since the 0PU5 is controlled to calculate and generate the next necessary Y-direction starting point address signal Kt-, the 0PU5 first inputs the two-dimensional data to be transferred from the first memory 1 to the second memory 2 to the address control circuit 3'. X, Y values and address system #circuit 3
' is applied to the address basic signal Dt-atl/s control circuit 3' of the address signal B sent to the first memory 1. On the other hand, the line address control circuit 6 is given the basic address signal H and the line address J' necessary for transferring data from the first memory 1 to the second memory 2, and then the address control circuit 3' is given the basic address signal H and the line address J' necessary for transferring data from the first memory 1 to the second memory 2. Data equal to the X and Y values of the data in the first memory 1 is transferred from the first memory 1 to the second memory 2 by simply applying the activation signal Ft- to transfer data to the second memory 2.

以上の説明はＹ方向起点アドレス信号Ｋからラインアド
レス信号Ｊを加算している例について述べているがこの
逆に減算して用いることも可能である。The above description has been made regarding an example in which the line address signal J is added to the Y-direction starting point address signal K, but it is also possible to subtract it from the Y-direction starting point address signal K.

本発明は以上説明し几ようにラインアドレス制御回路３
′と第１メモリ１から第２メモリ２へ移すべき２次元の
データのＹの値ｔ−０ＰＵ５から指示できる回路を付加
するだけでその実用比が容易で、１工学的に優れたもの
である。As explained above, the present invention provides line address control circuit 3.
' and the Y value t-0PU5 of the two-dimensional data to be transferred from the first memory 1 to the second memory 2.It is easy to put it into practical use by simply adding a circuit, which is excellent in terms of engineering. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来装置のブロック図、第２図は本発明実施例
のブロック図、第３図は第１メモリ１のデータｒ６Ｊｔ
−第２メモリ２へ転送した図で田）はアドレス制御回路
のゾ２ス方向ｔ′民わす。 １・・・第１メモリ、２・・・第２メモリ、３．３’及
び４・・・アドレス制御回路、５・・・中央処理装貨、
６・・・ラインアドレス制御回路。FIG. 1 is a block diagram of a conventional device, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is data r6Jt of the first memory 1.
- In the figure transferred to the second memory 2, the address control circuit is transferred to the second direction t'. DESCRIPTION OF SYMBOLS 1... First memory, 2... Second memory, 3.3' and 4... Address control circuit, 5... Central processing unit,
6...Line address control circuit.

Claims (1)

【特許請求の範囲】[Claims] 第１と第２の２つのメモリと、前記第１メモリに記憶し
た横方向Ｘ、縦方向Ｙの２次元の内容をもつたデータを
前記第２メモリに移すためのアドレス制御回路と、中央
処理装置とを備え、該中央処理装置は前記第１メモリか
ら移すべき前記２次元のデータの起点のアドレスとＸ、
Ｙの値と第２メモリ中に移すべきエリアの起点のアドレ
スとをアドレス制御回路に指示し、前記アドレス制御回
路はその指示によつて横方向のＸの大きさのデータを読
出して第２メモリへ移すと共にＹ方向のアドレスをアッ
プ又はダウンすることを特徴とするメモリアドレス方式
。two memories, a first and a second memory; an address control circuit for transferring data having two-dimensional content in the horizontal direction X and vertical direction Y stored in the first memory to the second memory; and a central processing unit. an address of the starting point of the two-dimensional data to be transferred from the first memory;
The value of Y and the address of the starting point of the area to be transferred into the second memory are instructed to the address control circuit, and the address control circuit reads out the data of the size of X in the horizontal direction according to the instructions, and transfers the data to the second memory. A memory addressing method characterized by moving the address up or down in the Y direction at the same time.