JPS6189621A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6189621A JPS6189621A JP59211703A JP21170384A JPS6189621A JP S6189621 A JPS6189621 A JP S6189621A JP 59211703 A JP59211703 A JP 59211703A JP 21170384 A JP21170384 A JP 21170384A JP S6189621 A JPS6189621 A JP S6189621A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thickness
- silicon nitride
- island
- lpcvd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000013078 crystal Substances 0.000 claims abstract description 16
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 16
- 238000009826 distribution Methods 0.000 description 7
- 238000002425 crystallisation Methods 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法、詳しくは窓を開けた反
射防止膜を用い、レーザ照射により単結晶化過程で要求
される温度分布をアイランド状に形成し単結晶領域を作
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a semiconductor device manufacturing method, using an anti-reflection film with an open window, the temperature distribution required in the single crystallization process is controlled by laser irradiation. This invention relates to a method of forming a single crystal region into a single crystal region.
非晶質絶縁層上の非単結晶半導体膜（シリコン・オン・
インシュレータ、ＳＯＩ ）を単結晶化するために、反
射防止膜を利用する技術がある。これは、非単結晶半導
体股上にストライプ状の反射防止膜をパターニングして
おき、パターンに沿ってレーザ光をスキャニングしてレ
ーザ光の半導体膜中への吸収量を制御して、単結晶化過
程で要求される温度分布を半導体膜中に形成するもので
ある。Non-single crystal semiconductor film (silicon on silicon) on an amorphous insulating layer
There is a technique that uses an anti-reflection film to make an insulator (SOI) into a single crystal. This process involves patterning a striped anti-reflection film on a non-single-crystal semiconductor, scanning laser light along the pattern, and controlling the amount of laser light absorbed into the semiconductor film during the single-crystalization process. This is to form the temperature distribution required in the semiconductor film.
第４図（ａ）の平面図とそのＢ−Ｂ線に沿う（ｂｌの断
面図を参照すると、２１は非晶質絶縁層、２２は再結晶
化すべき多結晶シリコン（ポリシリコン）またはアモル
ファスシリコン膜、２３はストライプ状のシリコン窒化
１１Ｑ （Ｓｉ、ＩＮｑ ）膜（反射防止膜）を示す。Referring to the plan view of FIG. 4(a) and its cross-sectional view along line B-B (bl), 21 is an amorphous insulating layer, 22 is polycrystalline silicon (polysilicon) or amorphous silicon to be recrystallized. The film 23 is a striped silicon nitride 11Q (Si, INq) film (antireflection film).
ここで、シリコン窒化膜３相互間の間隔よりも大なるス
ボ・ノド径のアルゴンレーザ（Ａｒ ＪｏｎＬａ５ｅｒ
＋波長４８８０人および５４６０人を主波長成分とする
）を照射すると、反射防止膜の形成されていない部分で
のレーザ光エネルギーの反射率は３５％、シリコン窒化
膜の下では５０％程度であり、第４図（ｂ）に示す構造
においては同図（Ｃ１に示される＆変分布が得られる。Here, an argon laser (Argon laser) with a diameter larger than the interval between the silicon nitride films 3 is used.
+ wavelengths of 4880 and 5460), the reflectance of the laser light energy is 35% in the area where the anti-reflection film is not formed, and about 50% under the silicon nitride film. , in the structure shown in FIG. 4(b), the &variant distribution shown in FIG. 4(C1) is obtained.
同図で縦軸Ｔは温度を、横軸はポリシリコン股のす伯を
示すが、シリコン窒化ｊ模２３の間の中間点でポリシリ
コン膜は温度が最も低く、そごが最初に冷却して再結晶
化し小結晶ノリコンとなり、シリコン窒化膜の下には結
晶粒界が発生する。In the same figure, the vertical axis T shows the temperature, and the horizontal axis shows the thickness of the polysilicon film.The temperature of the polysilicon film is the lowest at the midpoint between the silicon nitride films and the film cools down first. The silicon nitride film recrystallizes to become small crystalline silicon, and crystal grain boundaries are generated under the silicon nitride film.
その結果、第４図（ａ）に符号２４で示すシートから核
成長か始まり、それはレーザ光が同図に見て上方に進む
につれて上方に引きずられて行く。同図の曲線２５はか
かる核成長の拡がりを模式的に示すものである。As a result, nucleus growth begins from the sheet shown at 24 in FIG. 4(a), which is dragged upward as the laser beam advances upward as seen in the figure. A curve 25 in the figure schematically shows the spread of such nuclear growth.
（発明かＩＷ決しようとする問題点）
上記した非単結晶半導体膜の単結晶化において、素子形
成領域２６ａ（第４図（ａ））が反射防止膜の存在しな
い部分にあると、同領域は単結晶化されるので特に問題
はないが、素子形成領域が２６ｂで示されるように反射
防止膜の下の部分を含むものであるときには、そこにグ
レインが存在して素子を形成するに適しない。すなわち
、上記例において：よ、素子形成領域がストライブ状の
反射防止膜の１田に位置しなければならないという回路
設計上の制約か加わる問題がある。(Problems to be resolved by the invention or IW) In the single crystallization of the non-single crystal semiconductor film described above, if the element formation region 26a (FIG. 4(a)) is located in a portion where no antireflection film exists, the same region There is no particular problem since it is single-crystalized, but when the element formation region includes a portion under the antireflection film as shown by 26b, grains are present there and it is not suitable for forming an element. That is, in the above example, there is an additional problem in that the element formation region must be located in one area of the striped antireflection film, which is a restriction on circuit design.
本発明は上記問題点を解決した半導体装置の製造方法を
提供するもので、その手段は、非晶質絶縁層上の非単結
晶半導体膜を単結晶化する方法において、非単結晶″−
１４導体股上にエネルギービームの反射防止膜を形成し
、該反射防止膜に窓を開け、しかる後に前記窓を通して
エネルギービームを照射し前記領域の非す１結晶半導体
を小結晶化することを特徴とする半導体装置の製造方法
によってなされる。The present invention provides a method for manufacturing a semiconductor device that solves the above-mentioned problems.
14, forming an energy beam anti-reflection film on the crotch of the conductor, opening a window in the anti-reflection film, and then irradiating the energy beam through the window to crystallize the non-single-crystalline semiconductor in the region. This is accomplished by a method of manufacturing a semiconductor device.
上記方法においては、反射防止膜に窓をあけ、単結晶化
過程で要求される温度分布をアイラン］・状に形成し、
直接アイランド形状の単結晶化領域を作るものである。In the above method, a window is opened in the anti-reflection film and the temperature distribution required in the single crystallization process is formed in the shape of an island.
This method directly creates an island-shaped single crystal region.
従って、単結晶化しようとするアイランド領域が反射防
止膜に形成する窓の配置、形状および大きさに一致して
形成できるので、自由度の高いＬＳＩ設計が可能となる
。Therefore, the island region to be single-crystalized can be formed in accordance with the arrangement, shape, and size of the window formed in the antireflection film, making it possible to design an LSI with a high degree of freedom.
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
本発明実施例は第１図（ａｌの平面図と同図のＢ−Ｂ線
に沿う拡大断面を示す（ｂｌの断面図に示され、Ｌａ、
、、 ｌｅは反射防止膜２に形成された窓を示す。Embodiments of the present invention are shown in FIG.
,, le indicates a window formed in the antireflection film 2.
第１図ｆｂｌの断面図を参照すると、シリコンウェハ３
に熱酸化により１μｍのｊ漢ｊ￥の５ｉＯｚ ｌｌ臭４
を形成し、その上にシリコン窒化膜５を減圧化学気相成
長法（ＬＰＣＶＤ法）で１０００人のｊ膜厚に成長し、
その」−に再結晶化すべきポリシリコン膜６をＬＰＣＶ
Ｄ法で４０００人のｊ膜厚に成長し、その上に５ｉ０２
膜７を３００人の膜厚に熱酸化により形成し、その上に
シリコン窒化膜８をＬ Ｐ ＣＶ Ｄ法で３００人の膜
厚に成長する。従って、 ５ｉＯ２１１梁７とシリコン
窒化１１Ｑ ８とで第１図ｆａ）の反射防止膜２が構成
される。Referring to the cross-sectional view of FIG. 1 fbl, the silicon wafer 3
5iOz ll odor of 1μm by thermal oxidation 4
A silicon nitride film 5 is grown thereon to a thickness of 1000 nm by low pressure chemical vapor deposition (LPCVD),
LPCV the polysilicon film 6 to be recrystallized.
Grow to a film thickness of 4000 μm using the D method, and add 5i02 on top of it.
A film 7 is formed to a thickness of 300 nm by thermal oxidation, and a silicon nitride film 8 is grown thereon to a thickness of 300 nm by the LPCCVD method. Therefore, the 5iO211 beam 7 and the silicon nitride 11Q 8 constitute the antireflection film 2 shown in FIG. 1fa).
第１図ｔａ＋の実施例は、反射防止膜が従来例の如くス
トライブ状に形成されるものでな（、ウェハ全面上に形
成された反射防止膜に、所望の素子形成領域に対応した
アイランド状の窓を作り、これらの窓領域のポリシリコ
ンを結晶粒界な（再結晶化するものである。In the embodiment shown in FIG. 1 ta+, the anti-reflection film is not formed in a stripe shape as in the conventional example. The process involves creating windows with shapes and recrystallizing the polysilicon in these window areas at grain boundaries.
単結晶化には、例えばＧＷ （連続波）のＡｒレーザ（
パワーは８〜１４Ｗ）を用い、スキャンスピードは１〜
５μｍ／ｓｅａとし、シリコンウェハ３は４５０°Ｃに
加熱し空気中でスキャンする。スキャンはレーザ光源を
固定しウェハを動かしてなしたが、逆になすことも可能
である。すだ、再結晶化に用いるエネルギー源はレーザ
光に限定されるものではなく、その他のエネルギービー
ムも用いうる。For single crystallization, for example, a GW (continuous wave) Ar laser (
Power is 8~14W), scan speed is 1~
5 μm/sea, and the silicon wafer 3 is heated to 450° C. and scanned in air. Scanning was performed by fixing the laser light source and moving the wafer, but it is also possible to do the opposite. However, the energy source used for recrystallization is not limited to laser light, and other energy beams may also be used.
第２図ｔａ＞の平面図には第１図のア・イラントの１つ
１ａのみが示されるが、このアイランドにおけるレーザ
光照射後の温度分布は同図（ｂｌと（Ｃ）に示ず如くで
ある。なお、同図ｆｂ）、（Ｃ１の線図において、符号
Ｔを付した軸は温度を、その軸に直交する軸はアイラン
ドの幅を示す。すなわち、アイランドの中心部分が最も
低温で、アイランドの周辺に近つくにつれて温度が高く
なる６１に四分布が得られる。The plan view in Figure 2 (ta) shows only one of the island 1a in Figure 1, but the temperature distribution after laser beam irradiation on this island is as shown in the same figure (bl and (C)). In the diagram fb in the same figure, (C1), the axis with the symbol T indicates the temperature, and the axis perpendicular to that axis indicates the width of the island.In other words, the center part of the island is the lowest temperature. , a four-dimensional distribution is obtained in which the temperature increases as it approaches the periphery of the island.
従って、固化過十二ａでの核成長はアイランドの中心に
できるシード９を基点に始まりまわりに曲線１０に示す
如く拡がってアイランド形状の単結晶化領域が形成され
、その過■♀においてはダレインハウンダリーの発生は
全くないので、単結晶化か良好に進行する。Therefore, the nucleus growth in the solidified over-12a starts from the seed 9 formed at the center of the island and spreads around it as shown by the curve 10, forming an island-shaped single crystal region, and in the over-solidification, there is no sag. Since no inhoundry occurs, single crystallization progresses well.
レーザ光の照射方法を第３図の模式的平面図を参照して
説明すると、レーザ光のスポット径がＴであるとき、レ
ーザ光のスキャン方向く図に矢印Ｉで示す）に対して直
角方向のアイランドｉｆ、、、。The laser beam irradiation method will be explained with reference to the schematic plan view in Fig. 3. When the laser beam spot diameter is T, the direction perpendicular to the scanning direction of the laser beam (indicated by arrow I in the figure) is as follows. Island if...
１１の横方開拡がり ｔ （ｆ 、、、ｉ）は、 ｔ
（ｆ 、、、ｉ）くＴであることが必要で、レーザ光は
、スポットを部分的に重ねて（オーバーランプさせて）
照射する。The lateral spread t (f,,,i) of 11 is t
(f,,,i) It is necessary that the laser beam is partially overlapped (overlamped)
irradiate.
以上説明したように本発明によれば、窓を開けた反射防
止膜を用いてレーザ光照射によりアイランド形状の単結
晶領域を絶縁層上の非単結晶半導体膜に形成することが
できるので、ＬＳＩの設計の自由度を高めるに効果大で
ある。なお、ＳＯＩの再結晶化にはレーザ光のみならず
その他のエネルギービームを使用しうるちのであり、本
発明の適用範囲は上記した数値に制限されるものでない
。As explained above, according to the present invention, an island-shaped single crystal region can be formed in a non-single crystal semiconductor film on an insulating layer by laser beam irradiation using an antireflection film with an open window. This is highly effective in increasing the degree of freedom in design. Note that not only laser light but also other energy beams can be used for recrystallization of SOI, and the scope of application of the present invention is not limited to the above-mentioned values.
第１図（ａ）は本発明の方法を実施する工程における半
導体装置要部の平面図、同図（ｂ）はその（ａ）におけ
るＢ−Ｂ線に沿う拡大断面図、第２図（ａｌは第１図＋
ａ）のアイランド領域の１つの平面図、同図（ｂ）と（
Ｃ１はアイランドの温度分布を示す線図、第３図はレー
ザ光照射方法を示すための第１図のアイランド領域の平
面図、第４図（ａ）は従来方法を示す半導体装置要部の
平面図、同図ｆｂ）はその（ａ）におけるＢ−Ｂ線に沿
う断面図である。
図中、１ａ、、、ｌｉはアイランド、２は反射防止１模
、３はシリコンウェハ、４と７は５ｒ０２膜、５ト８は
シリコン窒化膜、６はポリシリコン膜、をそれぞれ示す
。
特 許 出願人 富士通株式会’；ｉ７．ｒ代理人
弁理士 松 岡 宏四負町ぐ」、１第１図
第２図
（ａ） （ｃ）
第３図
＋７FIG. 1(a) is a plan view of the main part of a semiconductor device in the step of carrying out the method of the present invention, FIG. 1(b) is an enlarged sectional view taken along line B-B in FIG. is Figure 1 +
A plan view of one of the island regions in a), (b) and (
C1 is a diagram showing the temperature distribution of the island, FIG. 3 is a plan view of the island region in FIG. 1 to show the laser beam irradiation method, and FIG. 4(a) is a plan view of the main part of the semiconductor device showing the conventional method. Figure fb) is a sectional view taken along line B-B in (a). In the figure, 1a, . . . li are islands, 2 is an anti-reflection model 1, 3 is a silicon wafer, 4 and 7 are 5R02 films, 5 and 8 are silicon nitride films, and 6 is a polysilicon film, respectively. Patent applicant: Fujitsu Limited; i7. r agent
Patent Attorney Hiroshi Matsuoka, 1 Figure 1 Figure 2 (a) (c) Figure 3 +7
Claims (1)
ネルギービームの反射防止膜を形成し、該反射防止膜に
窓を開け、しかる後に前記窓を有する反射防止膜を通し
てエネルギービームを照射し前記窓領域内の非単結晶半
導体を結晶粒界なく再結晶化することを特徴とする半導
体装置の製造方法。Forming an energy beam antireflection film on a non-single crystal semiconductor film formed on an amorphous insulating layer, opening a window in the antireflection film, and then irradiating an energy beam through the antireflection film having the window. A method of manufacturing a semiconductor device, characterized in that the non-single crystal semiconductor within the window region is recrystallized without grain boundaries.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59211703A JPS6189621A (en) | 1984-10-09 | 1984-10-09 | Manufacture of semiconductor device |
| EP85111301A EP0178447B1 (en) | 1984-10-09 | 1985-09-06 | A manufacturing method of an integrated circuit based on semiconductor-on-insulator technology |
| DE8585111301T DE3587100T2 (en) | 1984-10-09 | 1985-09-06 | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT BASED ON THE SEMICONDUCTOR ON ISOLATOR TECHNOLOGY. |
| KR1019850007151A KR900000561B1 (en) | 1984-10-09 | 1985-09-27 | Manufacturing method of an ic and device |
| US07/513,045 US5077233A (en) | 1984-10-09 | 1990-04-23 | Method for recrystallizing specified portions of a non-crystalline semiconductor material to fabricate a semiconductor device therein |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59211703A JPS6189621A (en) | 1984-10-09 | 1984-10-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6189621A true JPS6189621A (en) | 1986-05-07 |
Family
ID=16610188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59211703A Pending JPS6189621A (en) | 1984-10-09 | 1984-10-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6189621A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168980B1 (en) | 1992-08-27 | 2001-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5693312A (en) * | 1979-12-26 | 1981-07-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58184720A (en) * | 1982-04-23 | 1983-10-28 | Nec Corp | Manufacture of semiconductor film |
-
1984
- 1984-10-09 JP JP59211703A patent/JPS6189621A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5693312A (en) * | 1979-12-26 | 1981-07-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58184720A (en) * | 1982-04-23 | 1983-10-28 | Nec Corp | Manufacture of semiconductor film |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168980B1 (en) | 1992-08-27 | 2001-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
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