JPS6342417B2 - - Google Patents
Info
- Publication number
- JPS6342417B2 JPS6342417B2 JP56041328A JP4132881A JPS6342417B2 JP S6342417 B2 JPS6342417 B2 JP S6342417B2 JP 56041328 A JP56041328 A JP 56041328A JP 4132881 A JP4132881 A JP 4132881A JP S6342417 B2 JPS6342417 B2 JP S6342417B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- single crystal
- scribe line
- crystal silicon
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims description 51
- 239000013078 crystal Substances 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 23
- 229920005591 polysilicon Polymers 0.000 description 22
- 238000000034 method Methods 0.000 description 21
- 229910004298 SiO 2 Inorganic materials 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 12
- 238000002425 crystallisation Methods 0.000 description 8
- 230000008025 crystallization Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Description
【発明の詳細な説明】
本発明は、３次元化した半導体集積回路の製造
方法、特にレーザーの如きエネルギー線を用いて
絶縁膜上の半導体層を加熱単結晶化する技術を適
用して第２層、第３層…のLSIを製造する方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a three-dimensional semiconductor integrated circuit, in particular, a method for manufacturing a three-dimensional semiconductor integrated circuit by applying a technique of heating a semiconductor layer on an insulating film to single crystallization using an energy beam such as a laser. The present invention relates to a method for manufacturing an LSI with a layer, a third layer, and so on.
２酸化シリコン（SiO2）膜上に成長した多結
晶シリコン（ポリシリコン）またはアモルフアス
（非晶質）シリコンの如き非単結晶シリコンを、
レーザー・アニールの如きエネルギー線を用いる
アニールによつて単結晶化する技術は知られてい
る。かかる試みにおいて、アニール処置を行つて
も、冷却、再結晶化過程で色々な場所から結晶が
成長し始め再び多結晶に戻ることが経験された。
希望されるものは結晶方位の揃つた均一な単結晶
であるから、そのような単結晶を結晶核から育て
ることを本願の発明者は考えた。 Non-single crystal silicon, such as polycrystalline silicon (polysilicon) or amorphous silicon, grown on a silicon dioxide (SiO 2 ) film,
Techniques for single crystallization by annealing using energy beams, such as laser annealing, are known. In such attempts, it was experienced that even if annealing treatment was performed, crystals began to grow from various locations during the cooling and recrystallization process, and the material returned to polycrystalline form.
Since what is desired is a uniform single crystal with uniform crystal orientation, the inventors of the present invention considered growing such a single crystal from a crystal nucleus.
第１図には、このようにして開発されたシリコ
ン基板を結晶核として用いる技術が断面で示され
る。結晶方位１００のシリコン基板１上に、膜厚
ほぼ１〔μm〕のSiO2膜２を形成し、SiO2膜に孔
３を窓開きして形成、全面に約5000〔Å〕のポリ
シリコン層４を例えば化学気相成長法（CVD）
で成長させ、ポリシリコンを基板の結晶方位１０
０の単結晶シリコンと接触させる。この孔３のと
ころ、すなわち単結晶シリコンとポリシリコンと
が接触しているところにレーザー・ビーム５を照
射すると、ポリシリコンは加熱され溶融し、結晶
方位１００の単結晶シリコンがエピタキシヤル成
長する。レーザー・ビーム５を矢印Ａに示す方向
に移動させると、前記エピタキシヤル成長がいわ
ば引張り出されて、ゾーン・メルテイングの如く
結晶方位１００の単結晶シリコンが図に見て右に
拡がる。なお、図において、単結晶シリコンは白
地で、またポリシリコンは砂地で示す。 FIG. 1 shows a cross-sectional view of the technique developed in this way that uses a silicon substrate as a crystal nucleus. A SiO 2 film 2 with a thickness of approximately 1 [μm] is formed on a silicon substrate 1 with a crystal orientation of 100, holes 3 are opened in the SiO 2 film, and a polysilicon layer with a thickness of approximately 5000 [Å] is formed on the entire surface. For example, chemical vapor deposition (CVD)
The crystal orientation of the substrate is 10.
0 single crystal silicon. When a laser beam 5 is irradiated to this hole 3, that is, a place where the single crystal silicon and polysilicon are in contact, the polysilicon is heated and melted, and single crystal silicon having a crystal orientation of 100 is epitaxially grown. When the laser beam 5 is moved in the direction shown by arrow A, the epitaxial growth is pulled out, so that the single crystal silicon with crystal orientation 100 spreads to the right as seen in the figure, as in zone melting. In the figure, single crystal silicon is shown with a white background, and polysilicon is shown with a sandy background.
前記の如くにして形成された単結晶シリコン層
上にLSIを形成する方法で現在までに提案された
３次元LSIを製造しようとすると次の如き困難が
生ずる。即ち最近の集積度向上を要求に応じるた
めには、かかるLSIの上に絶縁膜を成長させ、こ
の絶縁膜上に例えばCVDでポリシリコン層を成
長し、これに前記した単結晶化工程を行ないたい
が、ポリシリコン層の下層の単結晶シリコン層に
は、既に、拡散層、ゲート・ポリシリコン、フイ
ールド酸化膜、上層へのコンタクト、金属配線な
どが形成され、チツプの内部はこれらによつて場
所を占有されているので、通常の場合、上層のポ
リシリコンの単結晶化のための結晶核の場所が存
在しない。 When attempting to manufacture the three-dimensional LSI proposed to date by the method of forming an LSI on the single crystal silicon layer formed as described above, the following difficulties arise. That is, in order to meet recent demands for increased integration, an insulating film is grown on such an LSI, a polysilicon layer is grown on this insulating film by, for example, CVD, and then the single crystallization process described above is performed on this. However, the single crystal silicon layer below the polysilicon layer already has a diffusion layer, gate polysilicon, field oxide film, contacts to the upper layer, metal wiring, etc., and the inside of the chip is affected by these. Since space is occupied, there is usually no place for crystal nuclei for single crystallization of the upper polysilicon layer.
本発明は前記した技術的課題を解決しようとす
るものであり、その目的を実現するためには、単
結晶シリコン基板上のSiO2膜に窓あけされた孔
のところを常に窓開けした状態に保ち、その部分
に単結晶シリコンの柱を形成し、第２層、第３層
…のポリシリコンはこの単結晶シリコンの柱のと
ころからレーザー照射を開始することにより、そ
れぞれの層の下層に形成されたLSIに無関係に上
層のポリシリコンを単結晶化する。更に、このよ
うな単結晶シリコン柱はウエハーのスクライブ・
ラインの部分に形成し、後の工程でウエハーをス
クライブ・ラインに沿つて切断して各チツプを個
別化すると、単結晶シリコン柱を形成することは
なんらウエハー面積の浪費にならない。このよう
なことは、スクライブ・ラインの部分にSiO2が
存在しないようにパターニングすることにより可
能とされるので、本発明の方法においては、ウエ
ハー面の有効利用が実現され、またそのために特
に工程を増やす必要もない。 The present invention aims to solve the above-mentioned technical problem, and in order to achieve the purpose, it is necessary to keep the holes drilled in the SiO 2 film on the single crystal silicon substrate always open. The polysilicon of the second layer, third layer, etc. is formed under each layer by starting laser irradiation from this single crystal silicon pillar. The upper layer polysilicon is made into a single crystal, regardless of the LSI that is made. Furthermore, such single-crystal silicon pillars can be used for wafer scribing and
Forming single-crystal silicon pillars does not waste any wafer area if the wafer is cut along the scribe lines to individualize each chip in a later step. This is possible by patterning so that SiO 2 does not exist in the scribe line portion, so in the method of the present invention, effective use of the wafer surface is realized, and for this purpose, especially in the process. There is no need to increase.
以下、本発明の方法の実施例を添付図面を参照
して説明しよう。 Embodiments of the method of the invention will now be described with reference to the accompanying drawings.
第２図には、本発明の方法を実施するための工
程が断面図で示される。図において、第１図と同
じ部分には同一符号を付ける。結晶方位１００の
単結晶シリコン基板１上に、ほぼ１〔μm〕の膜厚
にSiO2膜２を形成し、このSiO2膜２を通常の技
術でパターニングして孔３を窓開けし、全面にポ
リシリコン第１層を例えばCVDで約5000〔Å〕の
厚さに形成し、このポリシリコン層を第１図を参
照して説明したと同じ方法で単結晶化し、図示の
如くデバイスをもつた第1LSI層４を形成する。
図でn+は高濃度ｎ形不純物拡散層、p-は低濃度
ｐ形不純物拡散層、６はポリシリコン・ゲート・
電極、７はゲート酸化膜、８は選択酸化によつて
形成された酸化膜をそれぞれ示す。 FIG. 2 shows a cross-sectional view of the steps for carrying out the method of the invention. In the figure, the same parts as in FIG. 1 are given the same reference numerals. A SiO 2 film 2 with a thickness of approximately 1 μm is formed on a single-crystal silicon substrate 1 with a crystal orientation of 100, and this SiO 2 film 2 is patterned using a conventional technique to open holes 3 to cover the entire surface. A first layer of polysilicon is formed to a thickness of about 5000 Å by, for example, CVD, and this polysilicon layer is made into a single crystal by the same method as explained with reference to FIG. 1 to form a device as shown in the figure. A first LSI layer 4 is then formed.
In the figure, n + is a high concentration n-type impurity diffusion layer, p - is a low concentration p-type impurity diffusion layer, and 6 is a polysilicon gate.
Reference numeral 7 indicates an electrode, a gate oxide film, and 8 an oxide film formed by selective oxidation.
次に、全面に層間絶縁膜９を約１〔μm〕の膜厚
に例えば二酸化シリコン（SiO2）を気相成長法
を用いて形成する。この絶縁膜の孔３の上方部分
３′とその他層間コンタクトを形成する部分１０
には通常の技術でパターニングして窓開けし、し
かる後に再度5000〔Å〕の膜厚にポリシリコン第
２層を形成する。第１図を参照して説明したと同
じ方法で孔３の上方部分３′のところからレーザ
ー照射を始めると、孔３を埋めた結晶方位１００
の単結晶シリコン上には、あたかも柱の如く結晶
方位１００の単結晶シリコンが形成され、続いて
ポリシリコン第２層はこの単結晶シリコン部を核
として単結晶化される。 Next, an interlayer insulating film 9 of approximately 1 μm thick is formed on the entire surface using, for example, silicon dioxide (SiO 2 ) by vapor phase growth. The upper part 3' of this insulating film hole 3 and the other part 10 forming an interlayer contact.
Then, a window is formed by patterning using conventional techniques, and then a second polysilicon layer is formed again to a thickness of 5000 Å. When laser irradiation is started from the upper part 3' of the hole 3 in the same manner as explained with reference to FIG.
Single crystal silicon having a crystal orientation of 100 is formed on the single crystal silicon as if it were a pillar, and then the second polysilicon layer is single crystallized using this single crystal silicon portion as a nucleus.
引続き、この第２層の単結晶シリコン上に前記
したと同様の方法で図示される如きデバイスを形
成すると、第2LSI層４′が完成する。 Subsequently, a device as shown in the figure is formed on this second layer of single crystal silicon in the same manner as described above, thereby completing the second LSI layer 4'.
再び全面に１〔μm〕の膜厚の層間絶縁膜９を形
成し、以上に説明したと同じ工程を繰り返す。図
において、ポリシリコン第３層は第１図の場合の
如く単結晶化されつつある状態で示され、第１図
と同じ部分には同じ符号が付されている。 An interlayer insulating film 9 having a thickness of 1 [μm] is again formed on the entire surface, and the same steps as described above are repeated. In the figure, the third polysilicon layer is shown in a state of being monocrystalized as in FIG. 1, and the same parts as in FIG. 1 are given the same reference numerals.
上記した方法によると、最初に窓開けされた孔
３の上に単結晶シリコンがエピタキシヤル成長せ
しめられ、このいわば単結晶シリコンの柱を核と
して各層のポリシリコンが単結晶化されるから、
この単結晶化は各層に形成されたデバイスになん
らの影響を与えることなく実施され、別の表現を
用いると各層上のデバイスはその層上のポリシリ
コン層の単結晶化の妨げとならない。 According to the method described above, single crystal silicon is first epitaxially grown on the hole 3 that is opened, and the polysilicon in each layer is single crystallized using the so-called pillars of single crystal silicon as cores.
This single crystallization is performed without any effect on the devices formed on each layer, and in other words, the devices on each layer do not interfere with the single crystallization of the polysilicon layer on that layer.
更に、本発明の方法においては、前記した単結
晶シリコンの柱を、ウエハーのスクライブ・ライ
ンの部分に形成する。単結晶シリコン柱は結晶核
としての機能を果たすだけで、形成される半導体
デバイスのいかなる部分をも構成するものではな
く、全作業が終了すると放棄されるべきものであ
る。かかる単結晶シリコン柱を、それに沿つてウ
エハーが切断されるスクライブ・ラインの上に形
成し、ウエハー面積の有効利用が実現されるので
ある。 Further, in the method of the present invention, the above-described single crystal silicon pillars are formed at the scribe line portions of the wafer. The single crystal silicon pillars serve only as crystal nuclei, do not form any part of the semiconductor device being formed, and should be discarded once the entire operation is complete. By forming such single crystal silicon pillars on the scribe lines along which the wafer is cut, effective use of the wafer area is realized.
第３図はウエハーの１部分の平面図であり、図
においてＣはチツプを、またＤはチツプ内に形成
されたデバイスを示す。チツプＣ間の縦横に走る
幅約100〔μm〕の溝の中心にスクライブ・ライン
があり、本発明においては、単結晶シリコン柱を
このスクライブ・ラインの上に形成する。そのた
めには、第１図を再び参照すると、単結晶シリコ
ン基板１（ウエハー）上にSiO2膜２を形成し、
それをパターニングして基板１を露出させる孔３
を形成するとき、孔３がスクライブ・ラインのと
ころに来るようにする。 FIG. 3 is a plan view of a portion of the wafer, in which C indicates a chip and D indicates a device formed within the chip. A scribe line is located at the center of the groove having a width of about 100 [μm] running vertically and horizontally between the chips C, and in the present invention, a single crystal silicon pillar is formed on this scribe line. To do this, referring again to FIG. 1, a SiO 2 film 2 is formed on a single crystal silicon substrate 1 (wafer),
Hole 3 to expose the substrate 1 by patterning it
When forming the hole 3, make sure that it is at the scribe line.
いいかえると、スクライブ・ラインのところに
SiO2膜が存在しないようにパターニングし、い
わば単結晶シリコン柱を「切りしろ」にするので
ある。かくすることによつて、ウエハーの面積は
効率良く利用されることになる。In other words, at the scribe line
The patterning is done so that no SiO 2 film exists, so to speak, to "cut out" the single crystal silicon pillars. By doing so, the area of the wafer can be used efficiently.
上述の説明において、単結晶化のための加熱手
段としてレーザー照射を例にとつたが、かかる目
的のために利用されうるものはレーザーに限定さ
れることなく、電子ビーム、イオンビームも用い
うるし、更にフラツシユ・ライトも集光して用い
ることができる。要は、非単結晶層を下地に影響
しないよう局部的に加熱してそれを溶融するエネ
ルギーをもつエネルギー線であればよい。また、
例をポリシリコン層にとつたが、それはアモルフ
アス・シリコンでもよく、これらは非単結晶体と
呼称することが適切であろう。 In the above description, laser irradiation was used as an example of a heating means for single crystallization, but what can be used for this purpose is not limited to lasers, and electron beams and ion beams can also be used. Furthermore, flash light can also be used to condense the light. In short, any energy beam can be used as long as it has the energy to locally heat and melt the non-single crystal layer without affecting the underlying layer. Also,
Although the example is taken of a polysilicon layer, it may also be amorphous silicon, and it would be appropriate to refer to these as non-monocrystalline materials.
以上に説明した本発明の方法を要約すると、
(1) 単結晶半導体基板（ウエハー）上に絶縁層
（SiO2）を設け、スクライブ・ライン上におい
て基板半導体を露出させ、全面に非単結晶層を
被着し、エネルギー線の照射により、露出基板
を核として、非単結晶層を単結晶化する。 To summarize the method of the present invention explained above, (1) An insulating layer (SiO 2 ) is provided on a single crystal semiconductor substrate (wafer), the substrate semiconductor is exposed on the scribe line, and a non-single crystal layer is formed on the entire surface. is deposited, and the non-single crystal layer is made into a single crystal by irradiation with energy rays, using the exposed substrate as a nucleus.
(2) スクライブ・ライン部の単結晶を除いた領域
に半導体装置を形成し、かつ、スクライブ・ラ
イン部以外に層間絶縁膜を設け、再び非単結晶
層を被着し、エネルギー線照射により、スクラ
イブ・ライン部の単結晶を核として第２層目を
単結晶化する。(2) Form a semiconductor device in the area excluding the single crystal in the scribe line area, provide an interlayer insulating film in areas other than the scribe line area, deposit a non-single crystal layer again, and irradiate it with energy rays. The second layer is made into a single crystal using the single crystal in the scribe line portion as a core.
(3) 上記した工程を繰返す。(3) Repeat the above steps.
以上から理解されうる如く、本発明の方法を実
施するときは、各半導体層の結晶方位の指定、単
結晶化が確実に行われ、かつ、半導体ウエハーを
無駄なく有効に利用し、半導体装置の高集積度が
実現されうるのである。 As can be understood from the above, when implementing the method of the present invention, designation of crystal orientation and single crystallization of each semiconductor layer are reliably carried out, semiconductor wafers are used effectively without waste, and semiconductor devices are A high degree of integration can be achieved.
第１図は従来技術による非単結晶層の単結晶化
の工程を示す断面図、第２図は本発明の方法を実
施する工程を示す断面図、第３図はウエハーの１
部分の平面図である。
１…単結晶シリコン基板、２…SiO2膜、３…
孔、４…ポリシリコン層、５…レーザー・ビー
ム、６…ポリシリコン・ゲート、７…ゲート酸化
膜、９…層間絶縁膜、１０…コンタクト部分、１
４…第1LSI層、１４′…第2LSI層、Ｃ…チツプ、
Ｄ…半導体デバイス、８…酸化膜。
FIG. 1 is a cross-sectional view showing the process of single crystallizing a non-single crystal layer according to the prior art, FIG. 2 is a cross-sectional view showing the process of carrying out the method of the present invention, and FIG.
FIG. 1... Single crystal silicon substrate, 2... SiO 2 film, 3...
Hole, 4... Polysilicon layer, 5... Laser beam, 6... Polysilicon gate, 7... Gate oxide film, 9... Interlayer insulating film, 10... Contact portion, 1
4...1st LSI layer, 14'...2nd LSI layer, C...chip,
D...Semiconductor device, 8...Oxide film.
Claims (1)
板のスクライブ・ライン上に基板半導体を露出
し、次いで全面に非単結晶半導体層を被着し、エ
ネルギー線照射によりスクライブ・ラインの基板
半導体を結晶核として該非単結晶半導体層を単結
晶化し、スクライブ・ライン上を除く領域の単結
晶化半導体層内に半導体装置を形成した後、スク
ライブ・ライン部以外に層間絶縁膜を設け、該絶
縁膜上に再び非単結晶半導体層を被着し、エネル
ギー線照射によりスクライブ・ラインの単結晶化
半導体層を結晶核として該非単結晶半導体層を単
結晶化する工程を含むことを特徴とする半導体装
置の製造方法。1. An insulating film is formed on a single crystal semiconductor substrate, the substrate semiconductor is exposed on the scribe line of the substrate, a non-single crystal semiconductor layer is then deposited on the entire surface, and the substrate semiconductor at the scribe line is exposed by energy beam irradiation. The non-single-crystal semiconductor layer is single-crystalized using the non-single-crystal semiconductor layer as a crystal nucleus, and a semiconductor device is formed in the single-crystal semiconductor layer in a region excluding the scribe line, and then an interlayer insulating film is provided in areas other than the scribe line, and the insulating layer is A semiconductor characterized by comprising the step of again depositing a non-single-crystalline semiconductor layer on the film, and single-crystallizing the non-single-crystalline semiconductor layer by using the single-crystalline semiconductor layer at the scribe line as a crystal nucleus by irradiation with energy rays. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56041328A JPS57155764A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56041328A JPS57155764A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57155764A JPS57155764A (en) | 1982-09-25 |
| JPS6342417B2 true JPS6342417B2 (en) | 1988-08-23 |
Family
ID=12605445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56041328A Granted JPS57155764A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57155764A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5853822A (en) * | 1981-09-25 | 1983-03-30 | Toshiba Corp | Laminated semiconductor device |
| JPS5892211A (en) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS5996761A (en) * | 1982-11-25 | 1984-06-04 | Mitsubishi Electric Corp | Multi-stage semiconductor device |
| JPS6074553A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH0851109A (en) * | 1994-04-11 | 1996-02-20 | Texas Instr Inc <Ti> | Epitaxial silicon growth inside window of wafer patterned byoxide |
| US8247317B2 (en) * | 2009-09-16 | 2012-08-21 | Applied Materials, Inc. | Methods of solid phase recrystallization of thin film using pulse train annealing method |
-
1981
- 1981-03-20 JP JP56041328A patent/JPS57155764A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57155764A (en) | 1982-09-25 |
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