JPS6159820A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6159820A
JPS6159820A JP18190684A JP18190684A JPS6159820A JP S6159820 A JPS6159820 A JP S6159820A JP 18190684 A JP18190684 A JP 18190684A JP 18190684 A JP18190684 A JP 18190684A JP S6159820 A JPS6159820 A JP S6159820A
Authority
JP
Japan
Prior art keywords
film
region
polysilicon
single crystal
crystal silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18190684A
Other languages
Japanese (ja)
Inventor
Junji Sakurai
桜井　潤治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18190684A priority Critical patent/JPS6159820A/en
Publication of JPS6159820A publication Critical patent/JPS6159820A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

PURPOSE:To flatten the surface of an element forming section in the extent only of irregularities of 50Angstrom by forming a reflecting film for energy beams onto an element forming region, recrystallizing a polysilicon film and shaping the thickness of insulating isolation of the element region by said reflecting film. CONSTITUTION:A polysilicon film 12 and an insulating film 13 are applied onto an insulator 11 formed onto a wafer, a nitride film is grown on the whole surface, and the nitride film is patterned so as to remain only on an element forming region. The wafer on which the energy-beam SiO2 layer 11 is shaped is scanned to melt the polysilicon film 12, a single crystal silicon region 12a is formed through the recrystallization of the film 12, and field regions 13a as element isolation layers are shaped through a selective oxidation method using the Si3N4 film 14 as a mask. In a recrystallizing process, the SiO2 film 13 functions as an antireflection film in a region of 12a, polysilicon in the region 12 is kept at a high temperature, and a change into irregularities of the surface of the single crystal silicon layer 12a is relaxed remarkably. Lastly, the Si3N4 film 14 is removed, and a P type region and N<+> type source, drain and gate are formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、特にシリコン・オン・
インシュレータ（ＳＯＩ　）のアニールによるシリコン
の単結晶化に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, particularly a silicon-on-silicon device.
This article relates to single crystallization of silicon by annealing an insulator (SOI).

絶縁物の上の非単結晶シリコン例えば多結晶シリコン（
ポリシリコン）を単結晶化し、この単結晶シリコンに素
子を形成する技術は、素子の分離、浮遊容量の解消の見
地から研究されている分野であり、それについては多種
の方法が開発されている。Non-monocrystalline silicon on an insulator, such as polycrystalline silicon (
The technology of single-crystalizing polysilicon (polysilicon) and forming elements on this single-crystal silicon is an area of research from the standpoint of separating elements and eliminating stray capacitance, and a variety of methods have been developed for this purpose. .

〔従来の技術〕[Conventional technology]

フランス人Ｊ、Ｐ、　ＣｏＨｎｇｅは、ポリシリコン上
に反射防止ｊ模としてシリコンナイトライド膜（Ｓｉ３
Ｎｇ膜、以下窒化膜と略称する）をストライプ状に平行
にパターニングしてレーザを照射し、窒化膜の下のポリ
シリコンの温度を高くし、ポリシリコンを再結晶化する
において、窒化膜のない部分のポリシリコンにダレイン
バウンダリー（ｇｒａｉｎｂｏｕｎｄａｒｙ）の入らな
い再結晶シリコン膜を作る方法を、ＡＩ”Ｌ　４１（４
１，１５Ａｕｇｕｓｔ　１９８２に発表した。第３図（
ａ）の断面図を参照すると、シリコン基板１上に５ｉＯ
２１）Ｎ　２が形成され、その上にポリシリコン１）灸
３が形成され、ポリシリコン膜３の上にストライプ状の
紙面の垂直方向に延びる窒化膜４がパターニングされた
後の状態が示される。Frenchman J.P. CoHnge developed a silicon nitride film (Si3) as an anti-reflection layer on polysilicon.
A Ng film (hereinafter abbreviated as nitride film) is patterned in parallel stripes and irradiated with a laser to raise the temperature of polysilicon under the nitride film to recrystallize the polysilicon. AI"L 41 (4) describes a method for making a recrystallized silicon film without grain boundaries in the polysilicon portion.
Published on 1,15 August 1982. Figure 3 (
Referring to the cross-sectional view in a), 5iO is deposited on the silicon substrate 1.
21) The state after N2 is formed, polysilicon 1) moxibustion 3 is formed on it, and a striped nitride film 4 extending in the direction perpendicular to the plane of the paper is patterned on the polysilicon film 3. .

第３図（ｂ）はレーザ照射した後のポリシリコンＩＩＷ
３の温度分布を示す線図で、同図において、線ＴＩ′１
）はポリシリコンの溶融温度を表し、線Ｔｍの上ではポ
リシリコンが溶融しており、その下では再結晶化するこ
とを示す。同図は、窒化膜の下では窒化膜が反射防止ｊ
漠として働くので温度が高く、窒化膜のないところでは
温度が低いことを示す。レーザ照射後は、図示の曲線の
谷の部分が最初に線Ｔｍを超えて再結晶化し、次いで曲
線の山に向って再結晶化が進むことを示す。Figure 3(b) shows polysilicon IIW after laser irradiation.
3. In the diagram, the line TI'1
) represents the melting temperature of polysilicon, indicating that polysilicon is melted above the line Tm and recrystallized below it. The figure shows that the nitride film has antireflection under the nitride film.
This indicates that the temperature is high because it works in a vague manner, and the temperature is low in areas where there is no nitride film. After laser irradiation, the valley portion of the illustrated curve first recrystallizes beyond the line Tm, and then recrystallization progresses toward the peak of the curve.

〔発明が解決しようとする問題点〕 前記したＣｏＣｏ１）ｎの技術においては、窒化膜４の
ない部分のポリシリコンの表面には２０００人程度０凹
凸が形成され、微細素子の製作には不向きであることが
判明した。かかる凹凸が形成される理由は、第４図を参
照すると、レーザビームのエネルギー分布は曲線Ａで示
される如きものであり、それに対応し溶融したポリシリ
コン膜３の表面は表面張力によって図示の如くになり、
冷却すると図にＢに示す部分に歪が発生するためである
と解される。[Problems to be Solved by the Invention] In the above-mentioned CoCo1)n technology, approximately 2,000 unevenness is formed on the surface of the polysilicon in the area where the nitride film 4 is not present, making it unsuitable for manufacturing fine devices. It turns out that there is something. The reason why such unevenness is formed is that the energy distribution of the laser beam is as shown by curve A in FIG. become,
It is understood that this is because distortion occurs in the portion shown in B in the figure when cooling.

更に、窒化膜４をストライプ状に平行にパターニングす
る場合には、窒化膜４の幅と窒化膜の間の間隔とそこに
作る回路素子のレイ・アウトにおいては制約がある。Furthermore, when patterning the nitride film 4 in parallel stripes, there are restrictions on the width of the nitride film 4, the spacing between the nitride films, and the layout of circuit elements formed therein.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記問題点を解消したＳＯＩのアニールの改
善された方法を提供するもので、その手段は、絶縁物の
上に非単結晶シリコン膜、絶縁膜およびエネルギービー
ム反射ｌ挨を順に形成する工程、前記反射膜を素子形成
領域上にのみ残す如くパターニングする工程、エネルギ
ービームにより前記非単結晶シリコン膜を溶融し再結晶
化して単結晶シリコン領域を形成する工程、前記反射膜
はそのまま残し選択酸化法によって反射膜の形成されて
いない領域を酸化して素子分離層を形成する工程、およ
び単結晶シリコン領域に素子を形成することを特徴とす
る半導体装置の製造方法によってなされる。The present invention provides an improved method for annealing SOI that solves the above-mentioned problems, and the method includes sequentially forming a non-single crystal silicon film, an insulating film, and an energy beam reflecting layer on an insulator. a step of patterning the reflective film so as to leave it only on the element formation region; a step of melting and recrystallizing the non-single crystal silicon film with an energy beam to form a single crystal silicon region; a step of leaving the reflective film as it is; This is accomplished by a method of manufacturing a semiconductor device characterized by forming an element isolation layer by oxidizing a region where a reflective film is not formed using a selective oxidation method, and forming an element in a single crystal silicon region.

〔作用〕[Effect]

上記したＳ０１のアニールにおいて、素子形成領域上に
エネルギービームの反射膜（またはキャップ）を設け、
半導体膜例えばポリシリコン膜を再結晶化した後に、同
じ反射膜で素子領域の絶縁分離を実現するものである。In the above-described S01 annealing, an energy beam reflecting film (or cap) is provided on the element formation region,
After recrystallizing a semiconductor film, such as a polysilicon film, the same reflective film is used to achieve insulation isolation of element regions.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.

第１図ｆａ）に示される如くウェハ上に形成された絶縁
物、例えばＳｉＯ＋層１）層上１図に砂地を付して示す
ポリシリコン膜１２を通常の技術で５０００人の膜厚に
成長し、ポリシリコン膜１２上に均一にポリシリコンＩ
ＩＱの溶融・再結晶化の際、表面の平坦化のための氷色
本！ＩＩ莫例えば５ｉ０２１）央１３を１０００人のＩ
ＩＱ厚に被着する。引続き全面に窒（ヒ膜（Ｓｉ３Ｎ４
１）史）を３００人の膜厚に成長し、それが素子形成領
域上にのみ残るようパターニングする。かかるパターニ
ングは前記した従来技術のストライプ状に平行にパター
ニングする場合よりも容易になされる。As shown in Fig. 1fa), a polysilicon film 12 (shown with sand in Fig. 1) is grown on the insulator, e.g., SiO+ layer 1) layer, to a thickness of 5,000 layers using conventional techniques. Then, polysilicon I is uniformly deposited on the polysilicon film 12.
An ice-colored book for flattening the surface during melting and recrystallization of IQ! II Mo For example 5i021) Middle 13 I of 1000 people
Deposit to IQ thickness. Subsequently, a nitride film (Si3N4) was applied to the entire surface.
1) Grow the film to a thickness of 300 nm and pattern it so that it remains only on the element formation region. Such patterning can be performed more easily than in the case of patterning parallel to stripes in the prior art described above.

エネルギービーム例えば集光されたキセノンランプ光（
パワー密度Ｉ　ＫＷ／　ｃｍ２）で、１ｍｍ／ｓのスピ
ードで５ｉ０２１ｔｊｔｌｌが形成されたウェハを走査
し、ポリシリコン膜１２を熔融し、再結晶化して単結晶
シリコン領域１２ａを形成した後に、ｓｔｇＮ、、ＩＪ
ｉｆｆ１４をマスクにする選択酸化法で素子分離層とな
るフィールド領域を形成する（第１図（ｂ））。なお第
１図（ｂｌにおいて、図に白地で示す部分１２ａは単結
晶シリコン領域、１３ａはフィールド領域（酸化膜の素
子分離層）を示す。なお、アニールには集光されたキセ
ノンランプ光に代えてレーザ光を用いてもよい。An energy beam, e.g. focused xenon lamp light (
After scanning the wafer on which 5i021tjtll was formed at a speed of 1 mm/s with a power density I KW/cm2) and melting the polysilicon film 12 and recrystallizing it to form a single crystal silicon region 12a, stgN, , I.J.
A field region that will become an element isolation layer is formed by selective oxidation using if14 as a mask (FIG. 1(b)). In FIG. 1 (bl), the white area 12a in the figure is a single crystal silicon region, and 13a is a field region (an oxide film element isolation layer). Alternatively, a laser beam may be used.

前記した再結晶化工程においては、５ｉＯ２１）莫１３
は１２ｂの領域では反射防止膜として働き、１２のに比
べ１２ｂ：１ｌＩＩ＆のポリシリコンを高温に（呆ぢ、
かつ、単結晶シリコンＩＷ１２ａの表面の凹凸化が著し
く緩和される。In the recrystallization step described above, 5iO21) Mo13
acts as an antireflection film in the 12b region, and compared to 12b, the polysilicon of 12b:1lII& is heated to a high temperature (sadly,
Moreover, the unevenness of the surface of the single crystal silicon IW 12a is significantly reduced.

最後に、通常の技術で第１図（Ｃ１に示される如く素子
を形成する。すなわち、５ｉａＮｑ　１）１）４を除去
し、ｐ　型頭ｂＭ、Ｎ“型のソース（Ｓ）、ドレイン（
Ｄ）およびゲート（Ｇ）を形成する。Finally, the device is formed as shown in FIG.
D) and gate (G) are formed.

本発明の他の実施例は第２図の断面図に示され、先ず第
２図ｆａ）に示される如く、５ｉ０２１）Ｗ１３を２０
０゜人の膜厚に形成する。なお、第２図において、第１
図に示した部分と同じ部分は同一符号を付して表示する
。Another embodiment of the invention is shown in the cross-sectional view of FIG. 2, first of all, as shown in FIG.
Form to a film thickness of 0°. In addition, in Figure 2, the first
The same parts as those shown in the figures are indicated by the same reference numerals.

引続き　５ｉ０２膜１３上に前記した５ｉ３Ｎｑ膜に代
えて金Ｂ薄１）ｆｆ例えばタングステン（ｗ）＋＋ｉｔ
ｓを通常の技術で形成し、タングステン膜を素子形成領
域上にのみ残るようパターニングする。更に、エネルギ
ービームとして電子ビーム（ＥＢ）を、５０ＫｅＶのエ
ネルギー、５　ｃｍ／　ｓの走査スピード、電流２ｍＡ
で照射してポリシリコン膜１２をアニールし、再結晶化
して島状の単結晶シリコン領域１２ａ（図に白地で示す
）を作る。なお図において、砂地を付して示す部分１２
ｂはグレインなどの残っている部分を示す。このとき、
５ｉ０２１に’１３は局部的な蓄熱層とポリシリコンの
平坦化の機能を果す。Continuing, on the 5i02 film 13, instead of the 5i3Nq film described above, a gold B thin film 1)ff, for example, tungsten (w)++it is applied.
A tungsten film is formed using a conventional technique and patterned so that the tungsten film remains only on the element formation region. Furthermore, an electron beam (EB) was used as the energy beam, with an energy of 50 KeV, a scanning speed of 5 cm/s, and a current of 2 mA.
The polysilicon film 12 is annealed and recrystallized to form an island-shaped single crystal silicon region 12a (shown in white in the figure). In addition, in the figure, part 12 shown with sandy area
b indicates remaining portions such as grains. At this time,
5i021 '13 functions as a local heat storage layer and planarization of polysilicon.

次いで、第２図（ｂｌに示される如く、タングステン膜
１５をマスクにしてＳｉＯ＋　ｌｌＡ１３、ポリシリコ
ン１）ｇ１２ｂをエツチングして島状の単結晶シリコン
領域１２ａを作る。Next, as shown in FIG. 2 (bl), using the tungsten film 15 as a mask, the SiO+ llA 13, polysilicon 1) g12b is etched to form an island-shaped single crystal silicon region 12a.

最後に通常の技術でＰ型頭域、Ｎ＋型のソース（Ｓ）、
ドレイン（Ｄ）、およびゲート（Ｇ）を作る。Finally, with the usual technique, P type head area, N+ type source (S),
Make the drain (D) and gate (G).

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、単結晶化される領
域が予め素子形成領域として定めることができ、・セル
フアラインメント方式で素子の絶縁または分離ができ、
しかも素子形成部の表面が５０人の凹凸しかない程度に
平坦化される。なお、以上の例ではアニールにキセノン
ランプ光、ＥＢを用いる場合について説明したが、本発
明の適用範囲はその場合に限られるものでなく、その他
のエネルギービームを用いる場合にも及ぶ。As explained above, according to the present invention, the region to be single crystallized can be determined in advance as an element formation region, and the elements can be insulated or separated by a self-alignment method.
In addition, the surface of the element forming portion is flattened to the extent that there are only 50 irregularities. Note that although the above example describes the case where xenon lamp light or EB is used for annealing, the scope of application of the present invention is not limited to that case, but also extends to cases where other energy beams are used.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）ないしくＣ）および第２図（ａ）ないしｆ
ｃ）は本発明の一実施例と他の実施例の断面図、第３図
（ａｌとｆｂ）は従来例の断面図と温度分布を示す線図
、第４図は従来例のポリシリコン膜の表面を示す断面図
である。 図中、１）はＳｉＯ２層、１２はポリシリコン膜、１２
ａは単結晶シリコン領域、１３は５ｉ０２膜、１３ａは
フィール′ド領域、１４はＳｉ、ＩＮ＋＋膜、１５はタ
ングステン膜、をそれぞれ示す。 第１図 １／。 第２図 １２ｂ　　　１２ａ　　　　）２ｂ 第３図Figure 1 (a) to C) and Figure 2 (a) to f
c) is a sectional view of one embodiment of the present invention and another embodiment, FIG. 3 (al and fb) is a sectional view of a conventional example and a diagram showing temperature distribution, and FIG. 4 is a polysilicon film of a conventional example. FIG. In the figure, 1) is a SiO2 layer, 12 is a polysilicon film, 12
Reference numeral a indicates a single crystal silicon region, 13 a 5i02 film, 13a a field region, 14 a Si, IN++ film, and 15 a tungsten film. Figure 1 1/. Figure 2 12b 12a ) 2b Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）絶縁物の上に非単結晶シリコン膜、絶縁膜および
エネルギービーム反射膜を順に形成する工程、前記反射
防止膜を素子形成領域上にのみ残す如くパターニングす
る工程、エネルギービームにより前記非単結晶シリコン
膜を溶融し再結晶化して単結晶シリコン領域を形成する
工程、前記反射膜はそのまま残し選択酸化法によって反
射膜の形成されていない領域を酸化して素子分離層を形
成する工程、および単結晶シリコン領域に素子を形成す
ることを特徴とする半導体装置の製造方法。(1) A step of sequentially forming a non-single crystal silicon film, an insulating film and an energy beam reflective film on an insulator, a step of patterning the anti-reflection film so as to leave it only on the element formation region, and a step of patterning the anti-reflection film so as to leave it only on the element formation region. a step of melting and recrystallizing the crystalline silicon film to form a single crystal silicon region; a step of leaving the reflective film as it is and oxidizing the region where the reflective film is not formed by a selective oxidation method to form an element isolation layer; A method of manufacturing a semiconductor device, characterized by forming an element in a single crystal silicon region. （２）前記反射膜が金属薄膜であり、パターニングされ
た当該金属膜をマスクにして前記絶縁膜および非単結晶
シリコン膜をエッチングし島状の単結晶シリコン領域を
形成することを特徴とする特許請求の範囲第１項記載の
半導体装置の製造方法。(2) A patent characterized in that the reflective film is a metal thin film, and the insulating film and non-single crystal silicon film are etched using the patterned metal film as a mask to form island-shaped single crystal silicon regions. A method for manufacturing a semiconductor device according to claim 1.
JP18190684A 1984-08-31 1984-08-31 Manufacture of semiconductor device Pending JPS6159820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18190684A JPS6159820A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18190684A JPS6159820A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6159820A true JPS6159820A (en) 1986-03-27

Family

ID=16108954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18190684A Pending JPS6159820A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6159820A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999010918A1 (en) * 1997-08-22 1999-03-04 Micron Technology, Inc. Process of isolation in integrated circuit fabrication, using an antireflective coating
KR100233286B1 (en) * 1996-06-29 1999-12-01 김영환 Semiconductor device and fabricating method therefor
US6294459B1 (en) 1998-09-03 2001-09-25 Micron Technology, Inc. Anti-reflective coatings and methods for forming and using same
US6444588B1 (en) 1999-04-26 2002-09-03 Micron Technology, Inc. Anti-reflective coatings and methods regarding same
JP2008085318A (en) * 2006-08-31 2008-04-10 Semiconductor Energy Lab Co Ltd Crystalline semiconductor film, and manufacturing method of semiconductor device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100233286B1 (en) * 1996-06-29 1999-12-01 김영환 Semiconductor device and fabricating method therefor
US6605502B2 (en) 1997-08-22 2003-08-12 Micron Technology, Inc. Isolation using an antireflective coating
US6121133A (en) * 1997-08-22 2000-09-19 Micron Technology, Inc. Isolation using an antireflective coating
US6174590B1 (en) 1997-08-22 2001-01-16 Micron Technology, Inc. Isolation using an antireflective coating
US6423631B1 (en) 1997-08-22 2002-07-23 Micron Technology, Inc. Isolation using an antireflective coating
US6495450B1 (en) * 1997-08-22 2002-12-17 Micron Technology, Inc. Isolation using an antireflective coating
WO1999010918A1 (en) * 1997-08-22 1999-03-04 Micron Technology, Inc. Process of isolation in integrated circuit fabrication, using an antireflective coating
KR100424533B1 (en) * 1997-08-22 2004-03-27 마이크론 테크놀로지 인코포레이티드 Process of isolation in integrated circuit fabrication, using an antireflective coating
US6294459B1 (en) 1998-09-03 2001-09-25 Micron Technology, Inc. Anti-reflective coatings and methods for forming and using same
US6541843B2 (en) 1998-09-03 2003-04-01 Micron Technology, Inc. Anti-reflective coatings and methods for forming and using same
US6673713B2 (en) 1998-09-03 2004-01-06 Micron Technology, Inc. Anti-reflective coatings and methods for forming and using same
US6784094B2 (en) 1998-09-03 2004-08-31 Micron Technology, Inc. Anti-reflective coatings and methods for forming and using same
US6444588B1 (en) 1999-04-26 2002-09-03 Micron Technology, Inc. Anti-reflective coatings and methods regarding same
JP2008085318A (en) * 2006-08-31 2008-04-10 Semiconductor Energy Lab Co Ltd Crystalline semiconductor film, and manufacturing method of semiconductor device

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