JPS6181141U - - Google Patents
Info
- Publication number
- JPS6181141U JPS6181141U JP16666084U JP16666084U JPS6181141U JP S6181141 U JPS6181141 U JP S6181141U JP 16666084 U JP16666084 U JP 16666084U JP 16666084 U JP16666084 U JP 16666084U JP S6181141 U JPS6181141 U JP S6181141U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- recess
- fixed
- mount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
第１図は本考案の一実施例を樹脂を除いて示し
、ａは平面図、ｂは断面図、第２図は従来例を樹
脂を除いて示し、ａは平面図、ｂは正面図、第３
図は第１図に示した実施例のチツプ固着前におけ
る斜視図である。 １：マウント部、２：外部リード部、３：半導
体チツプ、４：ボンデイングワイヤ、５：樹脂、
７：凹部、７：傾斜面、７２：底面。
、ａは平面図、ｂは断面図、第２図は従来例を樹
脂を除いて示し、ａは平面図、ｂは正面図、第３
図は第１図に示した実施例のチツプ固着前におけ
る斜視図である。 １：マウント部、２：外部リード部、３：半導
体チツプ、４：ボンデイングワイヤ、５：樹脂、
７：凹部、７：傾斜面、７２：底面。
Claims (1)
- 金属よりなるマウント部上に半導体チツプが固
着され、半導体チツプの上面の電極と外部リード
部とがボンデイングワイヤにより接続され、半導
体チツプが樹脂により被覆されるものにおいて、
マウント部に階段状の傾斜面に囲まれた底面を有
する凹部が形成され、該凹部の底面上に半導体チ
ツプが固着されたことを特徴とする樹脂封止型半
導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16666084U JPS6181141U (ja) | 1984-11-02 | 1984-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16666084U JPS6181141U (ja) | 1984-11-02 | 1984-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6181141U true JPS6181141U (ja) | 1986-05-29 |
Family
ID=30724470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16666084U Pending JPS6181141U (ja) | 1984-11-02 | 1984-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181141U (ja) |
-
1984
- 1984-11-02 JP JP16666084U patent/JPS6181141U/ja active Pending