JPS616774U - Three-value detection circuit - Google Patents

Three-value detection circuit

Info

Publication number
JPS616774U
JPS616774U JP9172884U JP9172884U JPS616774U JP S616774 U JPS616774 U JP S616774U JP 9172884 U JP9172884 U JP 9172884U JP 9172884 U JP9172884 U JP 9172884U JP S616774 U JPS616774 U JP S616774U
Authority
JP
Japan
Prior art keywords
inverter
detection circuit
value detection
input terminal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9172884U
Other languages
Japanese (ja)
Inventor
文博 太斎
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP9172884U priority Critical patent/JPS616774U/en
Publication of JPS616774U publication Critical patent/JPS616774U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の3値検出回路の特性を示す特性図、第2
図は本考案の実施例を示す回路図である。 1・・・入力端子、2・・・第1のインバーク、3・・
・第2のインバータ、4,5・・・抵抗。
Figure 1 is a characteristic diagram showing the characteristics of a conventional three-value detection circuit;
The figure is a circuit diagram showing an embodiment of the present invention. 1... Input terminal, 2... First invert, 3...
-Second inverter, 4, 5...resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 互いにスレツショルド電圧が異なる第−1−のインバー
タと第2のインバータとが一つの入力端子子に接続され
、前記第1のインバータの出力、及び、第2のインバー
タの出力によって前記入力端子に印加された電圧レベル
を検出する3値検出回路に於いて、前記第1のインバー
タと第2のインバータの入力及び出力間に各々抵抗を接
続し、前記入力端子が開放されたとき入力端子の電圧を
前記異なるスレツショルド電圧の間に保持することを特
徴とする3値検出回路。
A first inverter and a second inverter having different threshold voltages are connected to one input terminal, and an output of the first inverter and an output of the second inverter are applied to the input terminal. In the three-value detection circuit that detects the voltage level of the first inverter and the second inverter, a resistor is connected between the input and output of the first inverter and the second inverter, and when the input terminal is opened, the voltage of the input terminal is A three-value detection circuit characterized by holding between different threshold voltages.
JP9172884U 1984-06-19 1984-06-19 Three-value detection circuit Pending JPS616774U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9172884U JPS616774U (en) 1984-06-19 1984-06-19 Three-value detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9172884U JPS616774U (en) 1984-06-19 1984-06-19 Three-value detection circuit

Publications (1)

Publication Number Publication Date
JPS616774U true JPS616774U (en) 1986-01-16

Family

ID=30647872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9172884U Pending JPS616774U (en) 1984-06-19 1984-06-19 Three-value detection circuit

Country Status (1)

Country Link
JP (1) JPS616774U (en)

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