JPS58172234U - oscillation circuit - Google Patents

oscillation circuit

Info

Publication number
JPS58172234U
JPS58172234U JP6923282U JP6923282U JPS58172234U JP S58172234 U JPS58172234 U JP S58172234U JP 6923282 U JP6923282 U JP 6923282U JP 6923282 U JP6923282 U JP 6923282U JP S58172234 U JPS58172234 U JP S58172234U
Authority
JP
Japan
Prior art keywords
capacitor
input terminal
oscillation circuit
switching element
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6923282U
Other languages
Japanese (ja)
Inventor
進 井口
憲次 小山
Original Assignee
株式会社リコー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社リコー filed Critical 株式会社リコー
Priority to JP6923282U priority Critical patent/JPS58172234U/en
Publication of JPS58172234U publication Critical patent/JPS58172234U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の発振回路を示す回路図、第2図は同発振
回路のタイミングチャート、第3図は本考案の一実施例
を示す回路図、第4図は同実施例のタイミングチャート
である。 Dl・・・スイッチング素子、C2・・・コンデンサ、
R2・・・抵抗。
Fig. 1 is a circuit diagram showing a conventional oscillation circuit, Fig. 2 is a timing chart of the same oscillation circuit, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a timing chart of the same embodiment. be. Dl... switching element, C2... capacitor,
R2...Resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1の入力端子の電圧に対して第1のしきい値で出力端
子が高いレベルになって第2のしきい値で出力端子が低
レベルになり第2の入力端子に入力される制御信号によ
り動作が制御される回路と、この回路の出力レベルに応
じて充放電を行なって充放電波波形を前記第1の入力端
子に印加する第1のコンデンサ及び第1の抵抗とを有す
る発振回路において、第2のコンデンサと、この第26
コンデンサと直列でこの直列回路が前記第1のコンデン
サと並列に接続されるスイッチング素子と、コノスイッ
チング素子及び前記第2のコンデンサと前記第2の入力
端子との間に接続された抵抗とを備えた発振回路。
With respect to the voltage of the first input terminal, the output terminal becomes a high level at a first threshold value, the output terminal becomes a low level at a second threshold value, and a control signal is input to the second input terminal. and a first capacitor and a first resistor that charge and discharge according to the output level of the circuit and apply a charge/discharge waveform to the first input terminal. , the second capacitor and this 26th capacitor
The series circuit includes a switching element connected in series with the capacitor and in parallel with the first capacitor, and a resistor connected between the switching element, the second capacitor, and the second input terminal. oscillation circuit.
JP6923282U 1982-05-12 1982-05-12 oscillation circuit Pending JPS58172234U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6923282U JPS58172234U (en) 1982-05-12 1982-05-12 oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6923282U JPS58172234U (en) 1982-05-12 1982-05-12 oscillation circuit

Publications (1)

Publication Number Publication Date
JPS58172234U true JPS58172234U (en) 1983-11-17

Family

ID=30078966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6923282U Pending JPS58172234U (en) 1982-05-12 1982-05-12 oscillation circuit

Country Status (1)

Country Link
JP (1) JPS58172234U (en)

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