JPS6165443A - Ｉｃチツプの組込み方法 - Google Patents

Ｉｃチツプの組込み方法

Info

Publication number
JPS6165443A
JPS6165443A JP59187621A JP18762184A JPS6165443A JP S6165443 A JPS6165443 A JP S6165443A JP 59187621 A JP59187621 A JP 59187621A JP 18762184 A JP18762184 A JP 18762184A JP S6165443 A JPS6165443 A JP S6165443A
Authority
JP
Japan
Prior art keywords
chip
terminal conductors
insulating plate
circuit board
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59187621A
Other languages
English (en)
Inventor
Yoshihiro Hirota
廣田　善弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59187621A priority Critical patent/JPS6165443A/ja
Publication of JPS6165443A publication Critical patent/JPS6165443A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 イ、産業上の利用分野 本発明は、モノリフｙりＩＣチップを、混成集積回路基
板にワイヤレスボンディング方式で組み込む方法に関す
る。
口、従来の技術 従来、混成集積回路基板に、ワイヤレスボンディングに
よりモノリフツクＩＣチップを組込むＫは、クリップチ
ップ方式とビームリード方式がある。前者は、チップ表
面に突起電極（バンプ）を形成し、チップを裏返してバ
ンプを直接混成集積回路基板のリードパターンに接続す
る方法であり、後者は、チップの外側にまでビームリー
ドを伸ばし、裏返したチップの裏面からも観察できるリ
ードを混成集積回路基板のリードパターンに接続する方
法である。
ハ０発明が解決しようとする問題点 上記従来のフリップチップ方式またはビームリード方式
などのワイヤレスボンディングでは、バンプまたはビー
ムリードを形成するのに多くの工数を必要とし高価にな
る。また、フリップチップは、接合部がチップの下にな
り直接目視できないので、接合部不良の解析が困難なこ
と、および、両者共に、基板とＩＣチップが接続点以外
では離れているので放熱が悪いことなどが解決を要する
問題点である。
二０問題点を解決するための技術手段 上記問題点に対し、本発明では、ＩＣチップを−たん凹
み部分のある絶縁板の前記凹み部に固着し、凹み部の同
壁上面の表面端子導体とＩＣチップの電極との間を真空
蒸着により接続し、それから、前記表面端子導体とスル
ーホールを通して接続されている前記絶縁板の裏面端子
導体を、混成集積回路基板のリードパターンに直接接続
する。
ホ、実施例 つぎに本発明方法を実施例により説明する。
第１図（ａ）は本発明に係るＩＣチ７ブマウント用の絶
縁板の平面図、同図（ｂ）は図（ａ）のＡ−Ａ断面図で
ある。図において、絶縁板１は、ＩＣチップマウント用
の凹み部２が設けられており、かつ、各凹み部の外側に
はスルーホール３があけられている。さらに図示してな
いが、スルーホール３の上部開口部および下部開口部に
は、それぞれ表面端子導体と裏面端子導体が設けられて
いる。このような絶縁板に対し、第２図（ａ）のように
、絶縁板１の凹み部２にＩＣチップ４をマウントし、表
面を絶縁樹脂７で覆う。つぎに、第２図（ｂ）のように
ホトリソ技術と真空蒸着により、ＩＣチップ４のｔ的に
接続する。次に、第３図の側面図のように、裏面導体層
５側にハンダバンプ１２（ｉｌ−形成した後、基板を分
割し、各個片１０を、予備ハンダを施した導体層１１を
有する混成集積回路着板９に、ハンダリフ０−により接
続する。
へ１発明の効果 本発明の方法により、ＩＣチップにバンプ等を形成する
必要がなく、通常のワイヤ用ＩＣチップに、ワイヤレス
ボンディングを行なうことが可能となり、又、ＩＣチッ
プと基板との電気的接続点が表面にでているため、不良
解析等の心気的確認が行い易くなった。又、ＩＣチップ
の表面が′ｅ！縁性相性樹脂り情われているため、耐湿
性に優れた構造となっている。
【図面の簡単な説明】
第１図（ａ）は、本発明の一実施例に係るＩＣチップを
マウントする絶縁板の平面図、同図（ｂｌは同図（ａ）
のＡ−ｈｉｍ面図、第２図１３）　ｌ　ｆｌ））は第１
図の絶縁板にＩＣチップをマウントする工程を説明する
断面図、第３図は第２図の絶縁板を混成集積回路基板へ
組込んだ状態の側面図である。 １・・・・・・ＩＣチップマウント用絶碌板、２・・・
・・・ＩＣチップマウント部、３・・・・・・スルーホ
ール、４・・・・・・ＩＣチップ、５・・・・・・裏面
端子導体、６・・・・・・表面端子導体、７・・・・・
・絶縁性樹脂、８・・・・・・蒸着導体膜、９・・・・
・・混成集積回路基板、１０・・・・−ＩＣチップをマ
ウントした絶縁板個片、１１・・・・・・予備ハンダを
施した導体、１２・・・・・・ハンダバンプ。 茅　１　図 某　２　図 ／ｌＪ 茶　３　囮

Claims (1)

    【特許請求の範囲】
  1. 　チップマウント部を凹ませた絶縁板の前記チップマウ
    ント部にＩＣチップを固着し、さらに保護絶縁膜で前記
    チップを覆った後、前記チップマウント部周壁上面の表
    面端子導体と前記ＩＣチップの電極との間を導電体の真
    空蒸着により接続した後、前記表面端子導体とスルーホ
    ールを通して接続された前記絶縁板裏面端子導体を、混
    成集積回路基板のリードパターンに直接接続することを
    特徴とするＩＣチップの混成集積回路基板への組み込み
    方法。
JP59187621A 1984-09-07 1984-09-07 Ｉｃチツプの組込み方法 Pending JPS6165443A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59187621A JPS6165443A (ja) 1984-09-07 1984-09-07 Ｉｃチツプの組込み方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59187621A JPS6165443A (ja) 1984-09-07 1984-09-07 Ｉｃチツプの組込み方法

Publications (1)

Publication Number Publication Date
JPS6165443A true JPS6165443A (ja) 1986-04-04

Family

ID=16209310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59187621A Pending JPS6165443A (ja) 1984-09-07 1984-09-07 Ｉｃチツプの組込み方法

Country Status (1)

Country Link
JP (1) JPS6165443A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0421962U (ja) * 1990-06-18 1992-02-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0421962U (ja) * 1990-06-18 1992-02-24

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