JPS6159819A - Manufacture of semiconductor base body - Google Patents

Abstract

PURPOSE:To improve the crystallizability of a semiconductor layer on an insulating film by forming the semiconductor layer through selective epitaxial growth in the lateral direction from a semiconductor substrate in a section, in which one part or the whole of the first insulating film on the side surface of a groove is removed, and shaping a second insulating film so as to electrically isolate the semiconductor layer and the substrate. CONSTITUTION:A groove 2 having a quadrilateral plane shape is formed to a P type silicon wafer 1 to which boron is doped, and an oxide film 3 as first insulating film is shaped onto the surface of a substrate 1 containing the base and side surface of the groove 2 through hydrogen combustion oxidation. The oxide film 3 on the side surface shaped into the groove 2 is removed, and an epitaxial growth layer 4 as a semiconductor layer is formed into the groove 2 through epitaxial growth in the lateral direction toward a central point P from the side surface from the substrate 1. The epitaxial growth layer 4 on the side surface of the groove 2 is removed to shape an opening section, and an SiO2 film 5 as a second insulating film is buried into the opening section, thus manufacturing a semiconductor base body having SOI structure.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体基体の製造方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor substrate.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

近年、人工衛星や原子炉など電離放射線の影響下で使用
する優れた耐放射線性を有する半導体素子に対する要求
が強くなって来ている。In recent years, there has been an increasing demand for semiconductor elements with excellent radiation resistance that are used under the influence of ionizing radiation, such as in artificial satellites and nuclear reactors.

まだ、Ｌ８Ｉの微細化、高集積化に伴ない微小電流を取
り扱うようになって来たため、電離放射線（例えば・９
ツケージ材料からのα線）による半導体素子の誤動作が
問題となってきた。However, due to the miniaturization and high integration of L8I, it has become possible to handle minute currents, so ionizing radiation (for example, 9
Malfunction of semiconductor devices due to alpha rays from cage materials has become a problem.

このため、本質的に耐放射線性の優れた。９０Ｉ（Ｓｉ
ｌｉｃｏｎ　ｏｎ　Ｉｎ５ｕｌａｔｏｒ）構造の半導体
基板が注目されている。同様に、ＬＳＩの微細化高集積
化に伴ない低油＊　’ｉＫ力のＣＭＯ８Ｌ、９Ｉが用い
られて来ているが１通常の半導体基板（例えばシリコン
基板）を用いたＣＭＯ８ＬＳＩ　では寄性チイリスクに
よるラッチアップ現象が避けられない。この点、ＳＯＩ
構造の半導体基板を用いれば前述したラッチアップ現象
を回避できる。Therefore, it has essentially excellent radiation resistance. 90I(Si
Semiconductor substrates with a licon on inductor structure are attracting attention. Similarly, with the miniaturization and high integration of LSIs, CMO8L and 9I with low oil consumption are being used. Latch-up phenomenon is inevitable. In this regard, SOI
By using a semiconductor substrate with this structure, the latch-up phenomenon described above can be avoided.

また、８０Ｉ構造の半導体基板を用いたＣＭＯ８ＬＳＩ
では構造上寄性容ｆｉ【が通常の半導体基板と比して低
減できるので、より高速な動作速度が期待できる。これ
らの点からもＳＯＩ構造の半導体基板が注目されている
。しかしながら。In addition, CMO8LSI using an 80I structure semiconductor substrate
Since the parasitic capacitance fi can be reduced compared to a normal semiconductor substrate due to its structure, higher operating speed can be expected. From these points as well, semiconductor substrates with an SOI structure are attracting attention. however.

ＳＯＩ構造の半導体基板は、シリコン基板に関してレー
ザービームや電子ビームによるアニール法、ＦＩ　　Ｐ
ＯＳ、酸素チャネルイオン注入後エピタキシャル成長を
行なう方法１選択エピタキシャル成長による方法、ラテ
ラルエピタキシャル成長法などの種々の方法が提案され
ているが、絶縁膜上のシリコン層の結晶性など問題が多
い。Semiconductor substrates with an SOI structure are manufactured using annealing methods using laser beams or electron beams on silicon substrates, FI P
Various methods have been proposed, such as method 1 selective epitaxial growth in which epitaxial growth is performed after OS and oxygen channel ion implantation, and lateral epitaxial growth, but these methods have many problems such as the crystallinity of the silicon layer on the insulating film.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので。 The present invention has been made in view of the above circumstances.

絶縁膜上の半導体層の結晶性を向上し得る半導体基体の
製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor substrate that can improve the crystallinity of a semiconductor layer on an insulating film.

〔発明のイ既要〕[Existing requirements of the invention]

本発明は、溝側面の第１の絶縁膜を一部もしくは全部除
去した後、除去した部分の半導体基板から横方向に選択
エピタキシャル成長を行なって半導体層を形胤後工程で
この半導体層と基板とを電気的に分離するように第２の
絶縁膜を形成することを特徴とし、上記半畳体層の結晶
性の１川上を図ったものである。In the present invention, after removing a portion or all of the first insulating film on the side surface of the groove, selective epitaxial growth is performed in the lateral direction from the removed portion of the semiconductor substrate to form a semiconductor layer. It is characterized by forming a second insulating film so as to electrically isolate the layers, and is intended to be one step higher than the crystallinity of the semiconvoluted layer.

〔発明の実地例〕[Practical example of the invention]

以下、本発明について図を参照して説明する。 Hereinafter, the present invention will be explained with reference to the drawings.

実施例１ まス、フケロンをドープした比抵抗２〜５Ω儒のＰ型の
シリコン４インチウェハ（半導体基板）１に、写真蝕刻
（ＰＥＰ）、反応性イオンエツチング（ＲＩＥ）を用い
て巾１０μｍ、深さ５μｍの平面形状が四角形の溝２を
形成した（第１図（ａ）図示）。つづいて、１０００℃
、３時間の水素燃焼酸化により、溝２の底面及び側面を
含む基板１表面に第１の絶縁膜としての厚さ７５００又
の酸化膜３を形成した（第１図（ｂ１図示）、次いで、
溝２に形成された側面の酸化膜３をＰ　ＥＰ及びウェッ
トエツチングにより除去した（第１図（０１図示〕。し
かる後、基板Ｉより第２図に示す如く４側面から中心点
Ｐに向うように横方向に４２　ｔｏｒｒ、　１０７５℃
、　Ｓ　Ｉ　Ｃｌｔ　Ｈｚ　＋　Ｈｔ　、１５分の条件
下でエピタキシャル成長を行ない、溝２内に半導体層と
してのエビダキンヤル成長層４を形成した（第１図ｆｄ
１図示）、更に、ＰＥＰ。Example 1 A 4-inch P-type silicon wafer (semiconductor substrate) 1 doped with Fuchelon and having a resistivity of 2 to 5 Ω was etched with a width of 10 μm using photoetching (PEP) and reactive ion etching (RIE). A groove 2 having a depth of 5 μm and a square planar shape was formed (as shown in FIG. 1(a)). Next, 1000℃
An oxide film 3 having a thickness of 7,500 mm as a first insulating film was formed on the surface of the substrate 1 including the bottom and side surfaces of the groove 2 by hydrogen combustion oxidation for 3 hours (see FIG. 1 (b1)).
The oxide film 3 on the side surfaces formed in the groove 2 was removed by PEP and wet etching (see Fig. 1 (01)).Then, as shown in Fig. 42 torr in the lateral direction, 1075℃
, SIClt Hz + Ht for 15 minutes to form an Evida kinial growth layer 4 as a semiconductor layer in the groove 2 (see Fig. 1fd).
1 shown), and further PEP.

ＲＩ　Ｅにより溝２の側面の、エピタキシャル成長層４
を除去して開口部（図示せず）を形成した後、この開口
部にＣＶ　Ｄ　（Ｃｈｅｍｉｃａｌ　ＶａｐｏｕｒＤｅ
ｐｏｓｉｔｉｏｎ）により第２の絶縁膜としてのＳｉｎ
。Epitaxially grown layer 4 on the side surface of trench 2 by RIE
After forming an opening (not shown) by removing CVD (Chemical VaporDe
position) as the second insulating film.
.

膜５を埋め込んでＳＯＩ構造の半導体基体を製造した（
第１図ｆｅ１図示）、。A semiconductor substrate with an SOI structure was manufactured by embedding the film 5 (
(shown in Figure 1 fe1).

しかして１本発明によれば、基板１に溝２を形成し、基
板表面に酸化膜３を形成した後、溝２の側面の酸化膜３
のみを除去し、更に基板１より横方向にエビクキンヤル
成長を行なって溝２内にエピタキシャル成長層４を形成
し、この後τ４２の側面の成長層４を除去し、この除去
部分に５ｉＯ１１９ｊ５を埋め込むため、エピタキシャ
ル層４の結晶性を良好にすることができる。According to the present invention, the groove 2 is formed in the substrate 1, the oxide film 3 is formed on the surface of the substrate, and then the oxide film 3 is formed on the side surface of the groove 2.
Then, epitaxial growth is performed laterally from the substrate 1 to form an epitaxial growth layer 4 in the groove 2. After that, the growth layer 4 on the side surface of τ42 is removed and the removed portion is filled with 5iO119j5. The crystallinity of the epitaxial layer 4 can be improved.

実施例２ 実施例１と比べ、第１図ｆｃ）で溝・２の側面の酸化膜
３を全て収り１洋＜代りに周囲の４面のうち１面だけを
取り除き、その他は実施例１と同様にして半導体基体を
製造した。この方法によれば、エピタキシャル成長を基
板１より第３図に示す如く溝の１側面から中心点Ｐに向
うように（矢印Ａ〕行なうことができ、実施例１と比ベ
エピタキシャル層４の結晶性を向上できる。なお、成長
は矢印Ｂ−Ｄのいずれかの方向でもよい。Example 2 Compared to Example 1, the oxide film 3 on the side surface of the groove 2 was completely removed in Figure 1 fc), and only one of the surrounding four surfaces was removed instead, and the rest were as in Example 1. A semiconductor substrate was manufactured in the same manner as described above. According to this method, epitaxial growth can be performed from one side of the groove toward the center point P (arrow A) from the substrate 1 as shown in FIG. Incidentally, the growth may be in either direction of arrows BD.

比較例１ 現在最も注目を集めているレーザアニール法でＳＯＩ構
造の半導体基体を製造した。Comparative Example 1 A semiconductor substrate having an SOI structure was manufactured using the laser annealing method, which is currently attracting the most attention.

比較例２ まず、実施例１と同じ半導体基板Ｉに厚さ７５００Ｘの
熱酸化膜２Ｉを形成した後、この熱酸化膜２ＩにＰＥＰ
によりｄ〕１０μｍ間隔に溝２２．２２を形成した（第
４図（ａ１図示）。つづいて、実施例１とほぼ同条件（
時間１７分）で選択エピタキシャル成長を行なってエピ
タキシャル成長層２３を形成した後、５ｉｎ２膜２４を
埋め込んで半導体基体を製造した（第４図ｆｂ）図示）
。Comparative Example 2 First, a thermal oxide film 2I with a thickness of 7500X was formed on the same semiconductor substrate I as in Example 1, and then PEP was applied to this thermal oxide film 2I.
Grooves 22.22 were formed at intervals of 10 μm (Fig. 4 (a1 diagram)).Continuously, under almost the same conditions as in Example 1 (
After forming an epitaxial growth layer 23 by selective epitaxial growth (time 17 minutes), a 5in2 film 24 was embedded to manufacture a semiconductor substrate (as shown in FIG. 4 fb).
.

ここで、上記の４つの半導体基体のエピタキシャル成長
層のシリコン結晶について評価を行なったところ、下記
表に示す結果となった。Here, when the silicon crystals of the epitaxial growth layers of the four semiconductor substrates mentioned above were evaluated, the results were shown in the table below.

表 この表より、結晶性は実施例２〉実施例１≧比較例２〉
比較例１の順に良いことが確認できる。Table From this table, the crystallinity is Example 2〉Example 1≧Comparative Example 2〉
It can be confirmed that the order of Comparative Example 1 is better.

なお、ここでは比較例として従来例のうちの２例を上げ
たが、その他の従来例ではいづれも本発明より劣るのは
明らかである。Although two conventional examples are shown here as comparative examples, it is clear that all other conventional examples are inferior to the present invention.

以下に、比較例として上げなかった従来例の本発明と比
べた欠点について述べると１次のようになる。Below, we will discuss the drawbacks of the conventional example, which was not listed as a comparative example, compared to the present invention.

（ａ）　　Ｆ　Ｉ　Ｐ　ＯＳ・・・溝の巾が最高１０μ
ｍでろる。(a) F I P OS...Maximum groove width is 10μ
It's m.

（ｂ）　　酸素チャネルイオン注入後エピタキシャル成
長を行なう方法・・・イオン注入する酸素の量を大きく
するのが困難。(b) Method of epitaxial growth after oxygen channel ion implantation: It is difficult to increase the amount of oxygen to be ion implanted.

（Ｃ）　　ラテラルエピタキシャル成長法・・・結晶性
が悪い。(C) Lateral epitaxial growth method: Poor crystallinity.

以上示したように、従来のどのＳ　ＯＩ　４．４造の作
製法と比較しても本発明法が優れている。As shown above, the method of the present invention is superior to any conventional SOI 4.4 fabrication method.

なお、上記実施例では、基板表面に酸化膜を形成した後
、溝の内側面金ての酸化膜を取シ除く場合（実施例１）
、あるいは溝の内側面のうち１面の酸化膜だけを取り除
く場合（実施例２〕についても夫々述べたが、これに限
らず、溝の内側面のうち２面もしくは３面の酸化膜だけ
を取シ除く場合でもよい。In the above example, after forming an oxide film on the substrate surface, the oxide film on the inner surface of the groove is removed (Example 1).
, or the case where only the oxide film on one of the inner surfaces of the groove is removed (Example 2) has been described, but the present invention is not limited to this. It is also possible to remove it.

また、上記実施例では％溝の側面のエピタキシャル層を
除去してここに８ｉ０．膜を埋め込む場合について述べ
たが、これに限らず、溝側面に沿う半導体基板もしくは
該基板とエピタキシャル層の両者を除去してここにＳｉ
ｎ、膜埋め込んでも実施例と同様の効果を期待できる。In the above embodiment, the epitaxial layer on the side surface of the trench is removed and the 8i0. Although the case of embedding a film has been described, the present invention is not limited to this, and the semiconductor substrate along the trench side surface or both the substrate and the epitaxial layer are removed and Si is buried here.
n. Even if the film is embedded, the same effect as in the example can be expected.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く本発明によれば、絶縁膜上に襞れた結
晶性を有する半導体層を容易に形成し得る半導体基体の
製造方法を提供できるものである。As described in detail above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor substrate in which a semiconductor layer having wrinkled crystallinity can be easily formed on an insulating film.

【図面の簡単な説明】[Brief explanation of drawings]

編１図（ａ）〜（ｅ）は本発明の一実施例に係る半導体
基体の製造方法を工程順に示す断面図、第２図及び第３
図は夫々エピタキシャル成長方向を示すための説明図、
第４図（ａ）　（ｂ）は比較例２に係る半導体基体の製
造方法を工程順に示す断面図である。 １・・・半導体基板、２・・・溝、３・・・酸化膜、４
・・・エピタキシャル層（半導体層）、５・・・Ｓｉｎ
。 膜。 出願人代理人　　弁理士　鈴　江　武　彦第１図　　　
　　Ｎ２図 （ａ）Figures 1 (a) to (e) are cross-sectional views showing the manufacturing method of a semiconductor substrate according to an embodiment of the present invention in order of steps, and Figures 2 and 3 are
The figures are explanatory diagrams to show the epitaxial growth direction, respectively.
FIGS. 4(a) and 4(b) are cross-sectional views showing the method for manufacturing a semiconductor substrate according to Comparative Example 2 in order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Groove, 3... Oxide film, 4
...Epitaxial layer (semiconductor layer), 5...Sin
. film. Applicant's agent Patent attorney Takehiko Suzue Figure 1
N2 diagram (a)

Claims (2)

【特許請求の範囲】[Claims] （１）半導体基板に溝を形成する工程と、この基板の表
面に第１の絶縁膜を形成する工程と、溝側面の第１の絶
縁膜を一部もしくは全部取り除く工程と、溝側面の半導
体基板から横方向に選択エピタキシャル成長を行なって
半導体層を形成する工程と、溝側面に沿う半導体基板も
しくは半導体層の少なくとも一方に開孔部を設けこれに
第２の絶縁膜を形成する工程とを具備することを特徴と
する半導体基体の製造方法。(1) A step of forming a groove in a semiconductor substrate, a step of forming a first insulating film on the surface of this substrate, a step of removing part or all of the first insulating film on the side surface of the groove, and a step of forming a semiconductor substrate on the side surface of the groove. The method includes a step of forming a semiconductor layer by performing selective epitaxial growth laterally from the substrate, and a step of forming an opening in at least one of the semiconductor substrate or the semiconductor layer along the side surface of the trench and forming a second insulating film therein. A method for manufacturing a semiconductor substrate, characterized in that: （２）溝の平面形状が四角形でかつ溝の４つの側面の第
１の絶縁膜のうち１つだけを取り除くことを特徴とする
特許請求の範囲第１項記載の半導体基体の製造方法。(2) The method of manufacturing a semiconductor substrate according to claim 1, wherein the groove has a rectangular planar shape and only one of the first insulating films on the four side surfaces of the groove is removed.