JPS615550A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS615550A JPS615550A JP12524484A JP12524484A JPS615550A JP S615550 A JPS615550 A JP S615550A JP 12524484 A JP12524484 A JP 12524484A JP 12524484 A JP12524484 A JP 12524484A JP S615550 A JPS615550 A JP S615550A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- layer
- interlayer insulating
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は多層配線構造を有する半導体装置に関し、主と
して高周波用リニアＩＣ（半導体集積回路装置）を対象
とする。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device having a multilayer wiring structure, and is mainly directed to a high frequency linear IC (semiconductor integrated circuit device).
ＩＣやＬＳＩ等の半導体装置において、１チツプあたり
の素子数が増大するに伴い、素子間を接続するアルミニ
ウム配線は一層構造では無理となり、２層以上の多層構
造が採用されている。この２層以上の配線間には層間絶
縁膜として、従来はシリコン酸化物やリンを含むガラス
等の無機絶縁材が使われていたが、厚膜に形成した場合
に熱歪を生じゃすく又、多層に形成すると配線による表
面段差が苔しくなった。このような無機絶縁膜に代って
低温処理でき１表面の平坦性を確保できる有機絶縁膜が
使われ、特に高耐熱性のポリイミド系高分子樹脂を層間
絶縁膜に用いた配線構造が採用されている。（特公昭５
７−３６７５９公報参照）。As the number of elements per chip increases in semiconductor devices such as ICs and LSIs, it has become impossible to use a single layer structure for aluminum wiring connecting the elements, and a multilayer structure of two or more layers has been adopted. Conventionally, inorganic insulating materials such as silicon oxide or glass containing phosphorus have been used as interlayer insulating films between these two or more layers of wiring, but when formed in a thick film, they may cause thermal distortion or , When multi-layered, the surface level difference due to wiring became mossy. Instead of such inorganic insulating films, organic insulating films that can be processed at low temperatures and ensure surface flatness are used, and in particular, wiring structures using highly heat-resistant polyimide polymer resin as interlayer insulating films are used. ing. (Tokuko Showa 5
(See Publication No. 7-36759).
このポリイミド樹脂、たと・えば芳香族ジアミンと、芳
香族テトラカルボン酸二無水物とを反応して得られる重
合物からなるボリイミ°ド樹脂を半導体基板上に層間絶
縁膜として形成する場合、ポリイミ樹脂のプレポリマー
溶液を配線の形成された前記基板表面にスピンナ塗布し
たのち、溶媒成分を蒸発させ、２００〜３００℃で熱処
理して重合硬化させて被膜を形成する。When forming this polyimide resin, for example, a polyimide resin made of a polymer obtained by reacting aromatic diamine and aromatic tetracarboxylic dianhydride, as an interlayer insulating film on a semiconductor substrate, polyimide resin After applying the prepolymer solution to the surface of the substrate on which the wiring is formed using a spinner, the solvent component is evaporated, and the prepolymer solution is polymerized and cured by heat treatment at 200 to 300° C. to form a film.
第１図はボリミイド樹脂を層間膜に使用した２層配線の
一例を示す断面図である。FIG. 1 is a sectional view showing an example of a two-layer wiring using a bolimide resin as an interlayer film.
１はシリコン結晶基板、２は表面酸化膜（ＳｉＯ□膜）
である。３は第１層アルミニウム配線で厚さｄ２が１．
７５μｍ程度とする。４はポリイミド樹脂からなる層間
膜で厚さｄｌは３．７５μｍ程度である。５は第２層ア
ルミニろム配線で層間膜４上に形成され、その一部にあ
けられたスルーホール６を通じて第１層アルミニウム配
線３に接続する。1 is a silicon crystal substrate, 2 is a surface oxide film (SiO□ film)
It is. 3 is the first layer aluminum wiring with a thickness d2 of 1.
The thickness is approximately 75 μm. 4 is an interlayer film made of polyimide resin and has a thickness dl of about 3.75 μm. A second layer aluminum wiring 5 is formed on the interlayer film 4, and is connected to the first layer aluminum wiring 3 through a through hole 6 formed in a part thereof.
このような２層配線構造において層間膜４は前記したよ
うにスピンナ塗布されて全面が平坦化しでいるため、第
１層アルミニウム配線３の上の層間膜の厚さｄ３は１．
０〜２．５μｍときわめて薄い被膜となり、この上に第
２層アルミニウム配線５が形成されていると、配線間容
量が大きくなる。In such a two-layer wiring structure, the interlayer film 4 is coated with a spinner as described above and the entire surface is flattened, so the thickness d3 of the interlayer film on the first layer aluminum wiring 3 is 1.
The film is extremely thin, ranging from 0 to 2.5 μm, and if the second layer aluminum wiring 5 is formed on top of this, the capacitance between the wirings becomes large.
このように配線間容量が大きいと配線間でクロストーク
や発振遅延を生じやすいことがあきらかとされた。特に
、高周波用リニアＩＣにおいて、たとえば、ボリミイド
系樹脂を層間絶縁膜として多層配線構造を形成する場合
に上記クロストークや発振遅延が生じてしまうため、多
層配線構造が採用されていないことが本発明者よりあき
らかとされた。It has been found that when the inter-wiring capacitance is large as described above, crosstalk and oscillation delay are likely to occur between the wirings. In particular, in high-frequency linear ICs, for example, when a multilayer wiring structure is formed using a borimide resin as an interlayer insulating film, the above-mentioned crosstalk and oscillation delay occur, so the present invention does not employ a multilayer wiring structure. It was made clear by the person.
本発明は上記問題を解決したものである。した
１カ、７□□。−ｖ ｃＦ） ＠ ｆｆ−ｒ Ｌよ
工□１１．ア、。 ｉ□でアルミニウム配線の２
層以上の多層構造を実現することにある。□本発明の他
の目的はＩＣチップせイズの縮小化にある。The present invention solves the above problems. did
1ka, 7□□. -v cF) @ ff-r L yo engineering □11. a,. Aluminum wiring 2 with i□
The goal is to realize a multilayer structure with more than one layer. □Another object of the present invention is to reduce the size of an IC chip.
本発明め前記ならびにそのほかの目的と新規な特徴は１
本明細書の記述および添付図面よりあきらかになるであ
ろう。The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the attached drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。すなわち、
半導体基体上に第１層配線と第２層配線とがポリイミド
樹脂等の有機性層間絶縁膜を介して形成された多層配線
構造において、第１層配・線と第２層配線とが交差する
部分の上記層間絶縁膜が他の部分の層間絶縁膜よりも厚
く形成され交差する部分の第１層配線上の層間絶縁膜を
充分の厚さをもたせ諷ことにより第１層・第２層の配線
間のクロストークや発振遅延を防ぐことかで−き発明の
目的を達成するものである。A brief overview of typical inventions disclosed in this application is as follows. That is,
In a multilayer wiring structure in which a first layer wiring and a second layer wiring are formed on a semiconductor substrate via an organic interlayer insulating film such as a polyimide resin, the first layer wiring and the second layer wiring intersect with each other. The above-mentioned interlayer insulating film in some parts is formed thicker than the interlayer insulating film in other parts, and by making the interlayer insulating film on the first layer wiring in the intersecting parts sufficiently thick, the first and second layers are The object of the invention is achieved by preventing crosstalk between wiring lines and oscillation delay.
第２図は本発明の一実施例を示すものであって。 FIG. 2 shows an embodiment of the present invention.
第１図に対応する多層配線構造を有する半導体装置の縦
断面図である。同図において第１図を共通の構成部分に
は同じ指示番号記号が附しである。FIG. 2 is a longitudinal cross-sectional view of a semiconductor device having a multilayer wiring structure corresponding to FIG. 1; In this figure, the same reference numbers and symbols are attached to the same components as in FIG. 1.
３’（３ａ、 ３ ｂ、 Ａ ｃ’）は第１層アルミニ
ウム配線でこのうち３ ｂ’は第２層アルミニウム配線
５と′交差する。４はポリイミド樹脂からなる層間絶縁
膜で、この上に第２層アルミニウム配線５が形成され層
間膜４の一部にあけたスルーホール６を通じて第１層ア
ルミニウム配線３ａと接続される６７は第２層アルミニ
ウム配線５を覆うように形成されポリイミド樹脂からな
るプロテクシ目ン（保護用）膜である。なお第２層アル
ミニウム配線５は第１層アルミニウム配線３ｃとは交差
しないものとする。3' (3a, 3b, A c') are first layer aluminum wirings, and 3b' intersects with the second layer aluminum wiring 5. 4 is an interlayer insulating film made of polyimide resin, on which a second layer aluminum wiring 5 is formed and connected to the first layer aluminum wiring 3a through a through hole 6 made in a part of the interlayer film 4; This is a protection film formed to cover the layered aluminum wiring 5 and made of polyimide resin. Note that the second layer aluminum wiring 5 does not intersect with the first layer aluminum wiring 3c.
上記ポリイミド樹脂からなる層間絶縁膜４は第１層配線
３ｂと第２層配線５とが交差する部分の厚さく酸化膜２
と接する部分からの厚さ）ｄ４は第２層配線５が第１層
配線と交差しない他の部分の厚さｄ４と交差する部分の
第１層配線３ｂの厚さｄ２との差ｄ’、−ｄ２＝ｄ３を
配線間寄生容量を小さくするに充分な厚さ、たとえばｄ
３＝３．０μｍ以上とする。The interlayer insulating film 4 made of polyimide resin has a thickness of oxide film 2 at the intersection of the first layer wiring 3b and the second layer wiring 5.
d4 is the difference d' between the thickness d4 of the other part where the second layer wiring 5 does not intersect with the first layer wiring and the thickness d2 of the first layer wiring 3b of the part where it intersects, -d2=d3 is set to a thickness sufficient to reduce the parasitic capacitance between wirings, for example, d
3=3.0 μm or more.
第３図乃至第７図は本発明による多層配線構造（第２図
に対応する）を有する半導体装置の製造プロセスを示す
工程断面図である。以下、各工程に従って説明する。3 to 7 are process cross-sectional views showing the manufacturing process of a semiconductor device having a multilayer wiring structure (corresponding to FIG. 2) according to the present invention. Each step will be explained below.
（１）第３図に示すようにシリコン結晶基体１を用意し
、この基体１の主面に図示されない半導体素子を形成し
、その際に形成された表面酸化膜２上にアルミニウムを
蒸着（又はスパッタ）し、パターニングエッチすること
により厚さｄ２＝１．７５μｍの第１層アルミニウム配
線３ａ、３ｂ、３ｃを形成する。このうち配線３ｂは上
層の配線と交差することになる。(1) As shown in FIG. 3, a silicon crystal substrate 1 is prepared, a semiconductor element (not shown) is formed on the main surface of this substrate 1, and aluminum is vapor-deposited (or Sputtering) and patterning etching are performed to form first layer aluminum interconnections 3a, 3b, and 3c having a thickness d2=1.75 μm. Of these, the wiring 3b intersects with the wiring in the upper layer.
（２）第４図に示すようにこの上にポリイミド樹脂を厚
めに塗布し、硬化後の厚さがたとえばｄ４＝５．０μｍ
程度となるように層間絶縁膜４を形成する。(2) As shown in Figure 4, a polyimide resin is applied thickly on this, and the thickness after curing is, for example, d4 = 5.0 μm.
The interlayer insulating film 4 is formed to a certain extent.
この絶縁膜４はポリイミド樹脂のプリポリマー溶液又は
半重合溶液（たとえばＮ−メチル−２ピロリドンもしく
はＮ−Ｎ−ジメチルアセトアミドなどを溶液とする）を
基本表面にスピンナ塗布したのち、溶媒成分を蒸発させ
、さらに２００〜３００℃で熱処理して硬化させて上記
厚さｄ４をもつポリイミド被膜を形成する。This insulating film 4 is formed by applying a prepolymer solution or a semi-polymer solution of polyimide resin (for example, N-methyl-2-pyrrolidone or N-N-dimethylacetamide as a solution) to the basic surface using a spinner, and then evaporating the solvent component. , and then heat-treated at 200 to 300° C. to form a polyimide film having the above-mentioned thickness d4.
（３）ホトレジスト材を塗布し、露光ご現像処理によっ
て２層配線の交差部、特に人、出力ラインのアルミ・ラ
ム２層配線交差部等寄生容量がｉ性上問題となる部分、
例えば配線３ｂの上部ホトレジストマスク８を形成し、
このマスクを用いて第５図に示すようにポリイミド被膜
４の一部を選択的にエッチする。この選択はエッチによ
り配線３ｂ等の問題個所以外の部分のポリイミド被膜４
の厚さｄｌは３，７５μｍ程度となる。(3) Apply a photoresist material, expose and develop the parts where parasitic capacitance is problematic, such as the intersections of two-layer wiring, especially the intersections of two-layer wiring between people and output lines, etc.
For example, forming the upper photoresist mask 8 of the wiring 3b,
Using this mask, a portion of the polyimide film 4 is selectively etched as shown in FIG. This selection is done by etching the polyimide film 4 in areas other than problem areas such as the wiring 3b.
The thickness dl is approximately 3.75 μm.
（４）あらたにホトレジスト材を塗布し、露光、現像処
理によって、配線３ａの上部以外の部分にホト、レジス
トマスク９を形成し、このマスクを用いて第６図に示す
ようにポリイミド被膜４の一部を選択的にエッチするこ
とにより、配線３ａが露 １出するように
スルーホール６を開ける。(4) Apply a new photoresist material, and use exposure and development to form a photoresist mask 9 on the parts other than the upper part of the wiring 3a, and use this mask to form a polyimide film 4 as shown in FIG. By selectively etching a portion, a through hole 6 is opened so that the wiring 3a is exposed.
（５）アルミニウム膜を蒸着法又はスパッタ（リング法
）により基板１上に形成し、パターニング・エッチする
ことにより、第７図に示すように第２層アルミニウム配
線５を形成する。この第２Ｍアルミニウム配線は第８図
に平面図で示すようにスルーホール６を通じて第１層ア
ルミニウム配線３ａに接続し、他の第１層アルミニウム
配線３ｂには交差するように重なり、また、他の第１層
アルミニウム配＠３ｃには重なり合わないものとする。(5) An aluminum film is formed on the substrate 1 by vapor deposition or sputtering (ring method), and patterned and etched to form the second layer aluminum wiring 5 as shown in FIG. As shown in the plan view in FIG. 8, this 2M aluminum wiring is connected to the first layer aluminum wiring 3a through the through hole 6, overlaps other first layer aluminum wiring 3b so as to cross it, and also connects to the other first layer aluminum wiring 3b. It is assumed that there is no overlap with the first layer aluminum layer @3c.
このあとポリイミド樹脂を全面に塗布し、第２図に示す
ようにプロテクション膜７を形成する。Thereafter, polyimide resin is applied to the entire surface to form a protection film 7 as shown in FIG.
このプロテクション用のポリイミド樹脂の形成は工程（
２）で述べた場合と同様の工程により行われる。The formation of this protective polyimide resin is a process (
This is carried out by the same process as described in 2).
以上実施例で説明した本発明によれば、下記の理由下前
記発明の目的が達成できる。According to the present invention described in the embodiments above, the object of the invention can be achieved for the following reasons.
（１）第１層と第２層のアルミニウム配線が層間膜を介
して交差する部分では層間膜であるポリイミド膜４の厚
さはたとえばｄ４−ｄ２＝３．０μｍｌ程度と充分に厚
く形成できるため゛Ｊ寄生容量によるクロストークや発
振遅延を防止することが出来る。(1) At the part where the aluminum wiring of the first layer and the second layer intersect via the interlayer film, the polyimide film 4 which is the interlayer film can be formed sufficiently thick, for example, about d4-d2 = 3.0 μml. Crosstalk and oscillation delay due to J parasitic capacitance can be prevented.
（２）第１層と第２層のアルミニウム配線が層間膜を介
して交差する部分以外では層間膜の厚さを薄く形成する
ことにより、たとえばスルーホールの形成が容易であり
、又、それにより寄生容量の問題はない。(2) By forming the interlayer film thinner in areas other than the parts where the aluminum wiring of the first layer and the second layer intersect via the interlayer film, it is easy to form through holes, for example. There is no problem with parasitic capacitance.
（３）上記（１）、（２）により、高周波用リニアＩＣ
において、アルミニウム２層配［１）造が可能となると
いう効果を有する。(3) According to (1) and (2) above, high frequency linear IC
This has the effect that a two-layer aluminum structure [1] is possible.
（４）上記（３）によりＩＣのチップサイズ縮小化（例
えば１０〜２０％程度の縮小）が可能となる。(4) Due to the above (3), it is possible to reduce the chip size of the IC (for example, about 10 to 20% reduction).
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、第１層配線と第２層配線とが層間絶縁膜を介
して交差する部分でその層間絶縁膜の上に有機樹脂を選
択的に堆積させることにより上記絶縁物の他の部分より
も厚く形成するようにしてもよい。この場合の有機樹脂
は上記層間絶縁膜とはエッチ性において異なる材質のも
のを選ぶか、又は同じ材質を使い、ホトレジストを用い
たりフトオフ法により選択的に堆積させるようにするこ
とができる。For example, by selectively depositing an organic resin on the interlayer insulating film at a portion where the first layer wiring and the second layer wiring intersect with each other via the interlayer insulating film, the thickness of the insulator is thicker than in other parts of the insulator. It may also be formed. In this case, the organic resin may be made of a material different in etchability from the interlayer insulating film, or the same material may be used and selectively deposited using photoresist or a foot-off method.
本発明は高周波用リニアＩＣ全般に適用することができ
、たとえばＦＭ９！振回路振子路ビジョン発振回路に応
用して有効である。The present invention can be applied to all high frequency linear ICs, such as FM9! It is effective when applied to a vision oscillation circuit.
又、本発明は２層以上の多層配線構造の場合にも同様に
適用することができる。Further, the present invention can be similarly applied to a multilayer wiring structure having two or more layers.
第１図は２層配線構造の一例を示す縦断面図である。
第２図は本発明の一実施例を示すものであって。
多層配線構造を有する半導体装置の縦断面図である。
第３図は乃至第７図は本発明の一実施例を示すものであ
って、第２図に示された多層配線構造を有する半導体装
置の製造プロセスの工程断面図である。
第８図は多層配線構造を有する半導体装置の平面図であ
ってそのＡ−Ａ ’断面に第７図が対応する。
■・・・シリコン半導体基体、２・・・表面酸化膜、３
ａ、３ｂ・・・第１層アルミニウム配線、４・・・層間
絶縁膜（ポリイミド樹脂）、５・・・第２層アルミニウ
ム配線、６・・・スルーホール、７・・・プロテクショ
ン（ポリイミド樹脂）。
第 １ 図
第 ２ 図
第 ３ 図
第 ４ 図
第 ５ 図FIG. 1 is a longitudinal sectional view showing an example of a two-layer wiring structure. FIG. 2 shows an embodiment of the present invention. 1 is a longitudinal cross-sectional view of a semiconductor device having a multilayer wiring structure. 3 to 7 show one embodiment of the present invention, and are process sectional views of a manufacturing process of a semiconductor device having the multilayer wiring structure shown in FIG. 2. FIG. 8 is a plan view of a semiconductor device having a multilayer wiring structure, and FIG. 7 corresponds to the AA' cross section thereof. ■...Silicon semiconductor substrate, 2...Surface oxide film, 3
a, 3b... First layer aluminum wiring, 4... Interlayer insulating film (polyimide resin), 5... Second layer aluminum wiring, 6... Through hole, 7... Protection (polyimide resin) . Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Claims (1)
配線とが形成された多層配線構造を有する半導体装置で
あって、上層配線と下層配線とが層間絶縁膜を介して交
差する部分でその層間絶縁膜が他の部分の層間絶縁膜よ
りも選択的に厚く形成されていることを特徴とする半導
体装置。 ２、上記層間絶縁膜は有機性樹脂よりなる特許請求の範
囲第１項に記載の半導体装置。 ３、半導体基体上に層間絶縁膜を介して上層配線と下層
配線とが形成された多層配線構造を有する半導体装置の
製造方法であって、前記上層配線と下層配線とが交差す
る部分の層間絶縁膜を選択的に厚く形成する工程を含む
ことを特徴とする半導体装置の製造方法。 ４、上記工程は、上層配線と下層配線とが交差する部分
の層間絶縁膜を除いて選択的に除去する工程である特許
請求の範囲第３項記載の半導体装置の製造方法。 ５、上記工程上層配線と下層配線とが交差する部分のみ
に層間絶縁膜を選択的に堆積させる工程である特許請求
の範囲第３項記載の半導体装置の製造方法。[Claims] 1. A semiconductor device having a multilayer wiring structure in which upper layer wiring and lower layer wiring are formed on a semiconductor substrate with an interlayer insulating film interposed therebetween, the upper layer wiring and the lower layer wiring having an interlayer insulating film between them. 1. A semiconductor device characterized in that an interlayer insulating film is selectively formed thicker at a portion where the interlayer insulating film intersects with the interlayer insulating film than at other portions. 2. The semiconductor device according to claim 1, wherein the interlayer insulating film is made of an organic resin. 3. A method for manufacturing a semiconductor device having a multilayer wiring structure in which an upper layer wiring and a lower layer wiring are formed on a semiconductor substrate via an interlayer insulating film, the method comprising interlayer insulation at a portion where the upper layer wiring and the lower layer wiring intersect. A method for manufacturing a semiconductor device, comprising a step of selectively forming a thick film. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step is a step of selectively removing the interlayer insulating film except for the portion where the upper layer wiring and the lower layer wiring intersect. 5. The method of manufacturing a semiconductor device according to claim 3, wherein said step is a step of selectively depositing an interlayer insulating film only at the portion where the upper layer wiring and the lower layer wiring intersect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12524484A JPS615550A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12524484A JPS615550A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS615550A true JPS615550A (en) | 1986-01-11 |
Family
ID=14905341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12524484A Pending JPS615550A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615550A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01193164A (en) * | 1987-12-08 | 1989-08-03 | Fein Verwaltung Gmbh | Portable type machine tool with operating spindle having automatic locking action |
| JPH036833U (en) * | 1989-06-07 | 1991-01-23 | ||
| JP2010271519A (en) * | 2009-05-21 | 2010-12-02 | Ricoh Co Ltd | Display device |
-
1984
- 1984-06-20 JP JP12524484A patent/JPS615550A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01193164A (en) * | 1987-12-08 | 1989-08-03 | Fein Verwaltung Gmbh | Portable type machine tool with operating spindle having automatic locking action |
| JPH0661694B2 (en) * | 1987-12-08 | 1994-08-17 | ファイン−フェルバルツング ゲゼルシャフト ミット ベシュレンクテル ハフツング | Portable machine tool with working spindle with self-locking action |
| JPH036833U (en) * | 1989-06-07 | 1991-01-23 | ||
| JP2010271519A (en) * | 2009-05-21 | 2010-12-02 | Ricoh Co Ltd | Display device |
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