JPH061795B2 - Multilayer wiring structure - Google Patents
Multilayer wiring structureInfo
- Publication number
- JPH061795B2 JPH061795B2 JP61110582A JP11058286A JPH061795B2 JP H061795 B2 JPH061795 B2 JP H061795B2 JP 61110582 A JP61110582 A JP 61110582A JP 11058286 A JP11058286 A JP 11058286A JP H061795 B2 JPH061795 B2 JP H061795B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- wiring
- wiring structure
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の配線構造に係り、特に高集積の
半導体集積回路に好適な多層配線構造体に関する。TECHNICAL FIELD The present invention relates to a wiring structure of a semiconductor device, and more particularly to a multilayer wiring structure suitable for a highly integrated semiconductor integrated circuit.
ＬＳＩ（大規模集積回路）に対する集積度向上の要求は
とどまるところを知らず、これに伴って基板面での配線
量は増加し、この結果、多層配線時での表面段差はます
ます酷くなる。There is no end to the demand for higher integration of LSIs (Large Scale Integrated Circuits), and the amount of wiring on the board surface increases accordingly. As a result, the surface step difference in multi-layer wiring becomes more and more severe.
同時に、配線の積層数の増加要求も著しくなり、このた
め、ＬＳＩの高集積化には、平坦性に優れた多層配線構
造が不可欠である。At the same time, the demand for an increase in the number of wiring layers is also significant. Therefore, a multi-layer wiring structure excellent in flatness is indispensable for high integration of LSI.
ところで、このような多層配線構造に関する従来技術と
しては、配線層を区画する絶縁膜（層間膜）として有機
質材料であるポリイミド樹脂を用いるものが、例えば、
特開昭５７−１７７５４０号公報などにより、又、無機
質膜の上に有機質膜を積層したものを用いるものが、例
えば、特開昭５８−１９７８４６号公報などによりそれ
ぞれ開示されている。By the way, as a conventional technique relating to such a multilayer wiring structure, one using a polyimide resin, which is an organic material, as an insulating film (interlayer film) for partitioning the wiring layer is, for example,
JP-A-57-177540 and the like, and those using an organic film laminated on an inorganic film are disclosed, for example, in JP-A-58-197846.
しかしながら、これら従来技術では、３層以上の多層化
を対象としていなかった。However, these prior arts have not been intended for multi-layering of three or more layers.
上記従来技術では、３層以上の多層配線構造について配
慮されておらず、このため、従来技術により、ＬＳＩの
配線構造の３層以上の多層化を図ると、外部からのスト
レスにより有機質膜が変形し、配線に断線が生じ易く、
かつ、この有機質膜のため耐湿性も低下し易くなるた
め、充分な信頼性が得難いという問題点があった。In the above-mentioned conventional technique, no consideration is given to a multilayer wiring structure having three or more layers. Therefore, when the wiring structure of the LSI is made to have three or more layers by the conventional technique, the organic film is deformed due to external stress. , The wiring is likely to be broken,
In addition, since this organic film also tends to reduce the moisture resistance, there is a problem that it is difficult to obtain sufficient reliability.
本発明の目的は、上記した従来技術の問題点に対処し、
３層以上の多層化に際して充分な平坦性を保ちながら、
外部からのストレスに強く、かつ、耐湿性低下の虞れも
なく、ＬＳＩの高集積化を充分に図ることができる多層
配線構造体を提供することにある。The object of the present invention is to address the above-mentioned problems of the prior art,
While maintaining sufficient flatness when making multiple layers of 3 or more,
An object of the present invention is to provide a multi-layer wiring structure that is highly resistant to external stress and has no risk of deterioration in moisture resistance, and that can sufficiently achieve high integration of LSI.
上記目的は、本発明によれば、基板面上で３層以上の配
線層を区画する絶縁層の少なくとも１層として、有機質
膜の上に無機質膜を積層した薄膜層を用いることにより
達成される。According to the present invention, the above-mentioned object is achieved by using a thin film layer in which an inorganic film is laminated on an organic film as at least one insulating layer that divides three or more wiring layers on the substrate surface. .
絶縁層を形成する有機質膜は、配線層を形成すべき面で
の平坦性を確保する働きをし、無機質膜は、耐ストレス
性と耐湿性を確保する働きをするので、信頼性の低下を
伴うことなく、充分に高集積化を図ることができる。The organic film forming the insulating layer functions to secure the flatness on the surface on which the wiring layer is to be formed, and the inorganic film functions to secure the stress resistance and the moisture resistance, so that the reliability is lowered. It is possible to achieve sufficiently high integration without being accompanied by it.
以下、本発明による多層配線構造体について、図示の実
施例により詳細に説明する。Hereinafter, the multilayer wiring structure according to the present invention will be described in detail with reference to the illustrated embodiments.
第１図は本発明の一実施例で、この実施例は、配線層が
４層にわたって設けられた半導体装置に対して本発明を
適用した場合のもので、図において、１０はシリコン基
板で、酸化膜１１、第１ゲート電極１２、第２ゲート電
極１３などによる段差パターンを有するものとなってお
り、この面に第１層配線２０が形成されている。FIG. 1 is an embodiment of the present invention, which is a case where the present invention is applied to a semiconductor device having four wiring layers, in which 10 is a silicon substrate, It has a step pattern formed by the oxide film 11, the first gate electrode 12, the second gate electrode 13, etc., and the first layer wiring 20 is formed on this surface.
３０は第１層絶縁膜で、ポリイミド樹脂を回転法によっ
て塗布し、図示のように、その上面が平坦な面として得
られるようにする。Reference numeral 30 denotes a first-layer insulating film, which is formed by applying a polyimide resin by a rotating method so that the upper surface thereof is obtained as a flat surface as shown in the drawing.
４０は第２層配線で、第１層絶縁膜３０にスルーホール
加工をした上で、この上面に形成される。A second layer wiring 40 is formed on the upper surface of the first layer insulating film 30 after the first layer insulating film 30 is processed with through holes.
５０は第２層絶縁膜で、この時点では、段差は第２層配
線４０によるものだけであるので、あまり大きくはない
から、この第２層絶縁膜５０は、シリコンなど適当な金
属の酸化物、ＳＯＧ、リンガラスなどの無機質材料で構
成される。Reference numeral 50 denotes a second-layer insulating film. At this point, since the step is only due to the second-layer wiring 40, it is not so large. Therefore, the second-layer insulating film 50 is an oxide of an appropriate metal such as silicon. , SOG, phosphorous glass, and other inorganic materials.
６０は第３層配線で、第２層絶縁膜５０にスルーホール
加工をした上で、その上面に形成されている。Reference numeral 60 denotes a third-layer wiring, which is formed on the upper surface of the second-layer insulating film 50 after the second-layer insulating film 50 has been through-hole processed.
７０は第３層絶縁膜である。70 is a third layer insulating film.
しかして、この時点に至ると、段差は第２層配線４０と
第３層配線６０によるものとなり、かなり大きな厳しい
段差となっている。そこで、この第３層絶縁膜７０とし
ては、第１層絶縁膜３０と同じポリイミド樹脂による有
機質のものを用い、充分な平坦性が与えられるようにす
る。At this point, however, the level difference is due to the second layer wiring 40 and the third layer wiring 60, which is a fairly large and severe step. Therefore, as the third layer insulating film 70, the same organic material made of the same polyimide resin as the first layer insulating film 30 is used so that sufficient flatness can be provided.
８０は第４層配線で、第３層絶縁膜７０にスルーホール
加工した後、その上に形成される。そして、その表面に
は、無機質材料からなる保護膜９０が形成される。Reference numeral 80 denotes a fourth layer wiring, which is formed on the third layer insulating film 70 after the through hole processing. Then, a protective film 90 made of an inorganic material is formed on the surface thereof.
この実施例によれば、第１層と第３層の絶縁膜３０、７
０としてポリイミド樹脂による有機質の膜を用いている
ので、配線層を３層以上にわたって設けたにもかかわら
ず、それぞれの配線層を設けるべき表面での平坦性が充
分に確保でき、半導体装置の高集積化を一層図ることが
できる。According to this embodiment, the first and third insulating films 30, 7 are formed.
Since an organic film made of a polyimide resin is used as 0, even if three or more wiring layers are provided, the flatness on the surface where each wiring layer should be provided can be sufficiently ensured, and the high level of the semiconductor device can be obtained. Further integration can be achieved.
また、この実施例によれば、第２層絶縁膜５０として無
機質の膜が用いられているため、外部からのストレスに
強く、さらに、この第２層絶縁膜５０のほか保護膜９０
にも無機質膜が用いられているため、耐湿性も充分に保
つことができる。Further, according to this embodiment, since the inorganic film is used as the second-layer insulating film 50, it is resistant to external stress, and the protective film 90 in addition to the second-layer insulating film 50.
Also, since an inorganic film is used, sufficient moisture resistance can be maintained.
さらに、この実施例では、第１層絶縁膜３０としてポリ
イミド樹脂膜を用いているため、その表面に第２層絶縁
膜５０を形成する際に、プラズマ法などを用いても、ダ
メージの虞れがなく、製造が容易である。Furthermore, in this embodiment, since the polyimide resin film is used as the first-layer insulating film 30, even if a plasma method or the like is used when forming the second-layer insulating film 50 on the surface, damage may occur. And easy to manufacture.
次に、第２図は、本発明の他の一実施例で、この実施例
は、第１図の実施例における有機質材料からなる第１と
第３の絶縁膜３０、７０の代りに、有機質膜３１、７１
と、これらの表面にそれぞれ形成した無機質膜３２、７
２のそれぞれからなる積層膜３０’，７０’とを設け、
これらの積層膜３０’，７０’をそれぞれ第１と第２の
絶縁膜としたものである。そして、この実施例では、有
機質膜３１、７１としてポリイミド樹脂膜を、そして、
無機質膜３２、７２としてプラズマ法による酸化膜をそ
れぞれ用いたものである。Next, FIG. 2 shows another embodiment of the present invention. In this embodiment, instead of the first and third insulating films 30 and 70 made of the organic material in the embodiment of FIG. Membrane 31, 71
And the inorganic films 32 and 7 formed on these surfaces, respectively.
And a laminated film 30 ', 70' composed of 2 respectively,
These laminated films 30 'and 70' are used as first and second insulating films, respectively. Then, in this embodiment, a polyimide resin film is used as the organic films 31 and 71, and
As the inorganic films 32 and 72, oxide films formed by the plasma method are used.
従って、この実施例によっても、配線層形成面での平坦
性は、第１と第３の絶縁層３０’、７０’を形成する有
機質膜３１、７１によって充分に確保され、かつ、外部
ストレスに対しては、無機質膜からなる第２層絶縁膜５
０が有効に機能する上、保護膜９０に加えて各層間にも
無機質膜３２、７２が設けられているので、さらに優れ
た耐湿性を与えることができる。Therefore, also in this embodiment, the flatness on the wiring layer forming surface is sufficiently secured by the organic films 31 and 71 forming the first and third insulating layers 30 ′ and 70 ′, and the external stress is prevented. On the other hand, the second layer insulating film 5 made of an inorganic film is used.
0 functions effectively, and since the inorganic films 32 and 72 are provided between the layers in addition to the protective film 90, it is possible to provide further excellent moisture resistance.
なお、以上の実施例は、いずれも配線が４層に設けられ
ている場合について説明したが、本発明は、これに限る
ことなく実施可能なことは言うまでもないところであ
る。In addition, in each of the above-described embodiments, the case where the wiring is provided in four layers has been described, but it goes without saying that the present invention can be implemented without being limited to this.
以上説明したように、本発明によれば、配線層を区画す
る絶縁膜として、有機質のものと、無機質のものとを用
いることにより、段差の平坦化と、ストレスに対する抵
抗力増大および耐湿性保持の両立とを可能にしたから、
半導体集積回路の配線層の多層化に伴なう段差の問題に
充分に対処しながら、高い信頼性を保つことができ、半
導体集積回路の高集積化に大きく役立つ多層配線構造体
を容易に提供することができる。As described above, according to the present invention, by using an organic film and an inorganic film as an insulating film for partitioning a wiring layer, the steps are flattened, the resistance to stress is increased, and the moisture resistance is maintained. Because it is possible to achieve both
It is possible to easily provide a multilayer wiring structure which can maintain high reliability while sufficiently dealing with the problem of a step due to the multilayering of wiring layers of a semiconductor integrated circuit and which is greatly useful for high integration of a semiconductor integrated circuit. can do.
第１図は本発明による多層配線構造体の一実施例を示す
断面図、第２図は同じく他の一実施例を示す断面図であ
る。 １０‥‥シリコン基板、１１‥‥酸化膜、１２‥‥第１
ゲート電極、１３‥‥第２ゲート電極、２０‥‥第１層
配線、３０‥‥第１層絶縁膜、４０‥‥第２層配線、５
０‥‥第２層絶縁膜、６０‥‥第３層配線、７０‥‥第
３層絶縁膜、８０‥‥第４層配線、９０‥‥保護膜。FIG. 1 is a sectional view showing an embodiment of the multilayer wiring structure according to the present invention, and FIG. 2 is a sectional view showing another embodiment of the same. 10 ... Silicon substrate, 11 ... Oxide film, 12 ... First
Gate electrode, 13 ... Second gate electrode, 20 ... First layer wiring, 30 ... First layer insulating film, 40 ... Second layer wiring, 5
0 ... Second layer insulating film, 60 ... Third layer wiring, 70 ... Third layer insulating film, 80 ... Fourth layer wiring, 90 ... Protective film.
Claims (4)
くとも３層の配線層を備えた多層配線構造体において、
上記絶縁層の少なくとも１層が有機質膜の上に無機質膜
を積層した薄膜層で形成されていることを特徴とする多
層配線構造体。1. A multi-layer wiring structure comprising a substrate surface and at least three wiring layers laminated with an insulating layer sandwiched between them.
At least one layer of the above-mentioned insulating layer is formed by a thin film layer in which an inorganic film is laminated on an organic film, which is a multilayer wiring structure.
層間の絶縁層として、更に、無機質膜からなる薄膜層で
形成されている絶縁層を有し、上記有機質膜の上に無機
質膜を積層した薄膜層で形成されている絶縁層と、上記
無機質膜からなる薄膜層で形成されている絶縁層とは、
上記基板面に対して交互に積層されていることを特徴と
する多層配線構造体。2. The insulating film between the wiring layers according to claim 1, further comprising an insulating layer formed of a thin film layer made of an inorganic film, wherein the inorganic film is formed on the organic film. An insulating layer formed of laminated thin film layers and an insulating layer formed of a thin film layer formed of the inorganic film,
A multilayer wiring structure characterized by being alternately laminated on the substrate surface.
の配線層のうちの最も外側にある配線層が、無機質膜か
らなる保護層を備えていることを特徴とする多層配線構
造体。3. The multilayer wiring structure according to claim 1, wherein the outermost wiring layer of the three wiring layers is provided with a protective layer made of an inorganic film. .
質薄膜層がポリイミド樹脂で構成されていることを特徴
とする多層配線構造体。4. A multilayer wiring structure according to claim 1, wherein the organic thin film layer is composed of a polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61110582A JPH061795B2 (en) | 1986-05-16 | 1986-05-16 | Multilayer wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61110582A JPH061795B2 (en) | 1986-05-16 | 1986-05-16 | Multilayer wiring structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62268144A JPS62268144A (en) | 1987-11-20 |
| JPH061795B2 true JPH061795B2 (en) | 1994-01-05 |
Family
ID=14539492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61110582A Expired - Lifetime JPH061795B2 (en) | 1986-05-16 | 1986-05-16 | Multilayer wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH061795B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5376590A (en) * | 1992-01-20 | 1994-12-27 | Nippon Telegraph And Telephone Corporation | Semiconductor device and method of fabricating the same |
| US5486493A (en) * | 1994-02-25 | 1996-01-23 | Jeng; Shin-Puu | Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators |
| US5500534A (en) * | 1994-03-31 | 1996-03-19 | Iowa State University Research Foundation | Integrated energy-sensitive and position-sensitive x-ray detection system |
| JPH09129727A (en) * | 1995-10-30 | 1997-05-16 | Nec Corp | Semiconductor device and manufacturing method thereof |
| US6054769A (en) * | 1997-01-17 | 2000-04-25 | Texas Instruments Incorporated | Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials |
| US5818111A (en) * | 1997-03-21 | 1998-10-06 | Texas Instruments Incorporated | Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979190A (en) * | 1972-12-04 | 1974-07-31 | ||
| JPS5877245A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS5974651A (en) * | 1982-10-22 | 1984-04-27 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-05-16 JP JP61110582A patent/JPH061795B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62268144A (en) | 1987-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2964537B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH061795B2 (en) | Multilayer wiring structure | |
| JPS63260054A (en) | Semiconductor integrated circuit device | |
| JPH0832244A (en) | Multilayer wiring board | |
| JPH0612789B2 (en) | Semiconductor device | |
| JP2867488B2 (en) | Semiconductor device | |
| JPH10154808A (en) | Semiconductor device and manufacture thereof | |
| JPS61112349A (en) | Semiconductor integrated circuit device | |
| JPH07106757A (en) | Thin-film multilayered circuit board and its manufacture | |
| JPH01286444A (en) | Semiconductor device | |
| JPS615550A (en) | Semiconductor device and manufacture thereof | |
| JPH07153756A (en) | Semiconductor integrated circuit device | |
| JPH03293728A (en) | Semiconductor device | |
| JPH04320049A (en) | Multilayered wiring structure, and manufacture thereof | |
| JPS63268295A (en) | Multilayer interconnection substrate | |
| JPH01312854A (en) | Multilayer interconnection structure of semiconductor integrated circuit | |
| JPH05267295A (en) | Semiconductor device | |
| JPH0536841A (en) | Semiconductor device and manufacture thereof | |
| JPH05234998A (en) | Semiconductor device | |
| JPH0481878B2 (en) | ||
| JPH04261023A (en) | Semiconductor device | |
| JPS62271453A (en) | Manufacture of semiconductor element | |
| JPH06120369A (en) | Mutilayer wiring board | |
| JPH04196563A (en) | Semiconductor device | |
| JPS62104052A (en) | Semiconductor device |