JPS6152820U - - Google Patents
Info
- Publication number
- JPS6152820U JPS6152820U JP13712984U JP13712984U JPS6152820U JP S6152820 U JPS6152820 U JP S6152820U JP 13712984 U JP13712984 U JP 13712984U JP 13712984 U JP13712984 U JP 13712984U JP S6152820 U JPS6152820 U JP S6152820U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- base
- emitter
- alc
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009499 grossing Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図ａは本考案の対象となる入力信号波形図、第２
図ｂは従来の出力波形図、第２図ｃは本考案の出
力波形図、第３図は従来の回路図である。
Ｑ１，Ｑ２，Ｑ３…トランジスタ、３…増幅器
、２０…整流平滑回路、Ｑ４…ＡＬＣ制御用トラ
ンジスタ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
Figure a is an input signal waveform diagram that is the subject of the present invention.
FIG. 2B is a conventional output waveform diagram, FIG. 2C is an output waveform diagram of the present invention, and FIG. 3 is a conventional circuit diagram. Q1 , Q2 , Q3 ...transistor, 3...amplifier, 20...rectifier smoothing circuit, Q4 ...ALC control transistor.
Claims (1)
地された第１のトランジスタと、エミツタが前記
第１のトランジスタのエミツタに接続され、コレ
クタがインピーダンス手段を介して直流電源に接
続された第２のトランジスタと、ベースが前記第
２のトランジスタおよびインピーダンス手段との
共通接続点に接続され、コレクタが前記直流電源
に供給され、エミツタが抵抗を介して前記第２の
トランジスタのベースに接続された第３のトラン
ジスタからなる入力直結形増幅器、前記増幅器の
出力を整流平滑する回路、ベースが前記回路の出
力端子に接続され、エミツタが接地され、コレク
タが前記第１のトランジスタのベースに接続され
たＡＬＣ制御用トランジスタを備え、前記第１の
トランジスタを実質的に接地バイアスで駆動する
ようにしてなるＡＬＣ回路において、前記増幅器
の入力にも前記ＡＬＣ制御用トランジスタに流し
込む制御電流を流すことによつて、ＡＬＣ制御用
トランジスタのオン抵抗によつて生じるオフセツ
トを減少させたことを特徴とするＡＬＣ回路。 a first transistor whose base is directly connected to an input signal source and whose collector is grounded; and a second transistor whose emitter is connected to the emitter of the first transistor and whose collector is connected to a DC power supply via impedance means. and a third transistor, the base of which is connected to the common connection point of the second transistor and the impedance means, the collector of which is supplied to the DC power supply, and the emitter of which is connected to the base of the second transistor via a resistor. A direct-coupled input amplifier consisting of a transistor, a circuit for rectifying and smoothing the output of the amplifier, a base connected to the output terminal of the circuit, an emitter grounded, and a collector connected to the base of the first transistor for ALC control. In an ALC circuit including a transistor and configured to drive the first transistor substantially with a ground bias, ALC control is performed by flowing a control current to the ALC control transistor also into the input of the amplifier. An ALC circuit characterized in that an offset caused by an on-resistance of a transistor is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13712984U JPH0241931Y2 (en) | 1984-09-10 | 1984-09-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13712984U JPH0241931Y2 (en) | 1984-09-10 | 1984-09-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6152820U true JPS6152820U (en) | 1986-04-09 |
| JPH0241931Y2 JPH0241931Y2 (en) | 1990-11-08 |
Family
ID=30695546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13712984U Expired JPH0241931Y2 (en) | 1984-09-10 | 1984-09-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0241931Y2 (en) |
-
1984
- 1984-09-10 JP JP13712984U patent/JPH0241931Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0241931Y2 (en) | 1990-11-08 |