JPS6142171A - Manufacture of nonvolatile semiconductor memory device - Google Patents
Manufacture of nonvolatile semiconductor memory deviceInfo
- Publication number
- JPS6142171A JPS6142171A JP16367984A JP16367984A JPS6142171A JP S6142171 A JPS6142171 A JP S6142171A JP 16367984 A JP16367984 A JP 16367984A JP 16367984 A JP16367984 A JP 16367984A JP S6142171 A JPS6142171 A JP S6142171A
- Authority
- JP
- Japan
- Prior art keywords
- peripheral circuit
- oxide film
- gate
- famos
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 230000002093 peripheral effect Effects 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- XUFQPHANEAPEMJ-UHFFFAOYSA-N famotidine Chemical compound NC(N)=NC1=NC(CSCCC(N)=NS(N)(=O)=O)=CS1 XUFQPHANEAPEMJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 108091006146 Channels Proteins 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明はメモリトランジスタとしての二層ポリシリコン
ゲート構造のＦ Ａ Ｍ ＯＳ （Ｆｌｏａシｉｎｇｇ
ａｔｅ Ａｖａｌａｎｃｈｅ １ｎｊｅｃヒｉｏｎ
Ｍｅｔａｌ ０ｘｉｄｅ Ｓｅｍ１−ｃｏｎｄ
ｕｃｔｅｒ）と０ＭＯ８構成の単一ポリシリコンゲート
構造の周辺回路トランジスタとを同一基板上に形成して
なる半導体メモリ装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an F A MOS (Floa Si...
ate Avalanche 1njechiion
Metal Oxide Sem1-cond
The present invention relates to a method for manufacturing a semiconductor memory device in which a peripheral circuit transistor having a single polysilicon gate structure having an 0MO8 configuration and a peripheral circuit transistor formed on the same substrate.
（従来技術）
第２図はメモリトランジスタとしてのＦＡＭＯＳと周辺
回路のＮＭＯ８Ｉ−ランジスタとを同一基板上に形成し
てなる半導体メモリ装置であるが、この半導体メモリ装
置の製造方法として次の方法が提案されている。(Prior art) Figure 2 shows a semiconductor memory device in which a FAMOS as a memory transistor and an NMO8I-transistor as a peripheral circuit are formed on the same substrate.The following method is proposed as a manufacturing method for this semiconductor memory device. has been done.
シリコン基板２上に、フィールド酸化膜４、ゲート酸化
膜６を形成し、メモリトランジスタ領域ａのみにイオン
゛注入を施した後、全体に第１のポリシリコン層８、層
間酸化膜１０及び第２のポリシリコン層１２を順次形成
する。After forming a field oxide film 4 and a gate oxide film 6 on a silicon substrate 2 and performing ion implantation only in the memory transistor region a, a first polysilicon layer 8, an interlayer oxide film 10 and a second polysilicon layer are formed on the entire silicon substrate 2. Polysilicon layers 12 are sequentially formed.
次に、ホトリソグラフィ技法によりメモリトランジスタ
領域ａにＦＡＭＯＳゲートを形成する。Next, a FAMOS gate is formed in the memory transistor area a by photolithography.
このとき、周辺回路トランジスタ領域すではシリコン基
板２が露出する。At this time, the silicon substrate 2 is exposed in the peripheral circuit transistor region.
次に、ゲート酸化膜１４及び第３のポリシリコン層１６
を順次形成した後、ホトリソグラフィ技法により周辺回
路トランジスタのゲート電極を形成する。Next, a gate oxide film 14 and a third polysilicon layer 16 are formed.
After sequentially forming the gate electrodes of peripheral circuit transistors, photolithography techniques are used to form gate electrodes of peripheral circuit transistors.
その後、砒素（Ａｓ）拡散によるソース・ドレイン拡散
層１８．２０の形成、中間絶縁膜２２の形成、コンタク
トホールの形成、配線２４の形成などを行なう。Thereafter, formation of source/drain diffusion layers 18 and 20 by arsenic (As) diffusion, formation of an intermediate insulating film 22, formation of contact holes, formation of wiring 24, etc. are performed.
ところで、上記の方法によれば、ＦＡＭＯＳの層間酸化
膜１０と周辺回路トランジスタのゲート酸化膜１４とを
独立に最適膜厚に形成できる利煮を有する反面、ＦＡＭ
ＯＳのゲート形成時に周辺回路トランジスタ領域すのシ
リコン基板が露出してしまう欠点を有する。つまり、ポ
リシリコン層８、工２には通常、不純物が含有されてい
るので、シリコン基板が露出するとポリシリコン層８゜
１２の不純物が気相状態を経て周辺回路トラＮジメタ領
域すの基板に拡散（オートドーピング）し、そこに形成
されるトランジスタのしきい値電圧に影響を及ぼすから
である。By the way, according to the above method, although the interlayer oxide film 10 of the FAMOS and the gate oxide film 14 of the peripheral circuit transistor can be independently formed to the optimal film thickness,
This method has the disadvantage that the silicon substrate of the peripheral circuit transistor region is exposed when forming the gate of the OS. In other words, since the polysilicon layer 8 and step 2 usually contain impurities, when the silicon substrate is exposed, the impurities in the polysilicon layer 8 and 12 pass through the gas phase and enter the substrate of the peripheral circuit transistor region. This is because it diffuses (autodoping) and affects the threshold voltage of the transistor formed there.
また、ＦＡＭＯＳのフローティングゲート電極８、コン
トロールゲート電極１２及び周辺回路トランジスタのゲ
ート電極１６はそれぞれ異なる工程のポリシリコン層に
より形成されるため、３回のポリシリコン層形成工程が
必要となり工程数が多くなる問題もある。Furthermore, since the floating gate electrode 8, control gate electrode 12, and gate electrode 16 of the peripheral circuit transistor of the FAMOS are formed using polysilicon layers in different processes, three polysilicon layer formation processes are required, resulting in a large number of processes. There is also a problem.
（目的）
本発明は、二層ポリシリコンゲート構造のＦＡＭＯＳメ
モリトランジスタとＣＭＯ３構成の単一ポリシリコンゲ
ート構造の周辺回路トランジスタとを同一基板上に形成
してなる不揮発性半導体メモリ装置を、ＦＡＭＯＳの層
間酸化膜の膜厚と周辺回路トランジスタのゲート酸化膜
の膜厚をそれぞれに適するように調整しつつ、オートド
ーピングの問題がなく、しかもポリシリコン層の形成工
程を２回に抑えて製造することのできる方法を提供する
ことを目的とするものである。(Objective) The present invention provides a nonvolatile semiconductor memory device in which a FAMOS memory transistor with a two-layer polysilicon gate structure and a peripheral circuit transistor with a single polysilicon gate structure with a CMO3 configuration are formed on the same substrate. The thickness of the interlayer oxide film and the gate oxide film of the peripheral circuit transistor are adjusted to suit each other, and the process of forming the polysilicon layer is reduced to two without the problem of autodoping. The purpose is to provide a method that allows for
（構成）
本発明の製造方法では、ＦＡＭＯＳのフローティングゲ
ート電極となる第１のポリシリコン層をメモリトランジ
スタ領域に残した後、ＦＡＭＯＳの層間酸化膜と周辺回
路トランジスタのゲート酸化膜を形成するために、既に
存在する周辺回路トランジスタ領域のゲート酸化膜を所
定の膜厚までエッチパックした後に酸化処理を施こす。(Structure) In the manufacturing method of the present invention, after leaving the first polysilicon layer that will become the floating gate electrode of the FAMOS in the memory transistor area, the interlayer oxide film of the FAMOS and the gate oxide film of the peripheral circuit transistor are formed. After the gate oxide film in the peripheral circuit transistor region that already exists is etch-packed to a predetermined thickness, oxidation treatment is performed.
また、ＦＡＭＯＳのコントロールゲート電極と周辺回路
トランジスタのゲート電極は同一の第２のポリシリコン
層により形成する。そして、ゲートを形成するパターン
化工程は、まず１周辺回路トランジスタ領域をレジスト
で被ってＦＡＭＯＳのゲートを形成し、その後にＦＡＭ
ＯＳメモリトランジスタ領域をレジストで被って周辺回
路トランジスタのゲート電極を形成するようにする。Further, the control gate electrode of the FAMOS and the gate electrode of the peripheral circuit transistor are formed of the same second polysilicon layer. In the patterning process for forming the gate, first, one peripheral circuit transistor region is covered with resist to form the FAMOS gate, and then the FAM
The OS memory transistor area is covered with a resist to form a gate electrode of a peripheral circuit transistor.
以下、実施例により本発明を具体的に説明する。Hereinafter, the present invention will be specifically explained with reference to Examples.
第１図は本発明の一実施例を表わす。FIG. 1 represents one embodiment of the invention.
同図（Ａ）に示されるように、通常の方法によりＰ型基
板３０にＰ型チャネルストッパ３２、Ｎ型ウェル３４、
フィールド酸化膜３６及びゲート酸化膜３８．３９を形
成する。より具体的には、Ｐ型基板３０としては引上げ
法（ＣＺ法）で形成された（１００）Ｐ型シリコン基板
を使用し、Ｐ型チャネルストッパ３２はエネルギ５０Ｋ
ｅＶ、ドーズ量１０”／ｃｍ”オーダのイオン注入によ
り形成し、Ｎ型ウェル３４はエネルギ１６０ＫｅＶ、ド
ーズ量１０１２／ａｍ”オーダのイオン注入により形成
した。フィールド酸化膜３６の形成時（ａ、ｓ ｇｒ
ｏｗｎ）の膜厚は１３０００人、ゲート酸化膜３８．３
９の膜厚は７００人とした°。As shown in FIG. 3A, a P-type channel stopper 32, an N-type well 34, and a P-type channel stopper 32, an N-type well 34,
A field oxide film 36 and gate oxide films 38 and 39 are formed. More specifically, as the P-type substrate 30, a (100) P-type silicon substrate formed by a pulling method (CZ method) is used, and the P-type channel stopper 32 is
eV and a dose on the order of 10"/cm", and the N-type well 34 was formed by ion implantation at an energy of 160 KeV and a dose on the order of 1012/am". When the field oxide film 36 was formed (a, s gr
own) film thickness is 13000, gate oxide film 38.3
The film thickness of 9 was 700 people.
その後、ホトリソグラフィ技法を用いてメモリトランジ
スタ領域ａに選択的に、しきい値電圧制御用のボロンの
チャネルドープ４０をイオン注入により行なった後、Ｆ
ＡＭｏＳのフローティングゲート電極となる第１のポリ
シリコン層４２を形成し、このポリシリコン層４２をホ
トリソグラフィ技法によりメモリトランジスタ領域ａに
残す。チャネルドープ４０のボロンの注入量は １０”
／ｃｍ”オーダとし、第１のポリシリコン層４２の膜
厚は形成時で１６００人とした。Thereafter, channel doping 40 of boron for threshold voltage control is selectively implanted into the memory transistor region a using photolithography, and then F
A first polysilicon layer 42 that will become a floating gate electrode of the AMoS is formed, and this polysilicon layer 42 is left in the memory transistor region a by photolithography. The amount of boron implanted in channel dope 40 is 10”
/cm'' order, and the film thickness of the first polysilicon layer 42 at the time of formation was 1600.
次に、周辺回路トランジスタのゲート酸化膜の膜厚調整
と第１のポリシリコン層４２からのオートドーピング防
止のため、周辺回路トランジスタ領域す、ｃのゲート酸
化膜３８を３００人程度になるまでエッチバックした後
、全面酸化を行なって、同図（Ｂ）に示されるように、
周辺回路トランジスタ領域す、ｃのゲート酸化膜４４と
ＦＡＭｏＳの層間酸化膜４６とを同時に形成する。ゲー
ト酸化膜４４の膜厚を７００人、層間酸化膜４６の膜厚
を９００人とした。Next, in order to adjust the film thickness of the gate oxide film of the peripheral circuit transistor and to prevent autodoping from the first polysilicon layer 42, the gate oxide film 38 in the peripheral circuit transistor regions A and C is etched to a thickness of about 300. After backing up, the entire surface is oxidized, and as shown in the same figure (B),
The gate oxide film 44 of the peripheral circuit transistor regions S and C and the interlayer oxide film 46 of the FAMoS are simultaneously formed. The thickness of the gate oxide film 44 was 700 mm, and the thickness of the interlayer oxide film 46 was 900 mm.
その後、周辺回路のＮＭＯＳトランジスタ領域す及びＰ
ＭＯＳトランジスタ領域Ｃのそれぞれのしきい値電圧制
御用チャネルドープ４８及び５゜をイオン注入によって
行なった後、ＦＡＭｏＳのコントロールゲート電極及び
周辺回路トランジスタのゲート電極となる第２のポリシ
リコン層５２を形成する。ここで、チャネルドープ４８
，５０のイオン注入量をそれぞれ１０”／ａｍ”オーダ
とし、第２のポリシリコン層５２の形成時の膜厚を３５
００人とした。After that, the NMOS transistor area of the peripheral circuit and P
After channel doping 48 and 5° for threshold voltage control in each of the MOS transistor regions C is performed by ion implantation, a second polysilicon layer 52 that will become the control gate electrode of the FAMoS and the gate electrode of the peripheral circuit transistor is formed. do. Here, channel dope 48
, 50 ion implantations were each on the order of 10"/am", and the film thickness at the time of formation of the second polysilicon layer 52 was 35"/am".
00 people.
次に、同図（Ｃ）に示されるように、ホトリソグラフィ
技法により周辺回路トランジスタ領域す及びＣをレジス
ト５４で被うとともに、メモリトランジスタ領域ａに形
成したレジストパターン５６をマスクとして第２のポリ
シリコン層５２をエツチングしてＦＡＭｏＳのコントロ
ールゲート電極を形成し、続いてそのコントロールゲー
ト電極をマスクとしてその下層の眉間酸化膜４６及び第
１のポリシリコン層４２をセルファライン的にエツチン
グしてＦＡＭＯＳメモリトランジスタのゲート５８を形
成する。Next, as shown in FIG. 5C, the peripheral circuit transistor areas A and C are covered with a resist 54 by photolithography, and a second polyester is applied using the resist pattern 56 formed in the memory transistor area a as a mask. The silicon layer 52 is etched to form a FAMoS control gate electrode, and then, using the control gate electrode as a mask, the lower eyebrow oxide film 46 and first polysilicon layer 42 are etched in a self-line manner to form a FAMOS memory. A gate 58 of the transistor is formed.
レジスト５４．５６を除去した後、今度は同図（Ｄ）に
示されるように、メモリトランジスタ領域ａをレジスト
６０を被うとともに、周辺回路トランジスタ領域す及び
Ｃにレジストパターン６２゜６４を形成し、第２のポリ
シリコン層５２をエツチングして周辺回路トランジスタ
のゲート電極６６及び６８を形成する。そして、ＰＭＯ
Ｓ ）−ランジスタ領域Ｃに開口を有するレジストパタ
ーン７０を形成してボロンのイオン注入を行いソース・
ドレイン領域７２を形成するが、このときＰＭＯＳトラ
ンジスタのゲート電極６８上のレジスト６４は残したま
まボロンのイオン注入を行なう。After removing the resists 54 and 56, as shown in FIG. 5D, the memory transistor area a is covered with a resist 60, and resist patterns 62 and 64 are formed in the peripheral circuit transistor areas and C. , etching the second polysilicon layer 52 to form gate electrodes 66 and 68 for peripheral circuit transistors. And P.M.O.
S) - A resist pattern 70 having an opening is formed in the transistor region C, and boron ions are implanted into the source region.
A drain region 72 is formed, and at this time, boron ions are implanted while leaving the resist 64 on the gate electrode 68 of the PMOS transistor.
このボロンのイオン注入はエネルギ３０ＫｅＶ、ドーズ
量１ （１１Ｍ ／ ０ｍｌオーダとした。This boron ion implantation was performed at an energy of 30 KeV and a dose of 1 (on the order of 11 M/0 ml).
その後、通常の方法により、同図（Ｅ）に示されるよう
に、ＮＭＯＳトランジスタ領域すのソース・ドレイン領
域７４をイオン注入法で形成し、層間ＰＳＧ （リンシ
リコンガラス）膜７６、メタル配［７８，パッシベーシ
ョン８０を形成する。Thereafter, as shown in FIG. 6(E), source/drain regions 74 of the NMOS transistor region are formed by ion implantation using a conventional method, and an interlayer PSG (phosphor silicon glass) film 76 and a metal wiring [78] are formed by ion implantation. , passivation 80 is formed.
（効果）
本発明によれば周辺回路トランジスタのゲート酸化膜を
全て除去する工程はなく、ゲート酸化膜を所定膜厚まで
エッチバックした後に酸化処理を施こすことによりその
膜厚調整を行なうので、オートドーピングの問題は発生
しない。(Effects) According to the present invention, there is no step of completely removing the gate oxide film of the peripheral circuit transistor, and the film thickness is adjusted by performing oxidation treatment after etching back the gate oxide film to a predetermined film thickness. No autodoping problems occur.
また、ＣＭＯＳ構成の周辺回路トランジスタのうち、特
にＰＭＯＳトランジスタのソース・ドレイン領域の形成
の際、ゲート電極上にレジスト層を残したままでイオン
注入を行なうことができる。Further, when forming the source/drain regions of a PMOS transistor among peripheral circuit transistors having a CMOS structure, ion implantation can be performed while leaving a resist layer on the gate electrode.
もし、レジスト層のない状態でボロンをイオン注入して
ソース・トレイン領域を形成しようとすれば、ボロンが
注入時又はその後の水素雰囲気での熱処理でゲート電極
を透過してチャネル領域に侵入し、ＰＭＯＳトランジス
タのしきい値電圧が大きく変動してしまうことになる。If an attempt is made to form a source/train region by implanting boron ions in the absence of a resist layer, boron will penetrate through the gate electrode and enter the channel region during implantation or during subsequent heat treatment in a hydrogen atmosphere. The threshold voltage of the PMOS transistor will vary greatly.
本発明方法ではこのようなしきい値変動を最小限に抑え
ることができる。The method of the present invention can minimize such threshold fluctuations.
さらに、ポリシリコン層の形成工程は２回で済み、工程
数が少なくなる効果もある。Furthermore, the process of forming the polysilicon layer only needs to be carried out twice, which has the effect of reducing the number of steps.
第１図（Ａ）ないし同図（Ｅ）は本発明の一実施例を示
す断面図、第２図は従来の方法を説明するためのＮＭＯ
８型ＦＡＭＯＳメモリ装置を示す断面図である。
３８．３９．４４・・・・・・ゲート酸化膜、 ４２・
・・・・・第１のポリシリコン層、 ４６・・・・・・
層間酸化膜、５２・・・・・・第２のポリシリコン層、
５４，５６゜６０．６２，６４．７０・・・・・・レ
ジストパターン、５８・・・・・・ＦＡＭＯＳのゲート
、 ６６．６８・・・・・・周辺回路トランジスタのゲ
ート電極、 ａ・・・・・・メモリトランジスタ領域
、ｂ、ｃ・・・・・・周辺回路トランジスタ領域。1(A) to 1(E) are cross-sectional views showing one embodiment of the present invention, and FIG. 2 is a cross-sectional view of an NMO
FIG. 2 is a cross-sectional view of an 8-inch FAMOS memory device. 38.39.44...Gate oxide film, 42.
...First polysilicon layer, 46...
Interlayer oxide film, 52... second polysilicon layer,
54,56゜60.62,64.70...Resist pattern, 58...Gate of FAMOS, 66.68...Gate electrode of peripheral circuit transistor, a... ...Memory transistor area, b, c... Peripheral circuit transistor area.
Claims (1)
トランジスタと、ＣＭＯＳ構成の単一ポリシリコンゲー
ト構造の周辺回路トランジスタとを同一基板上に形成し
てなる不揮発性半導体メモリ装置の製造方法において、 ゲート酸化膜形成後、メモリトランジスタ領域にＦＡＭ
ＯＳのフローティングゲート電極となる第１のポリシリ
コン層を形成する工程、 周辺回路トランジスタのゲート酸化膜を所定膜厚にエッ
チングした後、ＦＡＭＯＳの層間酸化膜と周辺回路トラ
ンジスタのゲート酸化膜とを同時に形成する工程、 ＦＡＭＯＳのコントロールゲート電極及び周辺回路トラ
ンジスタのゲート電極となる第２のポリシリコン層を形
成する工程、 まず、周辺回路トランジスタ領域をレジストで被ってメ
モリトランジスタ領域をパターン化してＦＡＭＯＳのゲ
ートを形成する工程、及び その後にメモリトランジスタ領域をレジストで被って周
辺回路トランジスタ領域をパターン化してゲート電極を
形成する工程、を含むことを特徴とする不揮発性半導体
メモリ装置の製造方法。(1) In a method for manufacturing a nonvolatile semiconductor memory device in which a FAMOS memory transistor with a two-layer polysilicon gate structure and a peripheral circuit transistor with a single polysilicon gate structure in a CMOS configuration are formed on the same substrate, gate oxidation is performed. After film formation, FAM is placed in the memory transistor area.
Step of forming the first polysilicon layer that will become the floating gate electrode of the OS: After etching the gate oxide film of the peripheral circuit transistor to a predetermined thickness, the interlayer oxide film of the FAMOS and the gate oxide film of the peripheral circuit transistor are etched at the same time. Step of forming a second polysilicon layer that will become the control gate electrode of the FAMOS and the gate electrode of the peripheral circuit transistor: First, the peripheral circuit transistor region is covered with a resist, the memory transistor region is patterned, and the gate of the FAMOS is formed. 1. A method for manufacturing a nonvolatile semiconductor memory device, comprising the steps of: forming a gate electrode; and thereafter covering a memory transistor region with a resist and patterning a peripheral circuit transistor region to form a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16367984A JPS6142171A (en) | 1984-08-02 | 1984-08-02 | Manufacture of nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16367984A JPS6142171A (en) | 1984-08-02 | 1984-08-02 | Manufacture of nonvolatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6142171A true JPS6142171A (en) | 1986-02-28 |
Family
ID=15778535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16367984A Pending JPS6142171A (en) | 1984-08-02 | 1984-08-02 | Manufacture of nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142171A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0395084A2 (en) * | 1989-04-28 | 1990-10-31 | Kabushiki Kaisha Toshiba | Method of manufacturing a logic semiconductor device having non-volatile memory |
| US5188976A (en) * | 1990-07-13 | 1993-02-23 | Hitachi, Ltd. | Manufacturing method of non-volatile semiconductor memory device |
| US6329247B1 (en) | 1999-08-04 | 2001-12-11 | Nec Corporation | Nonvolatile semiconductor memory device and manufacturing method thereof |
-
1984
- 1984-08-02 JP JP16367984A patent/JPS6142171A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0395084A2 (en) * | 1989-04-28 | 1990-10-31 | Kabushiki Kaisha Toshiba | Method of manufacturing a logic semiconductor device having non-volatile memory |
| US5158902A (en) * | 1989-04-28 | 1992-10-27 | Kabushiki Kaisha Toshiba | Method of manufacturing logic semiconductor device having non-volatile memory |
| US5188976A (en) * | 1990-07-13 | 1993-02-23 | Hitachi, Ltd. | Manufacturing method of non-volatile semiconductor memory device |
| US6329247B1 (en) | 1999-08-04 | 2001-12-11 | Nec Corporation | Nonvolatile semiconductor memory device and manufacturing method thereof |
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