JPS6141976A - Delay time monitoring circuit - Google Patents
Delay time monitoring circuitInfo
- Publication number
- JPS6141976A JPS6141976A JP16444884A JP16444884A JPS6141976A JP S6141976 A JPS6141976 A JP S6141976A JP 16444884 A JP16444884 A JP 16444884A JP 16444884 A JP16444884 A JP 16444884A JP S6141976 A JPS6141976 A JP S6141976A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- counting
- output
- ring oscillator
- delay time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路の遅延時間をモヨタする回路
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that modulates the delay time of a semiconductor integrated circuit.
従来、半導体集積回路の遅延時間を測定する方法として
、入力パルスを印加してから出力パルスが得られるまで
の時間の絶対償金計測する方法がとられてき比。Conventionally, the method of measuring the delay time of a semiconductor integrated circuit has been to measure the absolute amount of time from the application of an input pulse until the output pulse is obtained.
しかしながら、このような測定績は、集積回路の高速化
、大規模化に伴ない、精度のよい測定値を得ることが非
常に困難になってき友。これは特に大規模化による測定
条件設定の困難さ、おＬび計測機器の測定誤差に起因す
る。However, as integrated circuits become faster and larger, it has become extremely difficult to obtain accurate measurements. This is particularly due to the difficulty of setting measurement conditions due to large scale, and measurement errors of L and measurement equipment.
従って本発明の目的は、特別な測定機器を用いることな
く、１１１度よく集積回路の遅延時間がモニタできる回
路を提供することにある。Therefore, an object of the present invention is to provide a circuit that can monitor the delay time of an integrated circuit with 111 degrees of accuracy without using special measuring equipment.
本発明によれば、半導体集積回路の遅延時間を測定する
ために、予め半導体集積回路内にリングオシレータ及び
その発振周波数を計数する計数回路を設け、計数回路の
計数償金モニタすることにより、集ａ回路の遅延時間を
測定する遅延時間モ二タ回路が得られる。According to the present invention, in order to measure the delay time of a semiconductor integrated circuit, a ring oscillator and a counting circuit for counting its oscillation frequency are provided in advance in the semiconductor integrated circuit, and the counting compensation of the counting circuit is monitored. A delay time monitor circuit for measuring the delay time of the circuit is obtained.
次に、本発明の実施例を示す図面を参照して本発明の詳
細な説明する。Next, the present invention will be described in detail with reference to drawings showing embodiments of the present invention.
本発明の第一〇実施例を示す第１図において。In FIG. 1 showing the 10th embodiment of the present invention.
集積回路上には、リングオシレータ４とソノ出力パルス
を計数する計数回路とが設けられている。A ring oscillator 4 and a counting circuit for counting sono output pulses are provided on the integrated circuit.
リングオンレータ４は２！１１段（偶数段）のシリアル
接続されｔインバータ回路１と、前記インバータ回路の
最終段の出力１０を一方の入力とし半導体集積回路の入
力端子２を他の入力１１とする崩、−ＮＤ回路３とを有
し、ＮＡＮＤ 回路３の出力１２がインバータ回路ｌ
の初段入力にフィードパ、りされている。計数回路５は
ＮＡＮＤ回路３の出力１２をクロ、りとし、このクロッ
クに応じて計数値をカウントアツプ又はカウントダウン
させる。この計数回路５はリセット入力１３によ）その
内容をクリアされ、計数結果上モニタ出力１４として出
力する。The ring-on inverter 4 has 2!11 stages (even stages) serially connected to the inverter circuit 1, the output 10 of the final stage of the inverter circuit as one input, and the input terminal 2 of the semiconductor integrated circuit as the other input 11. In addition, it has a -ND circuit 3, and the output 12 of the NAND circuit 3 is connected to the inverter circuit l.
The feed is sent to the first stage input. The counting circuit 5 clocks the output 12 of the NAND circuit 3, and counts up or down the count value according to this clock. This counting circuit 5 has its contents cleared by a reset input 13) and outputs the counting result as a monitor output 14.
計数回ｊ１３５のモニタ出力１４は、計数回路５のスリ
ップ・フロップの内容をそのままパラレルに出力し、半
導体集積回路の出力端子でモニタすることも可能である
。ま九計数回路５の各７リツプ・フロップをシフトレジ
スタ構成にして、シリアルシフト出力をモニタしてもよ
い。The monitor output 14 of the count j135 can output the contents of the slip-flop of the counting circuit 5 in parallel as they are, and can also be monitored at the output terminal of the semiconductor integrated circuit. Each of the seven flip-flops in the counting circuit 5 may be configured as a shift register, and the serial shift output may be monitored.
遅延時間のモニタは入力端子２にあらかじめ定められた
パルス幅の入力波形上入力し、その期間のリングオシレ
ータクロ、り出力１２ｔ−計数回路５で計数し、その計
数結果をモニタすることによって得られる。パルス幅の
長さ及びパルス幅の精度に応じたインバータの段数選択
を行りことにエフ、実用上さしつかえない範囲の誤差で
リングオシレータ４の発振周波数を計測できる。The delay time can be monitored by inputting an input waveform with a predetermined pulse width to the input terminal 2, counting the ring oscillator clock for that period using the output 12t-counting circuit 5, and monitoring the counting result. . By selecting the number of inverter stages according to the length of the pulse width and the accuracy of the pulse width, the oscillation frequency of the ring oscillator 4 can be measured with an error within a practically acceptable range.
第２図江第−の実施例の回路の各部の波形及び計数結果
の例を示す。第２図（ａ）は入力端子２に与えるパルス
波形であｆｉ、（ｂ）はリングオシレータの出力に、す
なわち計数回路５に与えられるクロックである。今、計
数回路５をあらかじめａｌｌｏにリセットし、カウント
ラップさせると、クロック入力（ｂ）により、計数回路
５の内容は００１０１（５）となる、この計数結果の下
位ビットは、計数誤差の可能性があるため周波数測定に
に用いず、上位ビ、トのみを比較チェ、りすることによ
フ、遅延時間のモニタができる。FIG. 2 shows examples of waveforms and counting results of various parts of the circuit of the second embodiment. FIG. 2(a) shows the pulse waveform fi applied to the input terminal 2, and FIG. 2(b) shows the clock applied to the output of the ring oscillator, that is, to the counting circuit 5. Now, if the counting circuit 5 is reset to allo in advance and the count is lapped, the contents of the counting circuit 5 will be 00101 (5) due to the clock input (b).The lower bits of this counting result may be due to a counting error. Therefore, delay time can be easily monitored by comparing and checking only the upper bits without using it for frequency measurement.
次に本発明の第二の実施例上水す第３図において、集積
回路上には第一の実施例と同様にリングオシレータ３４
お工び計数回路３５が設けられる。Next, in FIG. 3 of the second embodiment of the present invention, a ring oscillator 34 is provided on the integrated circuit as in the first embodiment.
A work counting circuit 35 is provided.
２ｎ＋１（４数段）のシリアル接続されたインバータ回
路３１ｔ−有し、インバータ回路３１の最後段出力は初
段入力にフィードバックされている。It has 2n+1 (several four stages) serially connected inverter circuits 31t-, and the output of the last stage of the inverter circuit 31 is fed back to the input of the first stage.
計ｉｏｏ路３５はリングオシレータ３４の出力をクロ、
りとし、クロ、りに応じてその内容ｔカウントアツプ又
はカウントダウンさせる。この計数回路３５は、その内
容をモニタするモニタ出力３４とをそなえた構成になっ
ている。The ioo path 35 clocks the output of the ring oscillator 34,
The content is counted up or down depending on the content. This counting circuit 35 is configured to include a monitor output 34 for monitoring its contents.
計数回路３５のそニタ出力３４は、計数回路３５の計数
結果を出力するので、半導体集積回路の出力端子で周波
数としてモニタすることが可能である。すなわち、遅延
時間の測定は、リングオシレーターの出力３２をクロッ
クとする計数回路３５で、クロックの周波敷金計数し、
その計数結果をモニタすることによって得られる。計数
回路３５のビット数及びリングオシレータ３４の段数選
択全行なうことにより、実用上さしつかえない範囲の誤
差でリングオシレータの発振周波数を計数回路３５の発
振周波数で計測できる。Since the monitor output 34 of the counting circuit 35 outputs the counting result of the counting circuit 35, it can be monitored as a frequency at the output terminal of the semiconductor integrated circuit. That is, to measure the delay time, a counting circuit 35 using the output 32 of the ring oscillator as a clock counts the frequency of the clock, and
It can be obtained by monitoring the counting results. By fully selecting the number of bits of the counting circuit 35 and the number of stages of the ring oscillator 34, the oscillation frequency of the ring oscillator can be measured by the oscillation frequency of the counting circuit 35 with an error within a practically acceptable range.
第４図は第二の実施例の回路の各部の波形及び計数結果
の例を示す。第４図Ｃａｌはリングオシレータ３４出力
２の出力、すなわち計数回路３５に与えられるクロック
であり１ｂ）ｄ計数回路３５の計数結果の上位ビットの
波形である。FIG. 4 shows examples of waveforms and counting results of various parts of the circuit of the second embodiment. Cal in FIG. 4 is the output of the ring oscillator 34 output 2, that is, the clock given to the counting circuit 35, and is the waveform of the upper bit of the counting result of the 1b)d counting circuit 35.
今、計数回路３５をｍｂｉｔの計数回路であるとすると
、計数結果の出力３４から１周波数として上が得られる
。従って高精度でない測定機でも遅ｎ
延時間を測定できる。Now, assuming that the counting circuit 35 is an mbit counting circuit, the above is obtained as one frequency from the output 34 of the counting result. Therefore, it is possible to measure the delay time even with a measuring device that is not highly accurate.
本発明に以上説明したように、半導体集積回路にリング
オシレータとこのリングオシレータの発振周波数全計数
する計数回路とを内蔵させ、計数回路の計数結果の有効
ビット全機能検査することにより１ｗ単に遅延時間のモ
ニタができるという効果がある。As described above, the present invention incorporates a ring oscillator and a counting circuit for counting all the oscillation frequencies of this ring oscillator in a semiconductor integrated circuit, and by testing all functions of the effective bits of the counting result of the counting circuit, the delay time is simply 1w. This has the effect of being able to monitor
第１図は本発明の第一の実施例を示すプロ、り図、第２
図は本発明の第一の実施例の動作を示すタイムチャート
、第３図は本発明の第二の実施例上水すプロ、り図、第
４図は本発明の第二の実施例の動作を示すタイムチャー
トである。
１．３１・・・・・・インバータ回路、３・・・・・・
ＮＡＮＤ回路、４．３４・・・・・・リングオシレータ
、５，３５・・・・・・計数回路。
第１図
（鎖ル）
第２図Figure 1 is a professional diagram showing the first embodiment of the present invention;
The figure is a time chart showing the operation of the first embodiment of the present invention, FIG. It is a time chart showing the operation. 1.31... Inverter circuit, 3...
NAND circuit, 4.34...Ring oscillator, 5,35...Counting circuit. Figure 1 (Chain) Figure 2
Claims (1)
バータ回路を有し、前記インバータ回路の最終段の出力
を前記インバータ回路の初段入力にフィードバックさせ
て構成したリングオシレータ回路と、前記リングオシレ
ータのクロック出力を計数する計数回路とを設け、前記
計数回路の内容をモニタすることによって前記集積回路
の遅延時間を測定することを特徴とする遅延時間モニタ
回路。A ring oscillator circuit having a plurality of serially connected inverter circuits on a semiconductor integrated circuit, and configured by feeding back the output of the final stage of the inverter circuit to the first stage input of the inverter circuit, and a clock of the ring oscillator. 1. A delay time monitor circuit comprising: a counting circuit for counting output, and measuring the delay time of the integrated circuit by monitoring the contents of the counting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16444884A JPS6141976A (en) | 1984-08-06 | 1984-08-06 | Delay time monitoring circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16444884A JPS6141976A (en) | 1984-08-06 | 1984-08-06 | Delay time monitoring circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6141976A true JPS6141976A (en) | 1986-02-28 |
Family
ID=15793358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16444884A Pending JPS6141976A (en) | 1984-08-06 | 1984-08-06 | Delay time monitoring circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6141976A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008203111A (en) * | 2007-02-21 | 2008-09-04 | Matsushita Electric Ind Co Ltd | Ultrasonic flowmeter |
| JP2008203112A (en) * | 2007-02-21 | 2008-09-04 | Matsushita Electric Ind Co Ltd | Ultrasonic flowmeter |
| JP2009194459A (en) * | 2008-02-12 | 2009-08-27 | Nec Corp | Monitoring circuit and resource control method |
| US7768303B2 (en) | 2007-12-27 | 2010-08-03 | Nec Corporation | Apparatus, circuit and method of monitoring performance |
-
1984
- 1984-08-06 JP JP16444884A patent/JPS6141976A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008203111A (en) * | 2007-02-21 | 2008-09-04 | Matsushita Electric Ind Co Ltd | Ultrasonic flowmeter |
| JP2008203112A (en) * | 2007-02-21 | 2008-09-04 | Matsushita Electric Ind Co Ltd | Ultrasonic flowmeter |
| US7768303B2 (en) | 2007-12-27 | 2010-08-03 | Nec Corporation | Apparatus, circuit and method of monitoring performance |
| JP2009194459A (en) * | 2008-02-12 | 2009-08-27 | Nec Corp | Monitoring circuit and resource control method |
| US8018240B2 (en) | 2008-02-12 | 2011-09-13 | Nec Corporation | Apparatus, circuit and method of monitoring leakage current characteristics |
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