JPH03102266A - Pulse width measurer - Google Patents
Pulse width measurerInfo
- Publication number
- JPH03102266A JPH03102266A JP23971689A JP23971689A JPH03102266A JP H03102266 A JPH03102266 A JP H03102266A JP 23971689 A JP23971689 A JP 23971689A JP 23971689 A JP23971689 A JP 23971689A JP H03102266 A JPH03102266 A JP H03102266A
- Authority
- JP
- Japan
- Prior art keywords
- pulse width
- pulse
- gate
- input
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、パルス幅測定器に関し、特に、測定パルスが
装置のクロックに相当し、それ以上の周波数のクロック
が無い場合に、論理回路のみでパルス幅を測定するパル
ス幅測定器に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pulse width measuring device, and in particular, when the measurement pulse corresponds to the clock of the device and there is no clock with a higher frequency, only the logic circuit can be used. This invention relates to a pulse width measuring device for measuring pulse width.
［従来の技術］
従来、入力パルスのパルス幅を測定するパルス幅測定器
は、例えば、測定パルスが装置のクロックに相当し、そ
れ以上の周波数のクロックがない場合において、アナロ
グ回路による積分器を使用し、該入力パルスのパルス幅
の測定を行っていた。[Prior Art] Conventionally, a pulse width measuring device that measures the pulse width of an input pulse uses an integrator using an analog circuit when the measurement pulse corresponds to the clock of the device and there is no clock with a higher frequency. was used to measure the pulse width of the input pulse.
［発明が解決しようとする課Ｈ］
然しながら、上述した従来のパルス幅測定器にあっては
、積分器を使用したアナログ回路となっており、そのた
め、集積化を行う際に、アナログ・ディジタルの混在を
行う必要があり、煩雑になっているという問題があった
．
そこで、本発明の課題は、ディジタル回路のみでパルス
幅を測定できるようにする点にある。[Problem H to be solved by the invention] However, the above-mentioned conventional pulse width measuring device is an analog circuit using an integrator, so when integrating it, analog and digital There was a problem in that it was necessary to perform mixing, making it complicated. Therefore, an object of the present invention is to enable measurement of pulse width using only a digital circuit.
［課題を解決するための手段コ
このような課題を解決するための本発明の技術的手段は
，入力パルスのパルス幅を測定するパルス幅測定器にお
いて、入力された入力パルスを一定量ずつ順次遅延させ
るｎ個の遅延手段と、該ｎ個の遅延手段の出力を大カパ
ルスの立下がり時の出力状態に保持する保持手段とを有
し、この保持された出力状態からパルス幅を測定するよ
うにしたものである。[Means for Solving the Problems] The technical means of the present invention for solving these problems is to sequentially measure input pulses by a fixed amount in a pulse width measuring device that measures the pulse width of input pulses. It has n delay means for delaying, and a holding means for holding the outputs of the n delay means at the output state at the falling edge of the large pulse, and the pulse width is measured from this held output state. This is what I did.
［実施例］
以下、添付図面に基づいて、本発明の実施例に係るパル
ス幅測定器について説明する。[Example] Hereinafter, a pulse width measuring device according to an example of the present invention will be described based on the accompanying drawings.
第１図に示すように、実施例に係るパルス幅測定器は、
入力された入力バルス１０を一定量ずつ順次遅延させる
ｎ個の遅延手段としてのゲート１００，１１０，１２０
・・・・１５０を備えている。これらのゲート１００，
１１０，１２０・・・・１５０は、直列に接続され、最
初のゲート１００を入力パルス１０の入力ゲートとして
構或し、各ゲー｝−１００，１１０，１２０・・・・１
５０の出力側には、夫々、該各ゲート１００，１１０，
１２０・・・・１５０からのゲート出力信号２０，３０
．４０・・・・８０を保持手段１６０へ入力信号ＤＯ〜
Ｄｎ−１として出力する回路が接続されている。保持手
段１６０は、上記ｎ個のゲート１００，１１０，１２０
・・・・１５０のゲート出力信号２．０，３０．４０・
・・・８０を上記入力パルス１０の立下がり時の出力状
態に保持する機能を備え、第２図に示すように、出力Ｑ
Ｏ〜Ｑ ｎ−１（゛１′′若しくは゛’ｏ”）として出
力する。即ち、保持手段１６０は、入力信号ＤＯ〜Ｄｎ
−１をクロックＣＰの立下がりで保持し、パルス幅に相
当する出力信号９０を出力し、出力ＱＯ〜Ｑｎ−１のＱ
Ｏ側からＱｎ−１側へ向って出力状態゛１”が何個連続
しているかを見ることによりパルス幅を測定しうるよう
になっている。As shown in FIG. 1, the pulse width measuring device according to the embodiment is as follows:
Gates 100, 110, 120 serve as n delay means that sequentially delay the input pulse 10 by a fixed amount.
...It is equipped with 150. 100 of these gates,
110, 120...150 are connected in series, the first gate 100 is configured as an input gate for the input pulse 10, and each gate }-100, 110, 120...1
50, the respective gates 100, 110,
Gate output signals 20, 30 from 120...150
．． 40...80 to the holding means 160 as input signal DO~
A circuit outputting as Dn-1 is connected. The holding means 160 holds the n gates 100, 110, 120.
...150 gate output signal 2.0, 30.40・
...80 in the output state at the falling edge of the input pulse 10, as shown in FIG.
O~Q n-1 ('1'' or ''o''). That is, the holding means 160 outputs the input signal DO~Dn
-1 at the falling edge of clock CP, outputs an output signal 90 corresponding to the pulse width, and outputs QO to Qn-1.
The pulse width can be measured by seeing how many output states "1" are continuous from the O side to the Qn-1 side.
従って、この実施例に係るパルス幅測定器によれば、入
力パルス１０は一定量の遅延を持つゲー｝−１００〜１
５０を通過することにより、第２図に示すように、各ゲ
ートからはパルス幅に従ったゲート出力信号２０〜８０
が出力され、保持手段１６０においてこのゲート出力信
号２０〜８０を入力パルス１０の立下がりで保持し、保
持手段１６０からはパルス幅に相当する出力信号９０か
出力される。Therefore, according to the pulse width measuring device according to this embodiment, the input pulse 10 has a certain amount of delay.
As shown in FIG. 2, each gate outputs a gate output signal 20 to 80 according to the pulse width.
is output, and the holding means 160 holds these gate output signals 20 to 80 at the falling edge of the input pulse 10, and the holding means 160 outputs an output signal 90 corresponding to the pulse width.
即ち、今、ゲートｌＯＯ〜１３０を例に挙げて説明する
と、第２図に示すように、各ゲート出力、つまり、ゲー
ト１００のゲート出力２０〜ゲート１３０のゲート出力
５０には各ゲートの遅延量に従った入力パルスと同形の
波形が出力される．これらの出力を入力パルス１０の立
下がりで保持することにより、保持手段１６０の出力Ｑ
Ｏ〜Ｑ３の如く、パルス幅に従った信号が保持手段１６
０に保持される．なお、第２図中保持手段１６０の出力
ＱＯ〜Ｑ３の１回目の保持クロック以前の波形は不定で
あるため割愛してある．また、パルス幅は保持手段１６
０の出力ＱＯ〜Ｑｎ−１のＱＯ側からＱｎ−１側へ向っ
て何個“１′゛が連続しているかを見ることにより知る
ことが出来る。That is, to explain the gates lOO~130 as an example, as shown in FIG. A waveform with the same shape as the input pulse according to is output. By holding these outputs at the falling edge of the input pulse 10, the output Q of the holding means 160
A signal according to the pulse width, such as O to Q3, is stored in the holding means 16.
It is held at 0. Note that the waveforms of the outputs QO to Q3 of the holding means 160 in FIG. 2 before the first holding clock are omitted because they are unstable. Moreover, the pulse width is determined by the holding means 16.
This can be determined by looking at how many "1's" are consecutive from the QO side of the 0 outputs QO to Qn-1 toward the Qn-1 side.
［発明の効果］
以上説明したように、本発明のパルス幅測定器によれば
、入力バルスを一定量の遅延を持つゲートを通過させる
ことでパルス幅としての信号に変換ずることにより、そ
の測定パルス以上の周波数のクロックが無い場合におい
ても、デイジタル回路のみでパルス幅を測定できるとい
う効果がある。[Effects of the Invention] As explained above, according to the pulse width measuring device of the present invention, an input pulse is passed through a gate having a certain amount of delay to convert it into a signal as a pulse width, thereby measuring the pulse width. Even if there is no clock with a frequency higher than the pulse, the pulse width can be measured using only a digital circuit.
第１図は本発明の実施例に係るパルス幅測定器の構成を
示すブロック図、第２図はゲート及び保持手段からの出
力状態を示す波形タイくングチャートである。
１０：入力バルス
２０〜８０：ゲート出力信号
９０：出力信号（入力パルスのパルスＴｉｌｌ）１００
〜１５０：ゲート
１６０：保持手段
ＤＯ〜Ｄｎ−１
二入力信号
ＱＯ〜Ｑｎ
１
：出力FIG. 1 is a block diagram showing the configuration of a pulse width measuring device according to an embodiment of the present invention, and FIG. 2 is a waveform tying chart showing output states from the gate and holding means. 10: Input pulse 20-80: Gate output signal 90: Output signal (input pulse pulse Till) 100
~150: Gate 160: Holding means DO~Dn-1 Two input signals QO~Qn 1: Output
Claims (1)
て、入力された入力パルスを一定量ずつ順次遅延させる
ｎ個の遅延手段と、該ｎ個の遅延手段の出力を入力パル
スの立下がり時の出力状態に保持する保持手段とを有し
、この保持された出力状態からパルス幅を測定するよう
にしたことを特徴とするパルス幅測定器。A pulse width measuring device that measures the pulse width of an input pulse includes n delay means that sequentially delay the input pulse by a fixed amount, and outputs of the n delay means at the falling edge of the input pulse. 1. A pulse width measuring instrument comprising: a holding means for holding the output state, and measuring the pulse width from the held output state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23971689A JPH03102266A (en) | 1989-09-14 | 1989-09-14 | Pulse width measurer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23971689A JPH03102266A (en) | 1989-09-14 | 1989-09-14 | Pulse width measurer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03102266A true JPH03102266A (en) | 1991-04-26 |
Family
ID=17048863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23971689A Pending JPH03102266A (en) | 1989-09-14 | 1989-09-14 | Pulse width measurer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03102266A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1043596A2 (en) * | 1999-03-30 | 2000-10-11 | Infineon Technologies North America Corp. | Pulse width detection |
| JP2010054504A (en) * | 2008-08-28 | 2010-03-11 | Advantest Corp | Pulse width measurement circuit |
| CN102981063A (en) * | 2012-11-13 | 2013-03-20 | 工业和信息化部电子第五研究所 | Single-particle transient state pulse width measurement method and measurement device and pulse generation device |
-
1989
- 1989-09-14 JP JP23971689A patent/JPH03102266A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1043596A2 (en) * | 1999-03-30 | 2000-10-11 | Infineon Technologies North America Corp. | Pulse width detection |
| EP1043596A3 (en) * | 1999-03-30 | 2003-07-09 | Infineon Technologies North America Corp. | Pulse width detection |
| KR100685081B1 (en) * | 1999-03-30 | 2007-02-22 | 인피니언 테크놀로지스 노쓰 아메리카 코포레이션 | Pulse width detection |
| JP2010054504A (en) * | 2008-08-28 | 2010-03-11 | Advantest Corp | Pulse width measurement circuit |
| CN102981063A (en) * | 2012-11-13 | 2013-03-20 | 工业和信息化部电子第五研究所 | Single-particle transient state pulse width measurement method and measurement device and pulse generation device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5796682A (en) | Method for measuring time and structure therefor | |
| JPS6331750B2 (en) | ||
| JPS5948660A (en) | Apparatus for measuring frequency and period | |
| JPH08211165A (en) | Pulse-duration measuring device | |
| US5686846A (en) | Time duration trigger | |
| JPH03102266A (en) | Pulse width measurer | |
| SU1157520A1 (en) | Recirculation time-interval counter | |
| JPH01143978A (en) | Delay time measuring circuit | |
| JP2602330Y2 (en) | Simultaneous measurement of pulse width and peak value | |
| JPS62131637A (en) | Timing jitter measuring system | |
| JPH02185111A (en) | Skew adjusting circuit | |
| JP2944307B2 (en) | A / D converter non-linearity inspection method | |
| RU1798705C (en) | Method of measurement of root-mean-square values of variable signals | |
| JPH0365663A (en) | Signal pulse width measuring circuit | |
| JP2543721Y2 (en) | Waveform measuring device | |
| JPH04244971A (en) | Pulse interval measuring circuit | |
| JPH03113611A (en) | Reference voltage generation circuit | |
| JPS62261072A (en) | Potential difference measuring apparatus | |
| JPS5947262B2 (en) | Phase difference measuring device | |
| JPS62250369A (en) | Apparatus for measuring potential difference | |
| JPS60242388A (en) | Measuring device for time margin | |
| JPH0365821A (en) | Glitch measuring device for d/a converter | |
| JPH08223006A (en) | Method and device for adjusting delay time | |
| JPH01212368A (en) | Pulse width measuring circuit | |
| JPH0678873U (en) | Duty ratio measurement circuit |