JPS6139713A - Automatic gain control circuit - Google Patents
Automatic gain control circuitInfo
- Publication number
- JPS6139713A JPS6139713A JP16048184A JP16048184A JPS6139713A JP S6139713 A JPS6139713 A JP S6139713A JP 16048184 A JP16048184 A JP 16048184A JP 16048184 A JP16048184 A JP 16048184A JP S6139713 A JPS6139713 A JP S6139713A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- gain control
- time constant
- amplitude
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 abstract description 14
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229920006395 saturated elastomer Polymers 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 238000007599 discharging Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 235000002595 Solanum tuberosum Nutrition 0.000 description 1
- 244000061456 Solanum tuberosum Species 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
- Recording Or Reproducing By Magnetic Means (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
(技術分野) ′
本発明は、磁気ディスク装置や磁気テープ装置等の記憶
装置における読出し回路に関し、よシ詳しくは、記憶装
置の情報記憶媒体から読み出した信号の振幅を安定化す
る自動利得制御回路に関する0
(従来技術)
第1図は磁気ディスク装置等の磁気記憶装置お一般的な
読出し回路のプロ、り図である。この読出し回路は、磁
気へ一ド゛1、前置増幅器2、自動利得制御回路(以降
AGOと呼ぶ)3、低域F波器4、微分器5と庇較器6
とから構成される。第2図は従来のAdOめ回路図、第
3図はとのAGOの各部信号の包絡線図である。この従
来のAGOは、電圧利得制御増幅器(以降VOAと呼ぶ
)7、整流器8、抵抗器9,11、コンデンサ10.基
準電源12、及びバ、ファアンブ13で構成される。抵
抗器9,11と→ンデンサ10とで構成される積分回路
は、voi7の出力差動信号bl+b!のピーク電圧値
にAGCが追従するようにピー・クホールド気味に設定
遣れている。そして、抵抗器9とコンデンサ10とで定
まる充電時定数は、抵抗器11とコンデンサ10とで定
まる放電時定数よシ充分小さくしである。[Detailed Description of the Invention] (Technical Field) The present invention relates to a readout circuit in a storage device such as a magnetic disk device or a magnetic tape device, and more specifically, the present invention relates to a readout circuit in a storage device such as a magnetic disk device or a magnetic tape device. 0 Regarding a Stabilizing Automatic Gain Control Circuit (Prior Art) FIG. 1 is a schematic diagram of a general readout circuit for a magnetic storage device such as a magnetic disk device. This readout circuit consists of a magnetic field converter 1, a preamplifier 2, an automatic gain control circuit (hereinafter referred to as AGO) 3, a low-frequency F wave generator 4, a differentiator 5, and a comparator 6.
It consists of FIG. 2 is a circuit diagram of a conventional AGO, and FIG. 3 is an envelope diagram of signals of various parts of the AGO. This conventional AGO includes a voltage gain control amplifier (hereinafter referred to as VOA) 7, a rectifier 8, resistors 9, 11, a capacitor 10. It is composed of a reference power supply 12, a power supply, and a fan 13. The integrating circuit composed of resistors 9, 11 and →capacitor 10 outputs a differential signal bl+b! of voi7. The AGC is set to have a slight peak hold so that it follows the peak voltage value. The charging time constant determined by the resistor 9 and the capacitor 10 is sufficiently smaller than the discharging time constant determined by the resistor 11 and the capacitor 10.
この従来のAGOにおいては、入力差動信号”I+a、
が存在しない状態から存在する状態への引込み特性を改
善し、VOA7の出力差動信号b1+b!の振幅が飽和
値から所定の大きさになるまでの時間、即ち引込み時間
を短くするためには、前記充電時定数を小さくする必要
があった。しかし、充電時定数を小さくすると、入力信
号aI、a、の包絡線に第3図に示すような突起部があ
る場合、その出力信号す、、b、においては、その突起
部の後縁から相当期間にわたって振幅が低下し、その回
復が放電時定数で決定する時間だけ遅れる。この出力信
号b1+Jにおける振幅の低下は、SNRを悪化させか
つ信号検出における誤シ率を高くする。In this conventional AGO, input differential signals “I+a,
improves the pull-in characteristic from the non-existent state to the existing state, and the output differential signal b1+b! of VOA7 is improved. In order to shorten the time it takes for the amplitude to reach a predetermined value from the saturation value, that is, the pull-in time, it is necessary to reduce the charging time constant. However, when the charging time constant is reduced, if the envelope of the input signal aI,a has a protrusion as shown in Figure 3, the output signals S, b, The amplitude decreases over a considerable period of time, and its recovery is delayed by a time determined by the discharge time constant. This decrease in the amplitude of the output signal b1+J deteriorates the SNR and increases the error rate in signal detection.
もっとも、この振幅低下を小さくすることは前記充電時
定数を太きくシ、第3図の突起状包結線にAGOが追従
しにくくすることによシ容易に実現できるが、充電時定
数を大きくすると引込み時間が遅くなってしまう。従来
のAGOには以上のような欠点があった。However, this amplitude drop can be easily reduced by making the charging time constant thicker and making it difficult for the AGO to follow the protruding envelope line shown in Fig. 3; however, if the charging time constant is increased, The retraction time will be delayed. Conventional AGOs had the above-mentioned drawbacks.
(発明の目的)
本発明の目的は、読出し信号の引込み時間が短く、シか
も入力信号(読出し信号)の包結線に急激な変化があっ
ても出力信号の振幅が安定な自動利得制御回路の提供に
ある。(Object of the Invention) An object of the present invention is to provide an automatic gain control circuit which has a short lead-in time for a read signal and can stabilize the amplitude of the output signal even if there is a sudden change in the envelope of the input signal (read signal). It's on offer.
(発明の構成)
本発明の構成は、情報記憶媒体から読み出した信号の振
幅を安定化する自動利得制御回路において、利得制御端
子に受ける利得制御信号に応じた利得で前記読出し信号
を増幅する利得制御増幅器と、この利得制御増幅器の出
力信号を整流する整流器と、この整流器の出力電流を充
電し充電した電荷を放電する積分回路と、この積分回路
の充電電圧に応じて前記利得制御信号を生ずる回路とか
らなシ、前記積分回路には充電時定数又は放電時定数の
うちの少なくとも一方を外部信号に応じて変える手段が
備えであることを特徴とする。(Structure of the Invention) The structure of the present invention is to provide an automatic gain control circuit that stabilizes the amplitude of a signal read from an information storage medium. a control amplifier, a rectifier that rectifies the output signal of the gain control amplifier, an integration circuit that charges the output current of the rectifier and discharges the charged charge, and generates the gain control signal according to the charging voltage of the integration circuit. The circuit is characterized in that the integration circuit is provided with means for changing at least one of a charging time constant and a discharging time constant in accordance with an external signal.
(実施例)
次に本発明の実施例を挙げ、その実施例の図面を参照し
て本発明の詳細な説明する0
第4図は本発明の一実施例の回路図である。この実施例
は、磁気記憶装置の読出し回路に用いら ゛れ、電
圧利得制御増幅器7と、整流器8と、抵抗器9,11と
、コンデンサ10.14と、基準電源12と、バッファ
アンプ13と、FET15と、レベル変換器16とを含
みんで構成される。VOA7の差動出力端子は各々整流
器8の差動入力端子に接続され、整流器8の出力端子は
抵抗器9を通してバッファアンプ13の正極性入力端子
に接続されている。バッファアンプ13の正極性入力端
子は、更に抵抗11を通して接地され、またコンデンサ
10を通しても接地され、またコンデンサ14を通して
FET15のドレイン端子と接続され、バッファアンプ
13の負極性入力端子は基準、電源12の正極性端子と
接続され基準電源12の負極性端子は接地され、バッフ
ァアンプ13の出力端子はVOA7の利得制御端子に接
続され、FET15のゲート端子はレベル変換器16の
出万端子に接続され、FET15のソース端子は接地さ
れている。(Embodiment) Next, an embodiment of the present invention will be described, and the present invention will be described in detail with reference to the drawings of the embodiment. FIG. 4 is a circuit diagram of an embodiment of the present invention. This embodiment is used in a readout circuit of a magnetic storage device, and includes a voltage gain control amplifier 7, a rectifier 8, resistors 9 and 11, a capacitor 10, 14, a reference power supply 12, and a buffer amplifier 13. , FET15, and level converter 16. Differential output terminals of the VOAs 7 are each connected to differential input terminals of a rectifier 8, and an output terminal of the rectifier 8 is connected to a positive input terminal of a buffer amplifier 13 through a resistor 9. The positive input terminal of the buffer amplifier 13 is further grounded through a resistor 11 and also through a capacitor 10, and is connected to the drain terminal of an FET 15 through a capacitor 14, and the negative input terminal of the buffer amplifier 13 is connected to a reference power source 12. The negative terminal of the reference power supply 12 is grounded, the output terminal of the buffer amplifier 13 is connected to the gain control terminal of the VOA 7, and the gate terminal of the FET 15 is connected to the output terminal of the level converter 16. , the source terminals of FET15 are grounded.
第5図乃至第7図は第4図実施例の各部信号の波形図で
ある。但し、第6図及び第7図において、信号CI +
C2+ dI r dtは包絡線で示しである。5 to 7 are waveform diagrams of signals of various parts in the embodiment of FIG. 4. However, in FIGS. 6 and 7, the signal CI +
C2+ dI r dt is indicated by the envelope.
次に、この実施例の動作を説明する。VOA7に入力さ
れる信号CI+ 02は磁気記憶装置の再生信号であシ
、差動信号である。VOA7の出力信号d、、d、も差
動信号であり、利得制御端子の電圧りに対応した利得で
入力信号C1,C2を増幅した信号である。整流器8は
VOA7の出力信号d、、d、を両波整流し第5図の波
形eを生成する。Next, the operation of this embodiment will be explained. The signal CI+02 input to the VOA 7 is a reproduction signal of the magnetic storage device and is a differential signal. The output signals d, , d of the VOA 7 are also differential signals, and are signals obtained by amplifying the input signals C1 and C2 with a gain corresponding to the voltage of the gain control terminal. The rectifier 8 double-wave rectifies the output signals d, , d of the VOA 7 to generate the waveform e shown in FIG.
この整流信号eは、FET15がオンしていれば、抵抗
9とコンデンサ10とコンデンサ14.!:FET15
のオン抵抗とで定まる時定数を充電時定数として、また
抵抗11とコンデンサ10とコンデンサ14とFET1
5のオン抵抗とで定まる時定数を放電時定数として積分
され平滑化される。平滑信号fの電圧が整流器8の出力
信号eのピーク電圧に追従するように、前記放電時定数
と充電時定数との比は大きく設定しである。バッファア
ンプ13は、平滑信号fと基準電源12との電位差に比
例した電圧りをVOA7の利得制御端子に印加する。レ
ベル変換器16は、TTLレベルの時定数切換信号iを
、FET15をオン、オフできるレベルの信号gに変換
する。時定数切換信号iは、磁気記憶装置の蒜出しへ、
ドの選択に同期してレベルが変わる信号である。読出し
へ、ドの選択時点が読出し動作の開始時t1であ夛、時
定数切換信号i及びgはt、からT=4.5μs遅れた
時点t、に高電位から低電位になる。If the FET 15 is on, this rectified signal e is transmitted to the resistor 9, the capacitor 10, the capacitor 14. ! :FET15
The charging time constant is determined by the on-resistance of resistor 11, capacitor 10, capacitor 14, and FET1.
The time constant determined by the on-resistance of 5 is integrated and smoothed as the discharge time constant. The ratio between the discharging time constant and the charging time constant is set large so that the voltage of the smoothed signal f follows the peak voltage of the output signal e of the rectifier 8. The buffer amplifier 13 applies a voltage proportional to the potential difference between the smoothed signal f and the reference power supply 12 to the gain control terminal of the VOA 7. The level converter 16 converts the time constant switching signal i at the TTL level into a signal g at a level that allows the FET 15 to be turned on and off. The time constant switching signal i is sent to the magnetic storage device,
This is a signal whose level changes in synchronization with the selection of the mode. For reading, the selection time point is the start time t1 of the read operation, and the time constant switching signals i and g change from high potential to low potential at time t, which is T=4.5 μs behind t.
本実施例によると、第′6図に示すように、読出し動作
の開始の際(時間T)の引込み動作においては、FET
15をオフし、充電時定数を抵抗9とコンデンサ10と
で決定する小さい値にし、読出し信号CI+’!のレベ
ルへの追従を早くする。According to this embodiment, as shown in FIG. 6, in the pull-in operation at the start of the read operation (time T), the FET
15 is turned off, the charging time constant is set to a small value determined by the resistor 9 and the capacitor 10, and the read signal CI+'! to follow the level faster.
その結果、VOA出力信号d、、 d、は、最初VOA
7の利得が非常に大きいため振幅がクリ、プ(飽和)し
ているが、小さい充電時定数に対応して早く所定の振幅
に引込まれる。読出し動作の開始よシ所定の時間T後に
FETI 5をオンすることによシ充放電時定数を大き
く設定する。As a result, the VOA output signals d,, d, are initially VOA
Since the gain of No. 7 is very large, the amplitude dips (saturates), but it quickly reaches a predetermined amplitude corresponding to the small charging time constant. By turning on the FETI 5 a predetermined time T after the start of the read operation, the charging/discharging time constant is set to a large value.
従って、通常の読出し時に記録媒体における磁性膜の不
均一等に起因する第7の如き突起状の包結線を持つ信号
C1+C2がVOA7に入力されても、充電時定数力j
大きいので平滑信号f、a2電圧、−化は小さく、VO
A7の利得制御信号りの変化は小さく抑えることができ
る。その結果、VOA7の出力信号d8.d、において
、包結線の突起部の後縁以後に見られる振幅の沈みこみ
を小さくすることができる。この第7図のdl、 d、
の波形を第3図のblyb!と比べることにより本実施
例と従来例との違いが明瞭に分る。なお、第3図及び第
7図の破線は突起部がないときの包結線を示す。Therefore, even if a signal C1+C2 having a protruding envelope line such as the seventh one due to non-uniformity of the magnetic film in the recording medium is input to the VOA7 during normal reading, the charging time constant force j
Since it is large, the smoothed signal f, a2 voltage, - is small, and VO
Changes in the gain control signal of A7 can be kept small. As a result, the output signal d8. of VOA7. In d, it is possible to reduce the dip in the amplitude seen after the trailing edge of the protrusion of the wrapping line. dl, d, in this figure 7.
The waveform of blyb! is shown in Figure 3. The difference between this embodiment and the conventional example can be clearly seen by comparing it with . In addition, the broken line in FIG. 3 and FIG. 7 shows the wrapping line when there is no protrusion.
本実施例では、以上説明したように、読出し動作の開始
時と通常の読出し時とで帰還回路に設けられる積分回路
の時定数を切換えるから、読出し信号の高速引込み動作
が可能で、かつ読出し信号に突起状の振幅変動が存在し
ても、出力信号の振幅が安定であるoしたがって、本実
施例を備えた読出し回路では、信号検出誤シが起シ難<
<、信号読出しにおける誤シ率が低い。In this embodiment, as explained above, since the time constant of the integrating circuit provided in the feedback circuit is switched between the start of the read operation and the normal read operation, the read signal can be pulled in at high speed, and the read signal The amplitude of the output signal is stable even if there is a protruding amplitude fluctuation in
<, the error rate in signal readout is low.
(発明の効果)
本発明によれば、以上に説明したように、読出し信号の
引込み時間が短く、シかも読出し信号の包結線に急激な
変化があっても出力信号の振幅が安定な自動利得制御回
路が提供できる。(Effects of the Invention) According to the present invention, as explained above, the readout signal pull-in time is short, and even if there is a sudden change in the envelope of the readout signal, an automatic gain is achieved in which the amplitude of the output signal is stable. Control circuit can be provided.
第1図は磁気記録装置の一般的な読出し回路を示すプロ
、り図、第2図は従来の自動利得制御口 □路の回路図
、第3図は第2図回路の各部信号の包 ・絡線図、
第4図は本発明の一実施例を示す回路図、第5図乃至第
7図は第4図実施例の各部信号の波形図である。
1・・・・・・磁気へ、ド、2・・・・・・前置増幅器
、3・・・・・・ □自動利得制御回路、4・・
・・・・低域r波器、訃・・・・・微分器、6・・・・
・・比較器、7・・・・・・電圧利得制御増幅器、8−
・・・・整流器、9,11・・・・・・抵抗器、10,
14・・・・−・コンデンサ、12・・・・・・基準電
源、13・・・・・・バ、ファアンプ、15・・・・・
・FIT、16・・・・・・レベル変換器。
芋 I 聞
oL17
!
/!32VCA
メ
カアシ 、2 ″ 弗し≧1第 3
図Figure 1 is a diagram showing a general readout circuit of a magnetic recording device, Figure 2 is a circuit diagram of a conventional automatic gain control port, and Figure 3 is an envelope of signals for each part of the circuit in Figure 2. line diagram,
FIG. 4 is a circuit diagram showing one embodiment of the present invention, and FIGS. 5 to 7 are waveform diagrams of various signals in the embodiment of FIG. 4. 1... To magnetic field, 2... Preamplifier, 3... □ Automatic gain control circuit, 4...
...Low-range r-wave generator, ...Differentiator, 6...
... Comparator, 7 ... Voltage gain control amplifier, 8-
... Rectifier, 9, 11 ... Resistor, 10,
14...Capacitor, 12...Reference power supply, 13...Ba, fan amplifier, 15...
・FIT, 16...Level converter. Potato I listening oL17! /! 32VCA mechanical foot, 2″ width ≧1 3rd
figure
Claims (1)
動利得制御回路において、利得制御端子に受ける利得制
御信号に応じた利得で前記読出し信号を増幅する利得制
御増幅器と、この利得制御増幅器の出力信号を整流する
整流器と、この整流器の出力電流を充電し充電した電荷
を放電する積分回路と、この積分回路の充電電圧に応じ
て前記利得制御信号を生ずる回路とからなり、前記積分
回路には充電時定数又は放電時定数のうちの少なくとも
一方を外部信号に応じて変える手段が備えてあることを
特徴とする自動利得制御回路。An automatic gain control circuit that stabilizes the amplitude of a signal read from an information storage medium includes a gain control amplifier that amplifies the read signal with a gain corresponding to a gain control signal received at a gain control terminal, and an output signal of the gain control amplifier. It consists of a rectifier that rectifies the current, an integrating circuit that charges the output current of the rectifier and discharges the charged charge, and a circuit that generates the gain control signal according to the charging voltage of the integrating circuit. An automatic gain control circuit comprising means for changing at least one of a time constant and a discharge time constant in accordance with an external signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16048184A JPS6139713A (en) | 1984-07-31 | 1984-07-31 | Automatic gain control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16048184A JPS6139713A (en) | 1984-07-31 | 1984-07-31 | Automatic gain control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6139713A true JPS6139713A (en) | 1986-02-25 |
Family
ID=15715880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16048184A Pending JPS6139713A (en) | 1984-07-31 | 1984-07-31 | Automatic gain control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6139713A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0520786A (en) * | 1991-07-09 | 1993-01-29 | Canon Inc | Information signal output device |
EP2280480A1 (en) * | 2002-07-01 | 2011-02-02 | Texas Instruments Deutschland Gmbh | Low power regulated ampliflier in a transponder |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55109012A (en) * | 1979-02-15 | 1980-08-21 | Toshiba Corp | Automatic gain control circuit |
JPS5862912A (en) * | 1981-10-09 | 1983-04-14 | Hitachi Ltd | Automatic gain control circuit for video signal |
-
1984
- 1984-07-31 JP JP16048184A patent/JPS6139713A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55109012A (en) * | 1979-02-15 | 1980-08-21 | Toshiba Corp | Automatic gain control circuit |
JPS5862912A (en) * | 1981-10-09 | 1983-04-14 | Hitachi Ltd | Automatic gain control circuit for video signal |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0520786A (en) * | 1991-07-09 | 1993-01-29 | Canon Inc | Information signal output device |
EP2280480A1 (en) * | 2002-07-01 | 2011-02-02 | Texas Instruments Deutschland Gmbh | Low power regulated ampliflier in a transponder |
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