JP3457787B2 - Automatic transmission output control device for TDMA transmitter - Google Patents
Automatic transmission output control device for TDMA transmitterInfo
- Publication number
- JP3457787B2 JP3457787B2 JP01449696A JP1449696A JP3457787B2 JP 3457787 B2 JP3457787 B2 JP 3457787B2 JP 01449696 A JP01449696 A JP 01449696A JP 1449696 A JP1449696 A JP 1449696A JP 3457787 B2 JP3457787 B2 JP 3457787B2
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- JP
- Japan
- Prior art keywords
- burst
- voltage
- transmission output
- output
- circuit
- Prior art date
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- Control Of Amplification And Gain Control (AREA)
- Time-Division Multiplex Systems (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＴＤＭＡ（Time Div
ision Multipul Access ：時分割多重アクセス）方式の
通信システムにおけるバースト的に起動する送信機の送
信出力レベル自動制御（ＡＰＣ：Automatic Power Cont
rol ）装置の調整機能に関するものであり、送信開始直
後やレベル変更直後のバースト（特定バースト）立ち上
がり時におけるＡＰＣの応答をスムーズに行え、且つ各
セット間での送信出力のバラツキを抑えるものである。TECHNICAL FIELD The present invention relates to a TDMA (Time Div.
ision Multipul Access: Transmission power level control (APC: Automatic Power Cont) of a transmitter activated in burst in a communication system of time division multiple access
rol) This is related to the adjustment function of the device, and is capable of smoothly responding to the APC when the burst (specific burst) rises immediately after the start of transmission or immediately after changing the level, and suppresses variations in the transmission output between each set. .
【０００２】[0002]
【従来技術】従来の無線通信方式（ＴＤＭＡ方式でない
連続送信）における送信出力レベル自動制御回路の構成
例を図５〜図６に示す。図５はフィードバック制御信号
でパワーアンプ（ＰＡ：Power Amplifier Module）１の
利得制御を行う構成例で、ＰＡ１から出力された送信出
力レベルをカップラ（方向性結合器）２により取り出
す。カップラ２からの出力は検波回路３、積分回路４に
より送信出力レベルに応じた電圧として差動増幅器５に
入力される。この電圧は、ＣＰＵから与えられる基準電
圧と比較され、その差（差動増幅器５の出力電圧
（ｃ））をＰＡ１の利得制御端子にフィードバックする
ことにより基準電圧に応じた出力レベルを保つようにな
っている。また図６は電圧可変型利得制御器（ＶＣＡ：
Voltage ControlAttenator 又はVoltage Control Ampli
fier ）６をＰＡ１に組み合わせて構成した例で、ＶＣ
Ａ６の制御端子に図１と同様に差動増幅器５の出力電圧
（ｃ）フィードバックして利得制御を行い基準電圧に応
じた出力レベルを保つようになっている。2. Description of the Related Art FIGS. 5 and 6 show examples of the structure of a transmission output level automatic control circuit in a conventional wireless communication system (continuous transmission that is not the TDMA system). FIG. 5 is a configuration example in which a gain control of a power amplifier (PA: Power Amplifier Module) 1 is performed by a feedback control signal, and a transmission output level output from PA 1 is taken out by a coupler (directional coupler) 2. The output from the coupler 2 is input to the differential amplifier 5 as a voltage corresponding to the transmission output level by the detection circuit 3 and the integration circuit 4. This voltage is compared with the reference voltage given from the CPU, and the difference (the output voltage (c) of the differential amplifier 5) is fed back to the gain control terminal of PA1 so that the output level according to the reference voltage is maintained. Has become. Further, FIG. 6 shows a voltage variable gain controller (VCA:
Voltage Control Attenator or Voltage Control Ampli
In the example which is configured by combining fier) 6 with PA1, VC
Similar to FIG. 1, the output voltage (c) of the differential amplifier 5 is fed back to the control terminal of A6 to perform gain control and maintain the output level according to the reference voltage.
【０００３】ＴＤＭＡ動作の場合、バースト信号ＯＦＦ
状態の時、ＰＡ１またはＶＣＡ６には最大出力になるよ
うに制御電圧が与えられる。この状態からバースト信号
ＯＮ状態になると積分回路の時定数やループの応答速度
などによる時間だけ送信出力レベルが各バースト立ち上
がり毎に安定せず、正確なＡＰＣ動作が行われない事に
なる（図７参照）。Burst signal OFF in TDMA operation
In the state, the control voltage is applied to PA1 or VCA6 so as to maximize the output. When the burst signal is turned on from this state, the transmission output level is not stabilized at each burst rise for a time depending on the time constant of the integrating circuit, the response speed of the loop, etc., and accurate APC operation cannot be performed (FIG. 7). reference).
【０００４】そのため、検波回路と積分回路の間にゲー
ト回路とサンプル＆ホールド回路を設け、バースト信号
ＯＮ状態の検波回路出力レベルをサンプルして積分回路
に出力し、バースト信号ＯＦＦ状態でサンプルしたレベ
ルをホールドして積分回路に出力して各バーストの立ち
上がりを安定させることができる。しかしながら、この
構成であっても、送信開始直後や送信レベル変更直後の
送信バーストなどの特定バースト信号においては送信出
力制御の効果が期待できない（図８参照）。その理由
は、連続した同一レベルのバースト状態ではサンプル＆
ホールド回路出力はほぼ一定値に安定するが、送信開始
直後やレベル変更直後など、送信出力レベルが変化する
時にはサンプル＆ホールド回路出力も変化してしまう。
その為、変化してから本来制御すべき値に安定するまで
ループ回路の応答時間が必要となり、その影響が図６、
図７のフィードバック信号（ｃ）に現れ、その結果、送
信開始直後やレベル変更直後の第１バーストの大部分、
あるいは回路の応答や積分回路の時定数によっては第２
バースト以降にも影響が出てしまう（図８参照）。Therefore, a gate circuit and a sample-and-hold circuit are provided between the detection circuit and the integration circuit to sample the output level of the detection circuit when the burst signal is ON and output it to the integration circuit to sample the level when the burst signal is OFF. Can be held and output to the integrating circuit to stabilize the rising of each burst. However, even with this configuration, the effect of the transmission output control cannot be expected for a specific burst signal such as a transmission burst immediately after the start of transmission or immediately after the transmission level is changed (see FIG. 8). The reason is that the sample &
The output of the hold circuit stabilizes at an almost constant value, but the output of the sample & hold circuit also changes when the transmission output level changes, such as immediately after the start of transmission or immediately after the level is changed.
Therefore, the response time of the loop circuit is required from the change until it stabilizes at the value that should be controlled originally.
It appears in the feedback signal (c) in FIG. 7, and as a result, most of the first burst immediately after the start of transmission or immediately after the level change,
Alternatively, depending on the response of the circuit and the time constant of the integrating circuit, the second
It will also be affected after the burst (see Fig. 8).
【０００５】[0005]
【課題を解決するための手段】本発明は、ＴＤＭＡ方式
で且つ振幅変動のおこる変調方式である通信システムで
あっても、バースト信号ＯＮ状態立ち上がり時のＡＰＣ
動作を安定に、且つ正確に制御するため送信出力自動制
御装置にゲート回路、積分回路、サンプル＆ホールド回
路を付加するとともに、送信開始直後や送信出力レベル
変更直後の第１バースト（特定バースト）のＡＰＣ動作
を可能な限り短時間で安定、且つ正確に制御し正常動作
に戻すため、これら特定バースト時のみ強制的にアナロ
グＳＷを用い積分回路の時定数をバーストには十分応答
できる程度に短く設定する（Ｒ・Ｃ１）。同時に、通常
時の変調波振幅変動の単位時間に比べて十分長い時定数
（Ｒ・（Ｃ１＋Ｃ２））のコンデンサＣ２に基準電圧相
当をチャージしておく。次に、特定バースト開始後送信
するデータに極力影響無い短時間でこのアナログＳＷを
通常の時定数（Ｒ・（Ｃ１＋Ｃ２））に戻す。バースト
には十分応答できる程度の短い時定数（Ｒ・Ｃ１）は変
調波の振幅変動に応答する為、特定バーストの立ち上が
りで若干のレベル変動が生じるが、その後アナログＳＷ
が大きい時定数（Ｒ・（Ｃ１＋Ｃ２））に切り替える。
アナログＳＷが切り替わる時、変調波振幅変動の単位時
間に比べて十分長い時定数（Ｒ・（Ｃ１＋Ｃ２））のコ
ンデンサＣ２が基準電圧にチャージされている為、大き
なレベル変動無く通常のＡＰＣ動作に移ることが可能と
なる。以上の動作をする為、本発明はＴＤＭＡ送信機の
送信出力自動制御装置において特定バースト時に積分回
路の時定数をバーストに応答できる短いＲ・Ｃ１に切り
替えるアナログＳＷと、このアナログＳＷ切り替え時に
特定バースト時以外の通常時に使用する長い時定数（Ｒ
・（Ｃ１＋Ｃ２））のコンデンサＣ２に基準電圧をチャ
ージする機能を付加した。According to the present invention, even in a communication system which is a TDMA system and a modulation system in which amplitude fluctuations occur, the APC at the rise of the burst signal ON state is provided.
In order to control the operation stably and accurately, a gate circuit, an integration circuit, and a sample & hold circuit are added to the automatic transmission output control device, and the first burst (specific burst) immediately after the start of transmission or immediately after the transmission output level is changed. In order to control the APC operation stably and accurately in the shortest possible time and to return to normal operation, the analog SW is forcibly used only during these specific bursts and the time constant of the integrating circuit is set short enough to respond to the burst. Yes (R / C1). At the same time, the capacitor C2 having a time constant (R · (C1 + C2)) sufficiently longer than the unit time of the modulation wave amplitude fluctuation in the normal time is charged with the reference voltage equivalent. Next, after the start of the specific burst, the analog SW is returned to the normal time constant (R · (C1 + C2)) in a short time without affecting the data to be transmitted. Since the time constant (R · C1) that is short enough to respond to the burst responds to the amplitude fluctuation of the modulation wave, some level fluctuation occurs at the rising edge of the specific burst.
Changes to a large time constant (R · (C1 + C2)).
When the analog SW is switched, the capacitor C2 having a time constant (R · (C1 + C2)) that is sufficiently longer than the unit time of the modulation wave amplitude fluctuation is charged to the reference voltage, so that the normal APC operation is performed without a large level fluctuation. It becomes possible. In order to perform the above operation, the present invention provides an analog SW for switching the time constant of the integrating circuit to a short R / C1 capable of responding to the burst in the transmission output automatic control device of the TDMA transmitter, and the specific burst when the analog SW is switched. Long time constant (R
The function of charging the reference voltage to the capacitor C2 ((C1 + C2)) was added.
【０００６】[0006]
【発明の実施の形態】図１、図２に本発明の実施例を示
し詳細に説明する。図１はフィードバック制御信号でパ
ワーアンプ（ＰＡ：Power Amplifier Module）１の利得
制御を行う構成例、図２は電圧可変型利得制御器（ＶＣ
Ａ：Voltage Control Attenator 又はVoltage Control
Amplifier ）６をＰＡ１に組み合わせて構成した例であ
る。なお、従来例図５、図６と同一ブロックには同一符
号を付し説明は省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a configuration example in which a gain control of a power amplifier (PA: Power Amplifier Module) 1 is performed by a feedback control signal, and FIG. 2 is a voltage variable gain controller (VC).
A: Voltage Control Attenator or Voltage Control
Amplifier) 6 is combined with PA1. The same blocks as those in the conventional example shown in FIGS. 5 and 6 are designated by the same reference numerals, and the description thereof will be omitted.
【０００７】まず、通常の連続した同一送信出力のバー
スト動作時、つまりＡＰＣ積分回路４の時定数が通常時
時定数（Ｒ・（Ｃ１＋Ｃ２））の状態（アナログＳＷ９
が端子Ａの位置）である時、ゲート回路７とサンプル＆
ホールド回路８は、バースト信号ＯＮ状態時にゲートを
開き、同時にサンプル動作を行う。また、バースト信号
ＯＦＦ状態時にゲートを閉じ、同時にホールド動作を行
う。図３に連続した同一送信出力のバースト動作時のタ
イミングチャートを示す。これはＴＤＭＡ送信機がＯＮ
状態になっている間の送信レベルの平均値に相当する電
圧値をサンプリングし、ＴＤＭＡ送信機がＯＦＦ状態に
なっている間この電圧値をホールドし、且つ差動増幅器
５により基準電圧との比較を行っている。そのため、バ
ースト信号のＯＮ状態時のみの送信出力レベルを、バー
スト信号ＯＦＦ状態時の送信出力レベルに影響されずに
送信出力レベルを制御できる方式を提供できる。First, during a normal continuous burst operation of the same transmission output, that is, when the time constant of the APC integrating circuit 4 is the normal time constant (R. (C1 + C2)) (analog SW9
Is the position of terminal A), the gate circuit 7 and the sample &
The hold circuit 8 opens the gate when the burst signal is ON, and simultaneously performs the sampling operation. Further, when the burst signal is OFF, the gate is closed and the hold operation is performed at the same time. FIG. 3 shows a timing chart at the time of continuous burst operation of the same transmission output. This is the TDMA transmitter is ON
The voltage value corresponding to the average value of the transmission level during the state is sampled, this voltage value is held while the TDMA transmitter is in the OFF state, and the differential amplifier 5 compares it with the reference voltage. It is carried out. Therefore, it is possible to provide a method in which the transmission output level only when the burst signal is in the ON state can be controlled without being affected by the transmission output level when the burst signal is in the OFF state.
【０００８】次に、送信開始（電源投入）直後や送信出
力レベル変更直後の第１バースト（特定バースト）時、
アナログＳＷ９は、図４に示すアナログＳＷ制御タイミ
ングで特定バーストの立ち上がり前後の区間のみ端子Ｂ
の位置に切り替わる。この状態はＡＰＣ積分回路４がバ
ーストには十分に応答できる程度の通常時より短い時定
数（Ｒ・Ｃ１）にセットされる。この時定数の短い間、
送信出力は若干のレベル変動を生じるが、端子Ｂは最終
的に制御されるべき基準電圧相当（端子Ｂ＝ｅ１＝ｅ
２）の出力レベルになる。一方、端子Ａは特定バースト
の立ち上がり時には基準電圧値に安定する。この時積分
回路４の時定数（Ｒ・Ｃ１）がバーストにも十分応答
し、且つ変調によるレベル変動をある程度除去できるよ
うな適切な値であれば、端子Ａと端子Ｂの電圧値はどち
らも基準電圧値ｅ２に等しくなる。従って、特定バース
トの立ち上がり直後にアナログＳＷ９が端子Ｂから端子
Ａに切り替わっても、ＰＡ１（図１の場合）もしくはＶ
ＣＡ６（図２の場合）への差動増幅器５出力であるフィ
ードバック制御信号（Ｃ）に大きな変動はなく、特定バ
ーストにおいても早く、安定に、且つ正確なＡＰＣ動作
を提供できる。さらに、アナログＳＷ９が端子Ｂ側に切
り替わった時、バッファアンプ１０を介し基準電圧でコ
ンデンサＣ２をチャージするようにして、チャージがル
ープ応答に悪影響を与えることを防止している。Next, at the first burst (specific burst) immediately after the start of transmission (power-on) or immediately after the change of the transmission output level,
The analog SW 9 has a terminal B only in the section before and after the rise of a specific burst at the analog SW control timing shown in FIG.
Switch to the position. This state is set to a time constant (R · C1) shorter than the normal time such that the APC integrating circuit 4 can sufficiently respond to the burst. While this time constant is short,
Although the transmission output slightly changes in level, the terminal B corresponds to the reference voltage to be finally controlled (terminal B = e1 = e).
It becomes the output level of 2). On the other hand, the terminal A stabilizes at the reference voltage value when the specific burst rises. If the time constant (R · C1) of the time integration circuit 4 is an appropriate value that can sufficiently respond to the burst and that level fluctuation due to modulation can be removed to some extent, both the voltage values at the terminals A and B are It becomes equal to the reference voltage value e2. Therefore, even if the analog SW 9 is switched from the terminal B to the terminal A immediately after the rising of the specific burst, PA1 (in the case of FIG. 1) or V
The feedback control signal (C), which is the output of the differential amplifier 5 to the CA 6 (in the case of FIG. 2), does not fluctuate significantly, and a fast, stable and accurate APC operation can be provided even in a specific burst. Further, when the analog SW9 is switched to the terminal B side, the capacitor C2 is charged with the reference voltage via the buffer amplifier 10 to prevent the charge from adversely affecting the loop response.
【０００９】[0009]
【効果】ＴＤＭＡ方式の通信システムの送信機におい
て、従来技術では送信開始直後や送信出力レベル変更直
後のバースト（特定バースト）時に不安定、且つ不正確
であったＡＰＣ動作を安定、且つ正確に行う事が可能と
なる。[Effect] In the transmitter of the TDMA communication system, the APC operation that is unstable and inaccurate in the prior art at the time of a burst (specific burst) immediately after the start of transmission or immediately after the change of the transmission output level is performed stably and accurately. Things are possible.
【図１】本発明に係り、ＴＤＭＡ方式における送信出力
レベル自動制御回路の構成例を示すブロック図。FIG. 1 is a block diagram showing a configuration example of a transmission output level automatic control circuit in a TDMA system according to the present invention.
【図２】本発明に係り、ＴＤＭＡ方式における送信出力
レベル自動制御回路の構成例を示す第２のブロック図。FIG. 2 is a second block diagram showing a configuration example of a transmission output level automatic control circuit in the TDMA system according to the present invention.
【図３】本発明の構成によるタイミングチャート。FIG. 3 is a timing chart according to the configuration of the invention.
【図４】本発明の構成による特定バースト時のタイミン
グチャートで、（ａ）は電源投入直後、（ｂ）は送信出
力レベル変更直後のタイミグチャート。FIG. 4 is a timing chart at the time of a specific burst according to the configuration of the present invention, where (a) is a timing chart immediately after power-on, and (b) is a timing chart immediately after changing the transmission output level.
【図５】従来例に係り、ＴＤＭＡ方式における送信出力
レベル自動制御回路の構成例を示すブロック図。FIG. 5 is a block diagram showing a configuration example of a transmission output level automatic control circuit in a TDMA system according to a conventional example.
【図６】従来例に係り、ＴＤＭＡ方式における送信出力
レベル自動制御回路の構成例を示す第２のブロック図。FIG. 6 is a second block diagram showing a configuration example of a transmission output level automatic control circuit in a TDMA system according to a conventional example.
【図７】従来の構成によるタイミングチャート。FIG. 7 is a timing chart of a conventional configuration.
【図８】従来の構成による特定バースト時のタイミング
チャートで、（ａ）は送信開始直後、（ｂ）は送信出力
レベル変更直後のタイミグチャート。FIG. 8 is a timing chart at the time of a specific burst according to the conventional configuration, where (a) is a timing chart immediately after the start of transmission and (b) is a timing chart immediately after the transmission output level is changed.
１：パワーアンプ（ＰＡ：Power Amplifier Module）
２：カップラ（方向性結合器）
３：検波回路
４：積分回路
５：差動増幅器
６：電圧可変型利得制御器（ＶＣＡ：Voltage Control
Attenator 又はVoltageControl Amplifier ）
７：ゲート回路
８：サンプル＆ホールド回路
９：アナログＳＷ（スイッチ）
１０：バッファアンプ1: Power amplifier (PA: Power Amplifier Module) 2: Coupler (directional coupler) 3: Detection circuit 4: Integration circuit 5: Differential amplifier 6: Voltage variable gain controller (VCA: Voltage Control)
Attenator or Voltage Control Amplifier) 7: Gate circuit 8: Sample & hold circuit 9: Analog SW (switch) 10: Buffer amplifier
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H04J 3/00 H03G 3/30 H04B 1/04 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H04J 3/00 H03G 3/30 H04B 1/04
Claims (2)
おいて、送信出力の一部を取り出すカップラと、取り出
した送信出力信号レベルをレベル相当の電圧に変換する
検波回路と、前記検波回路出力をバースト信号ＯＮ状態
時にサンプルしＯＦＦ状態時にホールドするサンプル＆
ホールド回路と、通常時は送信出力信号検波電圧の平均
値を検出するため変調波振幅変動の単位時間に比べて十
分に長い時定数（Ｒ・（Ｃ１＋Ｃ２））で使用し、送信
開始直後や送信出力レベル変更直後の特定バースト時は
ＡＰＣループの応答を通常より早くするためバーストに
十分応答できる程度に短い時定数（Ｒ・Ｃ１）に切り替
えて使用するように構成した積分回路と、基準電圧と前
記積分回路出力電圧の差分を取り出す差動増幅器と、前
記特定バーストの立ち上がり前後区間のみ前記積分回路
の時定数を通常時のＲ・（Ｃ１＋Ｃ２）からＲ・Ｃ１に
切り替えるとともにこの時コンデンサＣ２に前記基準電
圧を印加して該基準電圧相当にチャージさせるアナログ
ＳＷと、前記差動増幅器出力電圧により利得を制御され
るパワーアンプもしくは該差動増幅器出力電圧により利
得を制御される電圧可変型利得制御器を有するパワーア
ンプとにより構成されることを特徴とするＴＤＭＡ送信
機の送信出力自動制御装置。1. In a transmitter in a TDMA communication system, a coupler for extracting a part of transmission output, a detection circuit for converting the extracted transmission output signal level into a voltage equivalent to the level, and a burst of the detection circuit output. Sample & sample when signal is on and hold when signal is off
It is used with a hold circuit and a time constant (R · (C1 + C2)) that is sufficiently longer than the unit time of the modulation wave amplitude fluctuation to detect the average value of the transmission output signal detection voltage during normal operation. In order to make the response of the APC loop faster than usual during a specific burst immediately after the output level is changed, an integrating circuit configured to be used by switching to a time constant (R · C1) that is short enough to sufficiently respond to the burst, and a reference voltage A differential amplifier for extracting the difference in the output voltage of the integrating circuit, and switching the time constant of the integrating circuit from R · (C1 + C2) in the normal state to R · C1 only in the section before and after the rise of the specific burst, and at the same time, in the capacitor C2 An analog SW for applying a reference voltage to charge the reference voltage and a power amplifier whose gain is controlled by the differential amplifier output voltage are also provided. Kuwa該 differential amplifier output voltage transmission output automatic control system of a TDMA transmitter, characterized in that it is constituted by a power amplifier having a voltage variable gain controller that is controlling the gain by.
アンプを介して前記コンデンサＣ２に印加するように構
成したことを特徴とする請求項１記載のＴＤＭＡ送信機
の送信出力自動制御装置。2. A transmission output automatic control apparatus for a TDMA transmitter according to claim 1, wherein a reference voltage is applied to said capacitor C2 via a buffer amplifier during said specific burst.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01449696A JP3457787B2 (en) | 1996-01-30 | 1996-01-30 | Automatic transmission output control device for TDMA transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01449696A JP3457787B2 (en) | 1996-01-30 | 1996-01-30 | Automatic transmission output control device for TDMA transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09214453A JPH09214453A (en) | 1997-08-15 |
| JP3457787B2 true JP3457787B2 (en) | 2003-10-20 |
Family
ID=11862678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01449696A Expired - Fee Related JP3457787B2 (en) | 1996-01-30 | 1996-01-30 | Automatic transmission output control device for TDMA transmitter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3457787B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5272805B2 (en) * | 2009-03-03 | 2013-08-28 | 日本電気株式会社 | Amplifier |
-
1996
- 1996-01-30 JP JP01449696A patent/JP3457787B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09214453A (en) | 1997-08-15 |
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