JPS61296729A - Formation of bonding part of integrated circuit - Google Patents

Formation of bonding part of integrated circuit

Info

Publication number
JPS61296729A
JPS61296729A JP60137690A JP13769085A JPS61296729A JP S61296729 A JPS61296729 A JP S61296729A JP 60137690 A JP60137690 A JP 60137690A JP 13769085 A JP13769085 A JP 13769085A JP S61296729 A JPS61296729 A JP S61296729A
Authority
JP
Japan
Prior art keywords
photoresist film
integrated circuit
solder
connection
solder bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60137690A
Other languages
Japanese (ja)
Inventor
Yuichi Suzuki
悠一 鈴木
Kishio Yokouchi
貴志男 横内
Kazunori Yamanaka
一典 山中
Koichi Niwa
丹羽　紘一
Shinya Hasuo
蓮尾　信也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60137690A priority Critical patent/JPS61296729A/en
Publication of JPS61296729A publication Critical patent/JPS61296729A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To form a required coaxial structure of a bonding part by a method wherein photoresist material is applied to a connection substrate and a part corresponding to an electrode pad is removed by photolithography and the formed groove is filled with solder bump forming material and the material is heated. CONSTITUTION:A card 4 has internal wirings 5 and electrode pads 6 are formed on the surface of the card 4 and then a uniform photoresist film 7 is formed. The photoresist employed in this case is of negative-type and composed of photosensitive polyimide resin. The resist film 7 is subjected to image exposure through a glass mask 8 which has light shielding parts at the positions corresponding to the electrode pads to form a cured photoresist film 17 with piercing holes 27. Successively, solder alloy balls 9 with predetermined sizes are compactly arranged in the piercing holes 27 and heated to melt to form solder bumps 19. The electrode pads 2 and 3 of the integrated circuit chip 1 are bonded to the formed bonding parts (6+19) of the card 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路の接続技術に関する。本発明は、さら
に詳しく述べると、フリップチップ方式を使用して、例
えばＩＣ，ＬＳＩ、超ＬＳＩ等の集積回路チップをプリ
ント配線基板のような接続基板に接続する際に存用な集
積回路接続部を形成する方法に関する。本発明の集積回
路接続部を使用して集積回路チップと基板（カード）を
接続すると、特に高速の信号あるいは大電流の信号をチ
ップ及びカード間で有効にやりとりすることができる。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuit connection technology. More specifically, the present invention provides an integrated circuit connection unit that is useful when connecting an integrated circuit chip such as an IC, LSI, or VLSI to a connection board such as a printed wiring board using a flip-chip method. Concerning how to form. When an integrated circuit chip and a substrate (card) are connected using the integrated circuit connection section of the present invention, particularly high-speed signals or high-current signals can be effectively exchanged between the chip and the card.

〔従来の技術〕[Conventional technology]

本発明者らの研究グループでは、集積回路チップを接続
基板に接続する場合、信号伝送線の接続端子をグランド
面の接続端子が取り囲む形でフリップチップ方式により
接続するのが有利であるという知見を得、別に特許出願
をした（特開昭　−号公報）。ところで、この接続方法
を実現する場合、接続基板上に形成されるべき集積回路
接続部の形成が問題としてあった。例えば、フリップチ
ップ方式における接続部形成方法として従来から用いら
れている方法に、接続基板（カード）又は集積回路チッ
プの入出力端子部に真空蒸着によりハンダバンプを形成
する方法があるというものの、この方法の実施に必要な
装置は高額であり、また、工程が複雑であり、したがっ
て、量産性に劣るという欠点がある。また、ハンダペー
ストを用いて集積回路接続部を印刷する方法が提案され
ているけれども、これでは、大サイズのパターンはとも
かく、合本発明が得ようとしている２００μｌ以下の小
サイズのパターンは実質的に形成不可能であるという欠
点がある。さらに、メタルマスクを用いて、そのマスク
の貫通孔にハンダポールを並べて加熱溶融することによ
りハンダバンプを形成する方法も提案されている。この
接続部形成方法を使用すると、上記した真空蒸着法やハ
ンダペースト法の欠点を確かに解消し得るというものの
、メタルマスクの加工の難かしさに原因して微細な接続
部パターンを得ることができない。実際、この方法を用
いた場合、数１０μｍ以下の幅員をもっ゛た接続部パタ
ーンを得ることができない。The research group of the present inventors has found that when connecting an integrated circuit chip to a connection board, it is advantageous to connect it using the flip-chip method in such a way that the connection terminal of the signal transmission line is surrounded by the connection terminal on the ground plane. A separate patent application was filed (Japanese Unexamined Patent Publication No. Sho No. 1). However, when implementing this connection method, there has been a problem in the formation of integrated circuit connection portions to be formed on the connection substrate. For example, one of the methods conventionally used to form connections in the flip-chip method is to form solder bumps on input/output terminals of connection boards (cards) or integrated circuit chips by vacuum deposition. The equipment required to carry out this method is expensive, and the process is complicated, which makes it difficult to mass-produce. Further, although a method of printing integrated circuit connections using solder paste has been proposed, this method is not suitable for printing large-sized patterns, but it is practically impossible to print small-sized patterns of 200 μl or less, which the present invention seeks to obtain. The disadvantage is that it cannot be formed. Furthermore, a method has been proposed in which solder bumps are formed by using a metal mask and arranging solder poles in the through holes of the mask and heating and melting them. Although this connection formation method can certainly overcome the drawbacks of the vacuum evaporation method and solder paste method described above, it is difficult to obtain a fine connection pattern due to the difficulty of processing the metal mask. Can not. In fact, when this method is used, it is not possible to obtain a connection pattern with a width of several tens of micrometers or less.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は、上記した従来の技術の欠点にかんがみ
て、高速信号伝送可能なチップ接続あるいは大電流の信
号を流す端子から他の端子への漏れ電流の影響を小さく
することができるチップ接続を実現するための、特に信
号伝送線の接続端子をグランド面の接続端子が取り囲む
形の、言わば同軸構造の、集積回路接続部を微細パター
ンでかつ容易に形成する方法を提供することにある。す
なわち、これが合本発明が解決しようとする問題点であ
る。In view of the above-mentioned drawbacks of the conventional technology, an object of the present invention is to provide a chip connection that can transmit high-speed signals or a chip connection that can reduce the influence of leakage current from a terminal that carries a large current signal to other terminals. In order to achieve this, it is an object of the present invention to provide a method for easily forming an integrated circuit connection part in a fine pattern, particularly in a so-called coaxial structure in which a connection terminal on a signal transmission line is surrounded by a connection terminal on a ground plane. That is, this is the problem that the present invention is intended to solve.

〔問題点を解決するための手段〕[Means for solving problems]

本発明者らは、このたび、形成しようとする同軸構造の
接続部と同一形状（平面形状）の電極パッドをもった接
続基板上にフォトレジスト材料を塗布し、次いでフォト
リソグラフィーにより前記電極パッドに対応する部分を
フォトレジスト膜から除去し、形成された断面形状が凹
形の溝にハンダバンプ形成材料を隙間なく充填し、そし
て最後にこの材料を加熱溶融し′て下地電極パッドに溶
着一体化した場合、所望とする同軸構造の集積回路接続
部を形成し得るということを見い出した。The present inventors applied a photoresist material onto a connection substrate having an electrode pad having the same shape (planar shape) as the connection part of a coaxial structure to be formed, and then attached the electrode pad to the connection part using photolithography. The corresponding part was removed from the photoresist film, the formed groove with a concave cross-section was filled with solder bump forming material without any gaps, and finally this material was heated and melted to be welded and integrated with the underlying electrode pad. It has now been discovered that it is possible to form integrated circuit connections of the desired coaxial structure.

本発明による集積回路接続部形成方法は、すなわち、 集積回路チップの信号伝送線及びグランド面の接続端子
が接続されるべき接続基板の表面上に所定の形状の金属
薄膜を被着して電極パッドとなし、感光性ポリイミド樹
脂からなるネガ型フォトレジスト材料を前記接続基板の
表面に全面的に塗布してフォトレジスト膜を形成し、 前記フォトレジスト膜のうち前記電極パッドに対応する
部分以外の領域に選択的に露光を施して゛露光域のフォ
トレジスト膜を不溶化し、前記フォトレジスト膜を現像
及びキユアリングして未露光域のフォトレジスト膜を溶
解除去し、よって、前記電極パッドと同一形状の貫通孔
を有する硬化フォトレジスト膜を得、 前記貫通孔の全体にハンダバンプ形成材料を充填し、そ
して 前記ハンダバンブ形成材料を加熱溶融することによって
所定の形状のハンダバンプを形成するとともにそのバン
ブを下地電極パッドに溶着させることを特徴とする。The method for forming an integrated circuit connection part according to the present invention includes depositing a metal thin film of a predetermined shape on the surface of a connection board to which signal transmission lines and connection terminals on the ground plane of an integrated circuit chip are to be connected, and forming electrode pads. Then, a negative photoresist material made of photosensitive polyimide resin is applied to the entire surface of the connection substrate to form a photoresist film, and an area of the photoresist film other than the part corresponding to the electrode pad is The photoresist film in the exposed area is insolubilized by being selectively exposed to light, and the photoresist film is developed and cured to dissolve and remove the photoresist film in the unexposed area. A cured photoresist film having holes is obtained, the through holes are entirely filled with a solder bump forming material, and the solder bump forming material is heated and melted to form a solder bump in a predetermined shape, and the bump is attached to a base electrode pad. It is characterized by welding.

本発明の実施において、集積回路接続部を同軸構造の形
状となすため、例えば、信号伝送線の接続端子を中央に
配し、それと同心的に環状のグランド面接続端子を配す
ることができる。また、必要に応じて、グランド面接続
端子の形状を環状から矩形に変更することができる。も
ちろん、本発明方法は、これらの同軸構造の接続部の形
成にのみ限定されるものではなく、従来の集積回路接続
部の形成にも有利に適用することができる。In implementing the present invention, in order to form the integrated circuit connection part into a coaxial structure, for example, the connection terminal of the signal transmission line can be arranged in the center, and the annular ground plane connection terminal can be arranged concentrically therewith. Further, the shape of the ground plane connecting terminal can be changed from annular to rectangular as necessary. Of course, the method of the invention is not limited to the formation of connections in these coaxial structures, but can also be advantageously applied to the formation of conventional integrated circuit connections.

本発明を実施する場合、先ず最初に、接続基板（カード
）の接続部分にチップの電極パッドに対応する形状の金
属薄膜、例えばＣｕ、Ａｕ、Ｐｄ。When carrying out the present invention, first of all, a thin metal film, such as Cu, Au, or Pd, having a shape corresponding to the electrode pad of the chip is formed on the connection portion of the connection board (card).

Ｐｄ　−Ａｇ　、Ａｇ　、Ｃｒなど、を蒸着、スパッタ
等により被着して電極パッド（ハンダパッドとも言う）
を形成する。Electrode pads (also called solder pads) are made by depositing Pd-Ag, Ag, Cr, etc. by vapor deposition, sputtering, etc.
form.

電極パッドの形成後、感光性ポリイミド樹脂のネガ型フ
ォトレジスト材料、例えば東し−から入手可能な“フォ
トニースＵ　Ｒ−３１００”（商品名）をスピンコード
等により塗布する。フォトレジスト膜の膜厚は、ハンダ
バンプ形成材料にポール。After the electrode pads are formed, a negative photoresist material made of photosensitive polyimide resin, such as "Photonice UR-3100" (trade name) available from Toshi, is applied using a spin cord or the like. The thickness of the photoresist film depends on the solder bump forming material.

ペースト又はペーストのどれを使うかに左右されるとい
うものの、一般には約２０〜４０μ信であるのが好まし
い。ハンダ合金ペーストを使用する場合のフォトレジス
ト膜の膜厚はハンダ合金ポールの場合のそれの約３〜４
倍とする必要がある。A thickness of about 20 to 40 microns is generally preferred, depending on whether the paste or paste is used. The thickness of the photoresist film when using a solder alloy paste is about 3 to 4 times thicker than that of a solder alloy pole.
It needs to be doubled.

次いで、形成されたフォトレジスト膜を紫外線光等に選
択的に像露光する。この像露光の結果として、フォトレ
ジスト膜の露光域（電極パッドに対応する部分以外の領
域）を不溶化する。引き続いて現像及びキユアリングを
実施して、先の像露光で不溶化せしめられなかった未露
光域のフォトレジスト膜を溶解除去する。電極パッドと
同一形状の貫通孔（凹形溝）を有する硬化フォトレジス
ト膜が得られる− 引き続いて、ハンダバンブの形成のため、先の工程で形
成された凹形の漢にハンダバンプ形成材料、例えばＰｂ
　−３ｎ　、　　Ｉｎ−Ｂ１　、Ｉｎ　−Ｓｎ　。Next, the formed photoresist film is selectively imagewise exposed to ultraviolet light or the like. As a result of this imagewise exposure, the exposed area of the photoresist film (area other than the area corresponding to the electrode pad) is made insoluble. Subsequently, development and curing are performed to dissolve and remove the unexposed areas of the photoresist film that were not insolubilized in the previous imagewise exposure. A cured photoresist film having through holes (concave grooves) having the same shape as the electrode pads is obtained.Subsequently, for the formation of solder bumps, a solder bump forming material, e.g. Pb, is applied to the concave holes formed in the previous step.
-3n, In-B1, In-Sn.

Ｉｎ　−Ｂｉ−３ｎなどのハンダ又はハンダ合金材料を
好ましくは直径約５０〜１００μｍのポール又は粒径約
２〜１０μｍの粉末の形で隙間なく並べるかもしくは充
填し、さもなければハンダペーストを詰め、これを加熱
溶融させる。加熱溶融の温度は、用いられるハンダバン
プ形成材料の溶融温度によって左右されるというものの
、一般的には約５０〜３００℃の温度が用いられる。例
えば、Ｉｎ系のハンダ合金を使用する場合には約６０℃
の温度が好ましく、一方、Ｓｎ系のハンダ合金を使用す
る場合には約２００℃を土建る温度が好ましい。solder or solder alloy material such as In-Bi-3n, preferably in the form of poles with a diameter of about 50-100 μm or powder with a particle size of about 2-10 μm, closely spaced or filled, otherwise packed with solder paste; This is heated and melted. Although the temperature of heating and melting depends on the melting temperature of the solder bump forming material used, a temperature of about 50 to 300° C. is generally used. For example, when using an In-based solder alloy, the temperature is approximately 60°C.
On the other hand, when using a Sn-based solder alloy, a temperature of about 200° C. is preferred.

上記のようにしてハンダバンプ形成材料を加熱溶融させ
ると、所定の形状、例えばバンブ状、球状又は類似の形
状のハンダバンプがレジスト膜の貫通孔内に形成され、
同時に、そのバンブと下地電極パッドとが強力に接合せ
しめられる。When the solder bump forming material is heated and melted as described above, solder bumps having a predetermined shape, such as a bump shape, a spherical shape, or a similar shape, are formed in the through holes of the resist film,
At the same time, the bump and the underlying electrode pad are strongly bonded.

カード上のレジスト膜はそのま＼残して保護膜として利
用してもよ（、また、不必要であるならば、適当な溶剤
を用いて溶解除去してもよい。いずれにしても、最後の
工程として、上記のようにして形成されたカードの集積
回路接続部をそれと整合するチップの電極パッドと接触
させ、介在せるハンダバンプのリフローによりカードと
チップをフリップチップ接合する。The resist film on the card can be left as is and used as a protective film (or, if unnecessary, it can be removed by dissolving it using an appropriate solvent. The process involves contacting the integrated circuit connections of the card formed as described above with the electrode pads of the matching chip, and flip-chip bonding the card and chip by reflowing the intervening solder bumps.

〔実施例〕〔Example〕

第１図は、本発明方法を有利に適用することのできる集
積回路チップの好ましい一例を示した略示図である。チ
ップ１は、図示される通り、信号伝送線のための電極パ
ッド２と、それを取り囲んで形成されたグランド面のた
めの電極パッド３とからなる複合電極パッドを有する。FIG. 1 is a schematic diagram showing a preferred example of an integrated circuit chip to which the method of the invention can be advantageously applied. As shown, the chip 1 has a composite electrode pad consisting of an electrode pad 2 for a signal transmission line and an electrode pad 3 for a ground plane formed surrounding it.

本願明細書では、このような複合電極パッドのことを、
特に、同軸構造をもった電極バンドあるいは接続部と呼
ぶ。このチップ１では、さらに、従来例のように信号伝
送線の電極パッド２及びグランド面の電極パッド３が互
いに独立して配置されたものも含まれている。第２図は
、第１図に示した集積回路チップの線分■−Ｈにそった
断面図である。In this specification, such a composite electrode pad is referred to as
In particular, it is called an electrode band or connection part with a coaxial structure. This chip 1 also includes a chip in which the electrode pad 2 of the signal transmission line and the electrode pad 3 of the ground plane are arranged independently of each other, as in the conventional example. FIG. 2 is a cross-sectional view of the integrated circuit chip shown in FIG. 1 taken along line -H.

本発明方法は、例えば、第３ａ図〜第３ｈ図に断面で示
される一連の工程を経て実施することができる。The method of the present invention can be carried out, for example, through a series of steps shown in cross section in FIGS. 3a to 3h.

先ず最初に、第２図に断面で示される構造をもった集積
回路チップを接続するための接続基板（カード）を用意
する。カード４は、第３ａ図に示されるように、内部配
線５を有する。First, a connection board (card) for connecting an integrated circuit chip having the structure shown in cross section in FIG. 2 is prepared. The card 4 has internal wiring 5, as shown in Figure 3a.

次いで、第３ｂ図に示されるように、カード４の表面上
に電極パフドロを被着する。この電極パッド又はハンダ
パッド６の形状はそれにフリップチップ接合されるべき
集積回路チップ１の電極パッド２及び３の形状に一致す
る。Next, as shown in FIG. 3b, electrode puff foam is applied on the surface of the card 4. The shape of this electrode pad or solder pad 6 corresponds to the shape of the electrode pads 2 and 3 of the integrated circuit chip 1 to be flip-chip bonded thereto.

次いで、第３Ｃ図に示されるように、カード４の全面に
フォトレジストを塗布して均一なフォトレジスト膜７を
形成する。ここで使用するフォトレジストは、前記した
通り、ネガ型であり、そして任意の感光性ポリイミド樹
脂からなることができる。Next, as shown in FIG. 3C, a photoresist is applied to the entire surface of the card 4 to form a uniform photoresist film 7. As mentioned above, the photoresist used here is negative type and can be made of any photosensitive polyimide resin.

次いで、フォトレジスト膜７に貫通孔を作るため、電極
パッド対応部が遮光性を有するガラスマスク８を通して
レジスト膜７に像露光を施す（第３ｄ図）。露光源とし
ては紫外線光などがある。Next, in order to create a through hole in the photoresist film 7, the resist film 7 is subjected to imagewise exposure through a glass mask 8 whose portion corresponding to the electrode pad has a light blocking property (FIG. 3d). Exposure sources include ultraviolet light and the like.

像露光の完了後、フォトレジスト膜７を現像及びキユア
リングしてその未露光部を溶解除去する。After the image exposure is completed, the photoresist film 7 is developed and cured to dissolve and remove the unexposed portion.

第３ｅ図に示されるように貫通孔２７をもった硬化フォ
トレジスト膜１７が得られる。A cured photoresist film 17 with through holes 27 is obtained as shown in FIG. 3e.

引き続いて、上記のようにして形成されたレジスト膜１
７の貫通孔２７に所定のサイズのハンダ合金ポール９を
緻密に整列させる（第３ｆ図）。Subsequently, the resist film 1 formed as described above is
Solder alloy poles 9 of a predetermined size are closely aligned in the through holes 27 of No. 7 (FIG. 3F).

なお、図面では、説明の都合上、答礼に１個のポール９
しか充填していないけれども、孔の幅が大きい場合には
２列もしくはそれ以上にポールを整列することもできる
。In addition, in the drawing, for convenience of explanation, one pole 9 is used for the response.
However, if the width of the hole is large, the poles can be arranged in two or more rows.

ハンダポールを充填した後、約６０〜２５０℃の温度で
そのポールを加熱溶融させる（第３ｇ図）。After filling the solder poles, the poles are heated and melted at a temperature of about 60-250°C (Figure 3g).

ハンダポールが一体となって、図示される通りのハンダ
バンブ１９が形成される。このようにして。Together, the solder poles form a solder bump 19 as shown. In this way.

形成された集積回路接続部のフォトレジスト膜除去後の
状態を断面図で示すと、第３ｈ図に記載される通りであ
る。なお、形成可能な接続部パターン（ハンダバンプ）
の幅は使用するハンダ、）−−／Ｌ／の粒径に応じて、
約５０〜１００μｍである。A cross-sectional view of the formed integrated circuit connection portion after removing the photoresist film is as shown in FIG. 3h. In addition, possible connection patterns (solder bumps)
The width depends on the particle size of the solder used, )--/L/,
It is about 50-100 μm.

最後に、第４図に示されるように、通常のフリップチッ
プ方式を使用して、形成されたカード４の接続部（６＋
１９）に第２図の集積回路チップ１の電極パッド２及び
３を接続する。Finally, the card 4 connections (6+
19) to connect the electrode pads 2 and 3 of the integrated circuit chip 1 shown in FIG.

さらに、上記した接続部形成方法の一部を変更しても、
すなわち、ハンダポールに代えてハンダ粉末やハンダペ
ーストを使用しても、上記と同様な結果を得ることがで
きる。Furthermore, even if a part of the above-mentioned connection part formation method is changed,
That is, even if solder powder or solder paste is used in place of the solder pole, the same results as above can be obtained.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、例えば第１図に示されるような集積回
路チップのための微細な集積回路接続部を容易にかつ大
量に形成することができる。また、このような接続部の
形成が可能となる結果、高速信号あるいは大電流の信号
を集積回路チップと接続基板（カード）との間でやりと
りすることが保証される。According to the present invention, fine integrated circuit connections for integrated circuit chips, such as those shown in FIG. 1, can be easily formed in large quantities. The possibility of forming such connections also ensures that high-speed or high-current signals can be exchanged between the integrated circuit chip and the connection substrate (card).

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明において用いることのできる集積回路
チップの一例を示した略示図、第２図は、第１図に示し
た集積回路チップの線分ＩＩ−ｎにそった部分断面図、 第３ａ図〜第３ｈ図は、それぞれ、本発明方法の好まし
い一例を順を追って示した断面図、そして 第４図は、本発明方法により形成された接続部を用いた
フリップチップ接続の一例を示した断面図である。 図中、１は集積回路チップ、２は信号伝送線の電極パッ
ド、３はグランド面の電極パッド、４は接続基板（カー
ド）、５は内部配線、６は電極パッド、７はフォトレジ
スト膜、８はガラスマスク、そして９はハンダポールで
ある。 本発明の集積回路チップの略示図 第１図 第１図のチップの部分断面図 第２図FIG. 1 is a schematic diagram showing an example of an integrated circuit chip that can be used in the present invention, and FIG. 2 is a partial cross-sectional view of the integrated circuit chip shown in FIG. 1 along line II-n. , FIGS. 3a to 3h are cross-sectional views sequentially showing a preferred example of the method of the present invention, and FIG. 4 is an example of a flip-chip connection using a connection portion formed by the method of the present invention. FIG. In the figure, 1 is an integrated circuit chip, 2 is an electrode pad of a signal transmission line, 3 is an electrode pad on a ground plane, 4 is a connection board (card), 5 is an internal wiring, 6 is an electrode pad, 7 is a photoresist film, 8 is a glass mask, and 9 is a solder pole. FIG. 1 is a schematic diagram of an integrated circuit chip of the present invention. FIG. 2 is a partial cross-sectional view of the chip of FIG. 1.

Claims (1)

【特許請求の範囲】 １、集積回路チップを接続基板に、信号伝送線の接続端
子をグランド面の接続端子が取り囲む形でフリップチッ
プ方式により接続する際の集積回路接続部を形成する方
法であって、 集積回路チップの信号伝送線及びグランド面の接続端子
が接続されるべき接続基板の表面上に所定の形状の金属
薄膜を被着して電極パッドとなし、感光性ポリイミド樹
脂からなるネガ型フォトレジスト材料を前記接続基板の
表面に全面的に塗布してフォトレジスト膜を形成し、 前記フォトレジスト膜のうち前記電極パッドに対応する
部分以外の領域に選択的に露光を施して露光域のフォト
レジスト膜を不溶化し、 前記フォトレジスト膜を現像及びキュアリングして未露
光域のフォトレジスト膜を溶解除去し、よって、前記電
極パッドと同一形状の貫通孔を有する硬化フォトレジス
ト膜を得、 前記貫通孔の全体にハンダバンプ形成材料を充填し、そ
して 前記ハンダバンプ形成材料を加熱溶融することによって
所定の形状のハンダバンプを形成するとともにそのバン
プを下地電極パッドに溶着させることを特徴とする、集
積回路接続部を形成する方法。 ２、前記ハンダバンプ形成材料がハンダ合金ポールであ
る、特許請求の範囲第１項に記載の方法。 ３、前記ハンダバンプ形成材料がハンダ合金粉末である
、特許請求の範囲第１項に記載の方法。 ４、前記ハンダバンプ形成材料がハンダペーストである
、特許請求の範囲第１項に記載の方法。 ５、フォトレジスト膜に紫外線光を照射して選択的露光
を行なう、特許請求の範囲第１項に記載の方法。[Claims] 1. A method for forming an integrated circuit connection part when connecting an integrated circuit chip to a connection board using a flip-chip method in which connection terminals of a signal transmission line are surrounded by connection terminals on a ground plane. Then, a metal thin film of a predetermined shape is coated on the surface of the connection board to which the signal transmission line and the connection terminal of the ground plane of the integrated circuit chip are to be connected to serve as an electrode pad, and a negative type made of photosensitive polyimide resin is used. A photoresist material is applied to the entire surface of the connection substrate to form a photoresist film, and a region of the photoresist film other than a portion corresponding to the electrode pad is selectively exposed to light to remove the exposed area. insolubilizing the photoresist film, developing and curing the photoresist film, and dissolving and removing the photoresist film in the unexposed area, thereby obtaining a cured photoresist film having through-holes having the same shape as the electrode pads; An integrated circuit characterized in that the entire through hole is filled with a solder bump forming material, and the solder bump forming material is heated and melted to form a solder bump in a predetermined shape, and the bump is welded to a base electrode pad. How to form connections. 2. The method of claim 1, wherein the solder bump forming material is a solder alloy pole. 3. The method according to claim 1, wherein the solder bump forming material is a solder alloy powder. 4. The method according to claim 1, wherein the solder bump forming material is a solder paste. 5. The method according to claim 1, wherein selective exposure is performed by irradiating the photoresist film with ultraviolet light.
JP60137690A 1985-06-26 1985-06-26 Formation of bonding part of integrated circuit Pending JPS61296729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60137690A JPS61296729A (en) 1985-06-26 1985-06-26 Formation of bonding part of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60137690A JPS61296729A (en) 1985-06-26 1985-06-26 Formation of bonding part of integrated circuit

Publications (1)

Publication Number Publication Date
JPS61296729A true JPS61296729A (en) 1986-12-27

Family

ID=15204523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60137690A Pending JPS61296729A (en) 1985-06-26 1985-06-26 Formation of bonding part of integrated circuit

Country Status (1)

Country Link
JP (1) JPS61296729A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0282625A (en) * 1988-08-22 1990-03-23 Internatl Business Mach Corp <Ibm> Metallic layer lift-off treatment method
JPH02306655A (en) * 1989-05-04 1990-12-20 Internatl Business Mach Corp <Ibm> Manufacture of circuit package
JPH03504064A (en) * 1989-01-03 1991-09-05 モトローラ・インコーポレーテッド Manufacturing method for high-density solder bumps and substrate sockets for high-density solder bumps
EP0631317A2 (en) * 1993-06-25 1994-12-28 AT&T Corp. Integrated semiconductor devices and method for manufacture thereof
WO1997003460A1 (en) * 1995-07-12 1997-01-30 Hoya Corporation Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip
JP2989271B2 (en) * 1995-07-12 1999-12-13 ホーヤ株式会社 Bare chip mounting board, method of manufacturing bare chip mounting board, and method of forming electrodes of bare chip
US6461953B1 (en) 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure
US6531664B1 (en) * 1999-04-05 2003-03-11 Delphi Technologies, Inc. Surface mount devices with solder
CN110504177A (en) * 2019-08-30 2019-11-26 合肥矽迈微电子科技有限公司 A kind of BGA ball-establishing method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0282625A (en) * 1988-08-22 1990-03-23 Internatl Business Mach Corp <Ibm> Metallic layer lift-off treatment method
JPH03504064A (en) * 1989-01-03 1991-09-05 モトローラ・インコーポレーテッド Manufacturing method for high-density solder bumps and substrate sockets for high-density solder bumps
JPH02306655A (en) * 1989-05-04 1990-12-20 Internatl Business Mach Corp <Ibm> Manufacture of circuit package
EP0631317A2 (en) * 1993-06-25 1994-12-28 AT&T Corp. Integrated semiconductor devices and method for manufacture thereof
EP0631317A3 (en) * 1993-06-25 1998-02-18 AT&T Corp. Integrated semiconductor devices and method for manufacture thereof
US6172417B1 (en) 1993-06-25 2001-01-09 Lucent Technologies Inc. Integrated semiconductor devices
WO1997003460A1 (en) * 1995-07-12 1997-01-30 Hoya Corporation Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip
JP2989271B2 (en) * 1995-07-12 1999-12-13 ホーヤ株式会社 Bare chip mounting board, method of manufacturing bare chip mounting board, and method of forming electrodes of bare chip
US6461953B1 (en) 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure
US6531664B1 (en) * 1999-04-05 2003-03-11 Delphi Technologies, Inc. Surface mount devices with solder
CN110504177A (en) * 2019-08-30 2019-11-26 合肥矽迈微电子科技有限公司 A kind of BGA ball-establishing method

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