WO1997003460A1 - Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip - Google Patents

Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip Download PDF

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Publication number
WO1997003460A1
WO1997003460A1 PCT/JP1996/001905 JP9601905W WO9703460A1 WO 1997003460 A1 WO1997003460 A1 WO 1997003460A1 JP 9601905 W JP9601905 W JP 9601905W WO 9703460 A1 WO9703460 A1 WO 9703460A1
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WO
WIPO (PCT)
Prior art keywords
bare chip
board
printed wiring
glass substrate
wiring board
Prior art date
Application number
PCT/JP1996/001905
Other languages
French (fr)
Japanese (ja)
Inventor
Takeshi Kagatsume
Original Assignee
Hoya Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hoya Corporation filed Critical Hoya Corporation
Priority to JP8527489A priority Critical patent/JP2989271B2/en
Publication of WO1997003460A1 publication Critical patent/WO1997003460A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]

Definitions

  • the present invention relates to a bare chip mounting board in which various semiconductor components are provided on a substrate, a method of manufacturing the bare chip mounting board, and a method of forming electrodes of a bare chip directly mounted on a printed wiring board.
  • a semiconductor chip such as a CPU chip is incorporated in a package, and this package is mounted on a printed circuit board.
  • the semiconductor chip itself is very small compared to the package size. Therefore, if the semiconductor chip is directly mounted on the board, the board can be reduced by the amount of the package omitted. Note that a semiconductor chip not incorporated in such a package is called a bare chip.
  • the wire bonding method is a method in which an electrode pad is arranged around a chip and a thin metal wire is connected from the electrode pad to a wiring pattern.
  • solder balls called bumps are provided on the electrodes of the chip, and the bumps are directed downward to contact the wiring pattern. Then, electrical connection is made by melting the bumps.
  • MCMs multi 'chip' modules
  • lithography As a technology for forming electronic components on a module substrate. It is also possible to increase the density of line patterns. If the wiring pattern can be made denser, the board can be made smaller. However, conventional printed substrates made of glass epoxy, ceramics, or the like do not have sufficient surface smoothness, and the density of electronic components cannot be increased by using lithography.
  • the first reliability issue is that when glass epoxy is used for the board, the alkali ions on the board migrate to the bare chip mounted. Such transfer of the ion force causes malfunction and lowers the reliability.
  • the second issue related to reliability is that the thermal expansion coefficient of the substrate using ceramics or glass epoxy differs greatly from the thermal expansion coefficient of various mounted semiconductor components (for example, silicon). The change is likely to cause poor contact between the substrate and the semiconductor component. Disclosure of the invention
  • the present invention has been made in view of such a point, and an object of the present invention is to provide a bare chip mounting board on which electronic components can be formed with high density and high reliability.
  • Another object of the present invention is to provide a method of manufacturing a bare chip mounting board that can connect a bare chip and a printed wiring board with extremely small electrodes.
  • Still another object of the present invention is to provide a bare chip electrode forming method capable of forming an extremely small electrode on a bare chip. It is to be.
  • a bare chip mounting board in which various semiconductor components are provided on a substrate, a printed wiring board in which a thin film electronic element and a wiring layer are formed on a glass substrate; And a bare chip mounted on a printed wiring board and having electrodes directly connected to the wiring layer.
  • a bare chip mounting board in which various semiconductor components are provided on a substrate, a printed wiring board in which a thin film electronic element and a wiring layer are formed on an alkali-free glass substrate;
  • a bare chip mounted board characterized by having a bare chip mounted on a board and a board is provided.
  • a bare chip mounting board on which various semiconductor components are provided on a substrate, printed wiring in which a thin-film electronic element and a wiring layer are formed on a glass substrate having a thermal expansion coefficient similar to that of silicon
  • a bare chip mounting board comprising: a substrate; and a tape mounted on the printed wiring board.
  • an appropriate portion of the wiring layer connected to the internal semiconductor element is exposed using lithography.
  • An electrode is formed on the surface of the bare chip by lithography, and a wiring layer for connecting to the electrode is formed on the surface of the printed wiring board using a glass substrate by lithography.
  • the bare chip is mounted on the printed wiring board by connecting the electrodes to the wiring layer, and a method for manufacturing a bare chip mounting board is provided.
  • a method for forming an electrode for a bare chip comprising: removing a protective film by lithography 1; and forming a metal for an electrode by lithography 1 at a position where the protective film is removed.
  • thin-film electronic elements are formed at high density on the surface of the glass substrate having high smoothness. Then, by directly connecting and mounting the semiconductor elements in a bare chip state, the entire circuit of the printed wiring board has a high density, and various electronic circuits are formed in a very narrow area.
  • a printed wiring board in which a thin film electronic element and a wiring layer are formed on a non-alkali glass substrate, a mounted base chip, TFT (Thin Film Transistor), diode, resistor, capacitor, etc. Alkali ions do not migrate between the thin-film electronic element and the substrate, and a highly reliable bare chip mounting board can be obtained.
  • TFT Thin Film Transistor
  • the printed wiring board has a thin-film electronic element and a wiring layer formed on a glass substrate having a thermal expansion coefficient similar to that of silicon, a bare chip and a board can be mounted. As a result, it is possible to prevent the occurrence of contact failure due to aging, and to obtain a highly reliable bay chip mounting board.
  • a suitable portion of the wiring layer connected to the internal semiconductor element is exposed to the surface of the bare chip by using a lithography method.
  • the electrodes are formed by lithography and connected to the electrodes.
  • the wiring layer is formed by lithography on the surface of a printed wiring board using a glass substrate, and an electrode about the same as the width of the internal wiring of the bare chip is connected to that electrode. Wiring layer is provided. Since the bare chip is mounted on the printed wiring board by connecting the electrodes of the bare chip to the wiring layer of the printed wiring board, the bare chip can be mounted in a very narrow area.
  • FIG. 1 is a cross-sectional view of a bare chip mounting board of the present invention.
  • Figure 2 is a table showing the composition of Al-free glass that satisfies the coefficient of thermal expansion.
  • FIG. 3 is a diagram showing a process of providing electrode terminals on a bare chip
  • FIG. 4 is a diagram showing a process of wiring electrodes on a printed wiring board (PCB)
  • Figure 5 is a diagram showing the process of mounting a bare chip on a printed wiring board.
  • FIG. 6 is an enlarged view of the joint between the printed wiring board and the bare chip.
  • FIG. 1 is a sectional view of a bare chip mounting board of the present invention. On the glass substrate 1, various thin-film electronic elements are formed, and a bare chip 2 is mounted.
  • the thin film electronic devices shown are TFT 3, diode 4, capacitor 5, and resistor 6.
  • the thin-film electronic element is covered with a protective film 7. These are formed by lithography used in the manufacture of LCD (Liquid Crystal Display) substrates.
  • the bare chip 2 is not provided with an electrode pad, and the electrode terminals are provided directly on the wiring inside the chip.
  • This electrode terminal is A1 wiring provided by lithography on the internal wiring of the chip.
  • the wiring layer provided on the glass substrate 1 by lithography and the A 1 wiring for the electrode of the bare chip 2 are directly connected by the aluminum (A) wiring 8.
  • the glass substrate 1 as a print wiring substrate, it is possible to form a high-density thin-film electronic element by lithography. Moreover, since the bare chip 2 has no pad, it is small in size.
  • alkali-free glass refers to alkali metal contained in glass components. It is a generic term for glass not included.
  • the coefficient of thermal expansion of the glass substrate 1 is close to that of the semiconductor component, a contact failure between the substrate and the semiconductor component does not occur due to aging. Therefore, if glass having a coefficient of thermal expansion similar to that of a semiconductor component is used as the material of the glass substrate, the reliability of the operation of the bare chip mounting board can be improved.
  • the average linear thermal expansion coefficient of the sheet re con which is used as a material of the semiconductor component 3 4 x 1 0 -. And a this is a 7 Z ° about C, and because not to cause contact failure due to aging change, the substrate
  • the average coefficient of linear thermal expansion must be within the range of 30 to 48 x 10-7 ° C (when measured in the temperature range of 100 to 300 ° C).
  • Figure 2 shows the composition of an alkali-free glass that satisfies the requirements for the coefficient of thermal expansion.
  • Figure 2 shows three types of glass.
  • the average linear thermal expansion coefficient of the first example is 37 x 10 -7 / ° C
  • the average linear thermal expansion coefficient of the second example is 43 x 10 -7 / ° C
  • the average linear thermal expansion coefficient of the example is 46 x 10 -7 / ° C. Therefore, all three sufficiently satisfy the above conditions. That is, the coefficient of thermal expansion is similar to the coefficient of thermal expansion of silicon.
  • the glass shown in FIG. 2 has an average coefficient of linear thermal expansion of 30-48 X10-fuda even if each composition is slightly changed. Can be kept within the range of C.
  • a total of 95 mol% or more of 203, A12 ⁇ 3, MgO, CaO, SrO, and BaO is contained, and the content of each component by mol%, S i 0 2 is 62% or more and 68% or less, B203 is 8% or less Less than 12%, A1203 is 9% or more and 13% or less, MgO is 1% or more and 5% or less, Ca0 is 3% or more and 7% or less, SrO is If the glass is 1% or more and less than 3% and B a0 is 1% or more and less than 3%, the average linear thermal expansion coefficient falls within the range of 30 to 48 X 10 -7Z ° C. .
  • the content of each component by mol% is 55 to 65% for S i ⁇ 2, and 7 to 11% for A1203.
  • Pb0 is 1 to 11%
  • Mg0 is 3 to 13%
  • Ca0 is 7 to 20%
  • Zn0 is 3 to 13%
  • Zr ⁇ 2 force is 0 to 3%
  • F2 force is 0-3%
  • As203 force is 0-5%
  • Sb203 force is '0-5% glass'
  • the average linear thermal expansion coefficient is 30- 4 8 X 1 0 - 7 fall within the scope of Bruno ° C.
  • the manufacturing process is roughly divided into the steps of providing electrode terminals on bare chips without pads (padless bare chips), wiring the electrodes on the printed wiring board, and placing the padless bare chips on the printed wiring board. It can be divided into mounting processes.
  • FIG. 3 is a diagram illustrating a process of providing an electrode terminal on a bare chip. The figure shows a cross-sectional view of a bare chip for each step.
  • step 1 (S1) a bare chip 10 without a pad is prepared.
  • a thin-film electronic element is formed between protective films 12 formed on a silicon (Si) substrate 11.
  • This thin-film electronic device is composed of internal circuit wirings 14a to 14c and A1 wirings 13a to 13c.
  • step 2 No special measures are required for connecting the wiring 13a to 13c to the outside.
  • the junction may be very small compared to the electrode pad that has been used. Normally, the electrode pad is about 100 ⁇ m, but the size of the A1 wirings 13a to 13c can be reduced to 2m or less.
  • step 2 (S 2) a protective layer 15 of a protective film is formed on the surface of the bare chip 10. The combined thickness of the protective film 12 and the protective layer 15 has an opening of about 5 zm to about 10 m in consideration of the unevenness of the electrode junction on the printed wiring board side.
  • step 3 (S 3) lithography is performed using a contact mask for wiring layer extraction with a hole at the position where the electrode is to be extracted, and the protective layer 1 on the A 1 wiring 13 a to l 3 c 5 is provided with holes 16a to 16c.
  • the position from which the electrode is to be taken out is arbitrary, and there is no special restriction such as that it must be around the chip.
  • step 4 a metal such as aluminum or copper is vapor-deposited, sputtered, or plated on the surface, and the lithography is performed using a wiring layer forming mask having a hole at a position where the electrode is to be taken out. Then, A 1 wiring 1 ⁇ a to l 7 c for connection is formed. Then, the protective layer 15 provided in Step 2 is removed. The remaining A1 wiring 17a to 17c is used as an electrode to connect to the printed wiring board.
  • a metal such as aluminum or copper is vapor-deposited, sputtered, or plated on the surface, and the lithography is performed using a wiring layer forming mask having a hole at a position where the electrode is to be taken out. Then, A 1 wiring 1 ⁇ a to l 7 c for connection is formed. Then, the protective layer 15 provided in Step 2 is removed. The remaining A1 wiring 17a to 17c is used as an electrode to connect to the printed wiring board.
  • FIG. 4 is a view showing a process of wiring electrodes on a printed wiring board (PCB). This step is performed in parallel with the step of providing electrode terminals on the bare chip. The figure shows a cross-sectional view of the printed wiring board 20 in each step.
  • PCB printed wiring board
  • step 5 (S5) the printed wiring board 20 is formed by attaching the thin film electronic element and the A] wirings 27a to 27f to the glass substrate 21. It is formed by lithography. Lithography has been used in the manufacture of LCD substrates. Thus, a TFT 23, a diode 24, a capacitor 25, and a resistor 26 are formed on the glass substrate 21. These thin-film electronic elements and A ⁇ wirings 27 a to 27 f are covered with a protective film 22.
  • step 6 (S6) the protective film 22 covering the wirings 27 to 27 is connected to the holes 28a to 2 for connection with the bare chip 10 (shown in FIG. 3). 8 Open c.
  • the positions of the holes 28a to 28c are positions that match the positions of the A1 wiring 17a to I7c of the bare chip 10.
  • step 7 A1 wires 29a to 29c for connection are provided on the A1 wires 27c to 27e exposed from the holes.
  • the A1 wirings 29a to 29c are terminals for connecting the bare chip 10 (shown in Fig. 3).
  • FIG. 5 is a diagram showing a process of mounting a bare chip on a printed wiring board.
  • step 8 the bare chip 10 created in step 4 (shown in FIG. 3) is overlaid on the printed wiring board 20 created in step 7 (shown in FIG. 4).
  • the surfaces of the A1 wirings 29a to 29c of the printed wiring board 20 and the A1 wirings 17a to 17c of the bare chip 10 are activated.
  • positioning is performed so that the positions of the A1 wirings 29 a to 29 c of the printed wiring board 20 and the A1 wirings 17 a to l 7 c of the bare chip 10 coincide with each other, and the electric power is supplied.
  • the AI wiring 29 a to 29 c of the printed wiring board 20 and the A 1 Wires 17a to 17c are bonded by surface activated cold bonding o
  • Surface-activated cold bonding is a direct bonding at the atomic level without a reaction layer at the bonding interface, and can be separated reversibly. Such a connection is called a reversible interconnection.
  • step 9 the periphery of the fused A 1 wirings 31 to 33 is hardened with insulating resin 34.
  • FIG. 6 is an enlarged view of the joint between the printed wiring board and the bare chip.
  • the cross section near the electrode of the bare chip 10 is composed of a plurality of layers.
  • the layers shown are the wiring 14 of the chip internal circuit and the protective film 12 from above.
  • An A1 wiring 13 is connected to the wiring 14, and an A1 wiring 17 whose surface is activated is connected to the AI wiring 13.
  • the thickness of wiring 14 inside the chip is 0.8 / m, and the thickness of A] wiring 17 is 5 rr! ⁇ 1 O ⁇ m.
  • the printed wiring board 20 has an A1 wiring with a width of 1.0 to 1.2 m.
  • a portion of the A 1 wiring 27 to be connected to the bare chip is provided with a hole in the protective layer, and an A 1 wiring 29 whose surface is activated is provided.
  • an A 1 wiring 29 whose surface is activated is provided.
  • the printed wiring board 20 is provided with an interface 20a, and can be connected to a computer bus via the interface 20a.
  • the case where aluminum was used for the wiring metal was used.
  • the wiring metal copper or other various alloys may be used in addition to aluminum.
  • a printed wiring board using a glass substrate was not used.
  • a dressless chip can be mounted.
  • the glass substrate has a very high surface smoothness, high-density wiring can be performed using a technique of lithography. Therefore, about 7 or 8 layers of wiring on a glass epoxy substrate can be covered by about 2 layers.
  • lithography a highly integrated thin-film electronic device can be formed on a glass substrate.
  • the size of the bare chip can be reduced.
  • the space for a pad of a general bare chip with a pad around it is 100 to 150 m on one side of a square pad, and the space around the pad is 40 m.
  • the width of the pad space is 200 im
  • the ratio of the space for the nod to the size of the bare chip is as follows.
  • chip size is 4.0 mm, 19%.
  • the small chip size means that the bare chip mounting board can be made smaller, and at the same time, more chips can be cut out from a single substrate in the bare chip manufacturing process.
  • various thin film electrodes are formed on a glass substrate. Since the bare chip is directly mounted on the printed wiring board on which the child elements are formed, the size of the bare chip mounting board can be reduced.
  • bare chip mounting boards can be obtained by using non-alkali glass or a printed wiring board using a glass substrate whose coefficient of thermal expansion is similar to that of silicon. Can be done.
  • print wirings include 56 to 64% by weight of SiO 2, 18 to 24% by A1203, and N by weight%. It has a composition of a 20 force 2-3%, Mg O force 2-6%, Zn force 2-11%, and a thermal expansion coefficient of 3 in the same temperature range of 100-300 °. Glass having a temperature of 1 to 36 X 10 -7 ° C can also be used.
  • the electrodes are directly extracted from the internal wiring of the bare chip by lithography, a pad for the electrode is not required, and the bare chip can be further reduced in size.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

A bare chip mounted board on which electronic parts can be mounted at a high density. A bare chip (2) is mounted on a glass substrate (1) and various kinds of thin film electronic elements are formed on the substrate (1). The thin film electronic elements shown in the figure are TFT (3), a diode (4), a capacitor (5), and a resistor (6), all being covered with a protective film (7). The electronic elements are formed by lithography. A wiring layer is also formed by lithography. The bare chip (2) does not have any pad for electrode and electrode terminals are led out from the wiring layer on the lower surface of the chip (2) and directly connected to the connecting terminals of the substrate (1) through A1 wiring (8). When the glass substrate (1) is used as a printed wiring board in such a way, thin film electronic elements can be formed at a high density by lithography.

Description

明 細 書 ベアチップ搭載ボー ド、 ベアチップ搭載ボー ドの製造方法 及びベアチップの電極形成方法 技 術 分 野  Description Bare chip mounting board, method for manufacturing bare chip mounting board, and method for forming bare chip electrode
本発明は基板上に各種半導体部品が設けられたベアチッ プ搭 載ボー ド、 そのベアチップ搭載ボー ドの製造方法、 及びプリ ン ト配線基板に直接実装されるベアチップの電極形成方法に関し、 特に装置の小型化を図ったベアチップ搭載ボー ド、 小型化を可 能とするベアチップ搭載ボー ドの製造方法、 及び小型化したチ ップをプリ ン ト配線基板に実装するためのベアチップの電極形 成方法に関する。 背 景 技 術  The present invention relates to a bare chip mounting board in which various semiconductor components are provided on a substrate, a method of manufacturing the bare chip mounting board, and a method of forming electrodes of a bare chip directly mounted on a printed wiring board. Miniaturized bare chip mounting board, method of manufacturing bare chip mounting board that enables miniaturization, and method of forming bare chip electrode for mounting miniaturized chip on printed wiring board . Background technology
コ ンピュー夕等の装置の小型高性能化に伴い、 半導体チ ップ を搭載した各種ボー ドの小型化が望まれている。 ボ一 ドを小型 化にするには、 各種半導体チップを小さ く するこ とが有効な手 段である。 一般的には、 C P Uチップ等の半導体チップはパッ ケージに組み込まれており、 このパッケージがプリ ン 卜基板に 実装されている。 半導体チップ自体はパッケージの大きさに く らべ非常に小さい。 従って、 半導体チップを直に基板に実装す れば、パッケージを省ける分ボー ドを小さ く するこ とができる。 なお、 このよう なパッケージに組み込まれていない半導体チッ プは、 ベアチップと呼ばれている。  With the miniaturization and high performance of devices such as computers, miniaturization of various boards equipped with semiconductor chips is desired. To reduce the size of the board, it is effective to reduce the size of various semiconductor chips. Generally, a semiconductor chip such as a CPU chip is incorporated in a package, and this package is mounted on a printed circuit board. The semiconductor chip itself is very small compared to the package size. Therefore, if the semiconductor chip is directly mounted on the board, the board can be reduced by the amount of the package omitted. Note that a semiconductor chip not incorporated in such a package is called a bare chip.
最近では良品保証されたベアチップ （ K G D ： Known Good Die ) が半導体メ一力から出荷されるようになってきており、 各 種ボー ドメ一力もベアチップの入手が可能となってきている。 そこで、 ベアチップを直接プリ ン ト基板に実装するための技術 が重要となる。 Recently, a bare chip (KGD: Known Good) with a guaranteed quality Die) has been shipped from semiconductor manufacturers, and it is becoming possible to obtain bare chips from various board manufacturers. Therefore, the technology for mounting the bare chip directly on the printed circuit board is important.
ベアチップをプリ ン 卜基板に実装する技術としては、 ワイヤ ボンディ ング方式やフ リ ップチップ方式がある。 ワイヤボンデ イ ング方式は、 電極パッ ドをチップ周辺に配置して、 電極パッ ドから配線パターン上へ金属細線で結線する方式である。一方、 フ リ ップチップ方式では、 チップの電極上にバンプと呼ばれる 半田ボールが設けられており、 このバンプを下向きにして配線 パターンに接触させる。 そして、 バンプを溶融させるこ とによ り電気的接続を行う。  Technologies for mounting a bare chip on a printed circuit board include a wire bonding method and a flip chip method. The wire bonding method is a method in which an electrode pad is arranged around a chip and a thin metal wire is connected from the electrode pad to a wiring pattern. On the other hand, in the flip chip method, solder balls called bumps are provided on the electrodes of the chip, and the bumps are directed downward to contact the wiring pattern. Then, electrical connection is made by melting the bumps.
このような技術を用いて、 M C M (マルチ ' チップ ' モジュ ール） 等が製品化されてきている。  MCMs (multi 'chip' modules) and the like have been commercialized using such technologies.
しかし、 ワイヤボンディ ングを行ったり 'ンプを設けるため には、 内部配線に比べ非常に大きな電極用パッ ドが設けられて いなければならない。 つま り、 ワイヤボンディ ング方式ではヮ ィャを機械的に打ちつけるため、 その際の位置誤差の許容範囲 を大き く取らなければならず、 ッ ドを小さ く するこ とができ ない。 一方、 フ リ ップチップ方式では、 ッ ドの間隔を狭くす ると半田同士がショー トする危険性が増大する。 このよう に、 従来の方式ではパッ ドを小さ くするこ とが困難でありべァチッ プの小型化に制限があった。 このため、 ベアチップを搭載した ボー ドの小型化にも限界があつた。  However, in order to perform wire bonding or provide a pump, an electrode pad that is much larger than the internal wiring must be provided. In other words, in the wire bonding method, since the wire is hit mechanically, the allowable range of the position error at that time must be large, and the head cannot be reduced. On the other hand, with the flip-chip method, the risk of short-circuiting between solders increases when the spacing between the pads is reduced. As described above, it is difficult to reduce the size of the pad in the conventional method, and there is a limit to downsizing the tape. For this reason, there was a limit to the miniaturization of boards equipped with bare chips.
なお、 モジュール基板上に電子部品を形成する技術としてリ ソグラフィ一があり、 リ ソグラフィ一を用いれば電子部品や配 線パターンを高密度化するこ とも可能である。 そ して、 配線パ ター ンを高密度化するこ とができればボー ドを小さ くするこ と が可能となる。 ところが、 従来のよう なガラスエポキシやセラ ミ ッ クス等によるプリ ン ト基板は表面の平滑性が十分に得られ ず、 リ ソグラフィ ーを用いても電子部品を高密度化するこ とが できない。 There is lithography as a technology for forming electronic components on a module substrate. It is also possible to increase the density of line patterns. If the wiring pattern can be made denser, the board can be made smaller. However, conventional printed substrates made of glass epoxy, ceramics, or the like do not have sufficient surface smoothness, and the density of electronic components cannot be increased by using lithography.
また、 ベアチップを直接プリ ン ト基板に実装する と、 製造さ れたボー ドの信頼性に関して、 次のよう な問題も生じる。  In addition, if the bare chip is directly mounted on the printed circuit board, the following problems occur with respect to the reliability of the manufactured board.
信頼性に関する第 1 の問題は、 基板にガラスエポキシを用い ると、 基板のアルカ リ イオンが、 搭載されたベアチップに移行 してしまう こ とである。 このよう なアル力 リ イオンの移行は誤 動作の原因となり、 信頼性の低下を招く 。  The first reliability issue is that when glass epoxy is used for the board, the alkali ions on the board migrate to the bare chip mounted. Such transfer of the ion force causes malfunction and lowers the reliability.
信頼性に関する第 2の問題は、 セラ ミ ッ クスやガラスェポキ シを用いた基板の熱膨張率が搭載された各種半導体部品 （例え ばシ リ コ ン） の熱膨張率と大き く 異なるため、 経時変化によ り 基板と半導体部品との間で接触不良が生じ易く なるこ とである。 発 明 の 開 示  The second issue related to reliability is that the thermal expansion coefficient of the substrate using ceramics or glass epoxy differs greatly from the thermal expansion coefficient of various mounted semiconductor components (for example, silicon). The change is likely to cause poor contact between the substrate and the semiconductor component. Disclosure of the invention
本発明はこのよう な点に鑑みてなされたものであり、 電子部 品が高密度に、 かつ信頼性よ く形成できるベアチップ搭載ボー ドを提供するこ とを目的とする。  The present invention has been made in view of such a point, and an object of the present invention is to provide a bare chip mounting board on which electronic components can be formed with high density and high reliability.
また、 本発明の別の目的は、 極めて小さな電極により、 ベア チップとプリ ン ト配線基板とを結線するこ とができるベアチッ プ搭載ボー ドの製造方法を提供するこ とである。  Another object of the present invention is to provide a method of manufacturing a bare chip mounting board that can connect a bare chip and a printed wiring board with extremely small electrodes.
さ らに、 本発明の他の目的は、 ベアチップ上に極めて小さな 電極を形成するこ とができるベアチップの電極形成方法を提供 するこ とである。 Still another object of the present invention is to provide a bare chip electrode forming method capable of forming an extremely small electrode on a bare chip. It is to be.
本発明では上記課題を解決するために、 基板上に各種半導体 部品が設けられたベアチップ搭載ボー ドにおいて、 ガラス基板 上に薄膜電子素子と配線層とが形成されたプリ ン ト配線基板と、 前記プリ ン 卜配線基板上に実装され、 電極が前記配線層に直に 結線されたベアチップと、 を有するこ とを特徴とするベアチッ プ搭載ボー ドが提供される。  In the present invention, in order to solve the above-mentioned problems, in a bare chip mounting board in which various semiconductor components are provided on a substrate, a printed wiring board in which a thin film electronic element and a wiring layer are formed on a glass substrate; And a bare chip mounted on a printed wiring board and having electrodes directly connected to the wiring layer.
また、 基板上に各種半導体部品が設けられたベアチップ搭載 ボー ドにおいて、 無アルカ リ ガラス基板上に薄膜電子素子と配 線層とが形成されたプリ ン ト配線基板と、 前記プリ ン ト配線基 板上に実装されたベアチップと、 を有するこ とを特徴とするベ ァチップ搭載ボー ドが提供される。  Further, in a bare chip mounting board in which various semiconductor components are provided on a substrate, a printed wiring board in which a thin film electronic element and a wiring layer are formed on an alkali-free glass substrate; A bare chip mounted board characterized by having a bare chip mounted on a board and a board is provided.
また、 基板上に各種半導体部品が設け られたベアチップ搭載 ボー ドにおいて、 熱膨張係数がシ リ コ ンと近似しているガラス 基板上に薄膜電子素子と配線層とが形成されたプリ ン ト配線基 板と、 前記プリ ン 卜配線基板上に実装されたべァチ ップと、 を 有するこ とを特徴とするベアチップ搭載ボー ドが提供される。  In addition, in a bare chip mounting board on which various semiconductor components are provided on a substrate, printed wiring in which a thin-film electronic element and a wiring layer are formed on a glass substrate having a thermal expansion coefficient similar to that of silicon A bare chip mounting board comprising: a substrate; and a tape mounted on the printed wiring board.
また、 各種半導体部品を搭載するべァチ ップ搭載ボー ドの製 造方法において、 内部半導体素子に接続された配線層のう ち適 当な部分をリ ソグラフィ ーを用いて露出させた状態のベアチッ プの表面に、 リ ソグラフ ィ 一によ り電極を形成する とともに、 前記電極に接続するための配線層を、 ガラス基板を用いたプリ ン ト配線基板の表面に リ ソグラフィ一によ り形成し、 前記電極 を前記配線層に結線するこ とによ り前記ベアチップを前記プリ ン ト配線基板に実装する、 こ とを特徴とするベアチップ搭載ボ ― ドの製造方法が提供される。 さ らに、 プリ ン ト配線基板に直接実装されるベアチップの電 極形成方法において、 内部回路の配線層が形成された状態のベ ァチップの表面を保護膜で覆い、 電極を取り出すべき位置の前 記保護膜をリ ソグラフィ 一によ り除去し、 前記保護膜が除去さ れた位置に リ ソグラフィ 一によ り電極用金属を形成する、 こ と を特徴とするベアチップの電極形成方法が提供される。 In addition, in the method of manufacturing a base mounting board on which various semiconductor components are mounted, an appropriate portion of the wiring layer connected to the internal semiconductor element is exposed using lithography. An electrode is formed on the surface of the bare chip by lithography, and a wiring layer for connecting to the electrode is formed on the surface of the printed wiring board using a glass substrate by lithography. The bare chip is mounted on the printed wiring board by connecting the electrodes to the wiring layer, and a method for manufacturing a bare chip mounting board is provided. Furthermore, in the method for forming bare chip electrodes directly mounted on a printed wiring board, the surface of the bare chip in which the wiring layer of the internal circuit is formed is covered with a protective film, and the position before the electrode is to be taken out A method for forming an electrode for a bare chip, comprising: removing a protective film by lithography 1; and forming a metal for an electrode by lithography 1 at a position where the protective film is removed. You.
上記に示すベアチップ搭載ボー ドによれば、 ガラス基板の平 滑度の高い表面上に高密度に薄膜電子素子が形成される。 そし て、 半導体素子をベアチップの状態で直接結線し実装するこ と によ り、 プリ ン ト配線基板の回路全体が高密度になり、 非常に 狭い領域内に各種電子回路が形成される。  According to the above-described bare chip mounting board, thin-film electronic elements are formed at high density on the surface of the glass substrate having high smoothness. Then, by directly connecting and mounting the semiconductor elements in a bare chip state, the entire circuit of the printed wiring board has a high density, and various electronic circuits are formed in a very narrow area.
また、 無アルカ リ ガラス基板上に薄膜電子素子と配線層とが 形成されたプリ ン 卜配線基板であるこ とにより、 搭載されるべ ァチップ， T F T (Thin Film Transistor) , ダイオー ド， 抵抗， コンデンサ等の薄膜電子素子と基板との間でアルカ リ イオンの 移行が生じるこ とがな く 、 信頼性の高いベアチップ搭載ボー ド が得られる。  In addition, by using a printed wiring board in which a thin film electronic element and a wiring layer are formed on a non-alkali glass substrate, a mounted base chip, TFT (Thin Film Transistor), diode, resistor, capacitor, etc. Alkali ions do not migrate between the thin-film electronic element and the substrate, and a highly reliable bare chip mounting board can be obtained.
また、 熱膨張係数がシ リ コ ンと近似しているガラス基板上に 薄膜電子素子と配線層とが形成されたプリ ン 卜配線基板である こ とにより、 搭載されるベアチップと基板との間で、 経時変化 による接触不良の発生を防止するこ とができ、 信頼性の高いベ ァチップ搭載ボ一 ドが得られる。  Also, since the printed wiring board has a thin-film electronic element and a wiring layer formed on a glass substrate having a thermal expansion coefficient similar to that of silicon, a bare chip and a board can be mounted. As a result, it is possible to prevent the occurrence of contact failure due to aging, and to obtain a highly reliable bay chip mounting board.
また、上記に示すベアチップ搭載ボー ドの製造方法によれば、 内部半導体素子に接続された配線層のう ち適当な部分を リ ソグ ラフィ 一を用いて露出させた状態のベアチップの表面に、 リ ソ グラフィ一により電極を形成する とともに、 電極に接続するた めの配線層を、 ガラス基板を用いたプリ ン ト配線基板の表面に リ ソグラフィ一により形成するこ とにより、 ベアチップの内部 配線の幅と同程度の大きさの電極と、 その電極を接続するため の配線層が設けられる。 ベアチップの電極をプリ ン ト配線基板 の配線層に結線するこ とによりベアチップをプリ ン ト配線基板 に実装しているので、 非常に狭い領域にベアチップを実装する ことができる。 Further, according to the method of manufacturing a bare chip mounting board described above, a suitable portion of the wiring layer connected to the internal semiconductor element is exposed to the surface of the bare chip by using a lithography method. The electrodes are formed by lithography and connected to the electrodes. The wiring layer is formed by lithography on the surface of a printed wiring board using a glass substrate, and an electrode about the same as the width of the internal wiring of the bare chip is connected to that electrode. Wiring layer is provided. Since the bare chip is mounted on the printed wiring board by connecting the electrodes of the bare chip to the wiring layer of the printed wiring board, the bare chip can be mounted in a very narrow area.
さ らに、 上記に示すベアチップの電極形成方法によれば、 内 部回路の配線層が形成された状態のベアチップの表面を保護膜 で覆い、 電極を取り出すべき位置の保護膜をリ ソグラフィ 一に より除去し、 保護膜が除去された位置に リ ソグラフィ一により 電極用金属を形成するこ とにより、 ベアチップに電極パッ ドが なく とも、 内部の配線層に直接接続された電極端子が設けられ る。 図 面 の 簡 単 な 説 明 図 1 は本発明のベアチップ搭載ボ一 ドの断面図、  Further, according to the bare chip electrode forming method described above, the surface of the bare chip in which the wiring layer of the internal circuit is formed is covered with the protective film, and the protective film at the position where the electrode is to be taken out is lithographically integrated. By removing the protective film and forming the electrode metal by lithography at the position where the protective film has been removed, even if the bare chip does not have an electrode pad, the electrode terminal directly connected to the internal wiring layer is provided. . FIG. 1 is a cross-sectional view of a bare chip mounting board of the present invention.
図 2は熱膨張率の要件を満たした無アル力 リガラスの組成を 示した表、  Figure 2 is a table showing the composition of Al-free glass that satisfies the coefficient of thermal expansion.
図 3は、 ベアチップに電極端子を設ける工程を示す図、 図 4はプリ ン ト配線基板 （ P C B ) に電極を配線する工程を 示す図、  FIG. 3 is a diagram showing a process of providing electrode terminals on a bare chip, FIG. 4 is a diagram showing a process of wiring electrodes on a printed wiring board (PCB),
図 5はプリ ン ト配線基板にベアチップを実装する工程を示す 図、  Figure 5 is a diagram showing the process of mounting a bare chip on a printed wiring board.
図 6はプリ ン ト配線基板とベアチップとの接合部の拡大図で ある。 発明を実施するための最良の形態 FIG. 6 is an enlarged view of the joint between the printed wiring board and the bare chip. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施例を図面に基づいて説明する。  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
図 1 は本発明のベアチップ搭載ボー ドの断面図である。 ガラ ス基板 1 上には、 各種薄膜電子素子が形成されているとともに ベアチップ 2が実装されている。  FIG. 1 is a sectional view of a bare chip mounting board of the present invention. On the glass substrate 1, various thin-film electronic elements are formed, and a bare chip 2 is mounted.
図示されている薄膜電子素子は、 T F T 3、 ダイオー ド 4、 コンデンサ 5、 及び抵抗 6である。 薄膜電子素子は保護膜 7で 覆われている。 これらは、 L C D (液晶表示装置） の基板の製 造に利用されている リ ソグラフ ィ 一によ り形成されている。  The thin film electronic devices shown are TFT 3, diode 4, capacitor 5, and resistor 6. The thin-film electronic element is covered with a protective film 7. These are formed by lithography used in the manufacture of LCD (Liquid Crystal Display) substrates.
ベアチップ 2 には電極用のパッ ドが設け られておらず、 電極 端子がチップの内部の配線に直接設けられている。 この電極端 子はチップの内部配線上に リ ソグラフィ 一によ り設けられた A 1 配線である。  The bare chip 2 is not provided with an electrode pad, and the electrode terminals are provided directly on the wiring inside the chip. This electrode terminal is A1 wiring provided by lithography on the internal wiring of the chip.
そして、 ガラス基板 1 上に リ ソグラフ ィ 一によ り設けられた 配線層と、 ベアチップ 2 の電極用の A 1 配線とが直接アルミ二 ユーム （ A 】 ） 配線 8 により結線されている。  The wiring layer provided on the glass substrate 1 by lithography and the A 1 wiring for the electrode of the bare chip 2 are directly connected by the aluminum (A) wiring 8.
このよう に、 プリ ン ト配線基板と してガラス基板 1 を用いる こ とにより、 リ ソグラフ ィ 一による高密度の薄膜電子素子の形 成が可能となる。 しかも、 ベアチップ 2 はパッ ドが設けられて いないため、 その分小型である。  As described above, by using the glass substrate 1 as a print wiring substrate, it is possible to form a high-density thin-film electronic element by lithography. Moreover, since the bare chip 2 has no pad, it is small in size.
特に、 ガラス基板 1 に無アルカ リ ガラスを用いた場合、 基板 から薄膜電子素子や半導体部品へアルカ リ イオンが移行するこ とがない。 そのため、 アルカ リ イオンの影響で誤動作するこ と がな く 、 ベアチップ搭載ボー ドの動作の信頼性が保たれる。 こ こで、 無アルカ リ ガラスとは、 ガラス成分中にアルカ リ金属を 含まないガラスの総称である。 In particular, when non-alkali glass is used for the glass substrate 1, alkali ions do not transfer from the substrate to the thin-film electronic elements or semiconductor components. Therefore, malfunction does not occur due to the influence of alkali ions, and the reliability of the operation of the board mounted with bare chips is maintained. Here, alkali-free glass refers to alkali metal contained in glass components. It is a generic term for glass not included.
さらに、 ガラス基板 1 の熱膨張率が半導体部品に近ければ、 経時変化により基板と半導体部品との間で接触不良が生じるこ とがない。 そのため、 熱膨張率が半導体部品に近似したガラス を、 ガラス基板の材料として用いれば、 ベアチップ搭載ボ一 ド の動作の信頼性の向上が図れる。 半導体部品の材料として使用 されているシ リ コンの平均線熱膨張係数は 3 4 x 1 0 - 7Z° C 程度であるこ とから、 経時変.化による接触不良を生じさせない ためには、 基板の平均線熱膨張係数が 3 0〜 4 8 X 1 0 - 7 ° Cの範囲内である必要がある （ 1 0 0〜 3 0 0 ° Cの温度帯域 で計測した場合） 。 Further, if the coefficient of thermal expansion of the glass substrate 1 is close to that of the semiconductor component, a contact failure between the substrate and the semiconductor component does not occur due to aging. Therefore, if glass having a coefficient of thermal expansion similar to that of a semiconductor component is used as the material of the glass substrate, the reliability of the operation of the bare chip mounting board can be improved. The average linear thermal expansion coefficient of the sheet re con which is used as a material of the semiconductor component 3 4 x 1 0 -. And a this is a 7 Z ° about C, and because not to cause contact failure due to aging change, the substrate The average coefficient of linear thermal expansion must be within the range of 30 to 48 x 10-7 ° C (when measured in the temperature range of 100 to 300 ° C).
図 2に、 熱膨張率の要件を満たした無アルカ リ ガラスの組成 を示す。  Figure 2 shows the composition of an alkali-free glass that satisfies the requirements for the coefficient of thermal expansion.
この図 2 には 3種類のガラスを示している。 第 1 の例の平均 線熱膨張係数は 3 7 x 1 0 -7/° Cであり、 第 2の例の平均線 熱膨張係数は 4 3 X 1 0 -7/° Cであり、 第 3の例の平均線熱 膨張係数は 4 6 x 1 0 -7/° Cである。 従って、 3つとも上記 の条件を十分に満たしている。 即ち、 シ リ コ ンの熱膨張率に近 似した熱膨張率である。  Figure 2 shows three types of glass. The average linear thermal expansion coefficient of the first example is 37 x 10 -7 / ° C, and the average linear thermal expansion coefficient of the second example is 43 x 10 -7 / ° C. The average linear thermal expansion coefficient of the example is 46 x 10 -7 / ° C. Therefore, all three sufficiently satisfy the above conditions. That is, the coefficient of thermal expansion is similar to the coefficient of thermal expansion of silicon.
ところで、 図 2に示したガラスは、 各組成を若干変化させて も、 平均線熱膨張係数を 3 0 - 4 8 X 1 0 -フダ。 Cの範囲内に 押さえるこ とができる。  By the way, the glass shown in FIG. 2 has an average coefficient of linear thermal expansion of 30-48 X10-fuda even if each composition is slightly changed. Can be kept within the range of C.
第 1 の例に示したガラスの組成を変えた場合 「 S i 0 2 、 B When the composition of the glass shown in the first example is changed, “S i 0 2, B
2 0 3 、 A 1 2 〇 3 、 M g O、 C a O、 S r O、 及び B a O を合量で 9 5モル％以上含有し、 モル％による各成分の含有量 、 S i 0 2 が 6 2 %以上で 6 8 %以下、 B 2 0 3 が 8 %以 上で 1 2 %未満、 A 1 2 0 3 が 9 %以上で 1 3 %以下、 M g O が 1 %以上で 5 %以下、 C a 0が 3 %以上で 7 %以下、 S r O が 1 %以上で 3 %未満、 B a 0が 1 %以上で 3 %未満あるガラ ス」 であれば、 平均線熱膨張係数が 3 0〜 4 8 X 1 0 -7Z° C の範囲内に納まる。 A total of 95 mol% or more of 203, A12〇3, MgO, CaO, SrO, and BaO is contained, and the content of each component by mol%, S i 0 2 is 62% or more and 68% or less, B203 is 8% or less Less than 12%, A1203 is 9% or more and 13% or less, MgO is 1% or more and 5% or less, Ca0 is 3% or more and 7% or less, SrO is If the glass is 1% or more and less than 3% and B a0 is 1% or more and less than 3%, the average linear thermal expansion coefficient falls within the range of 30 to 48 X 10 -7Z ° C. .
また、 第 2の例に示したガラスの組成を変えた場合 「モル％ による各成分の含有量が、 S i 〇 2 が 5 5〜 6 5 %、 A 1 2 0 3 が 7〜 1 1 %、 P b 0が 1 〜 1 1 %、 M g 0が 3〜 1 3 %、 C a 0が 7〜 2 0 %、 Z n 0が 3〜 1 3 %、 Z r 〇 2 力 0〜 3 %、 F 2 力く 0〜 3 %、 A s 2 0 3 力 0〜 5 %、 S b 2 0 3 力、' 0〜 5 %であるガラス」 であれば、 平均線熱膨張係数が 3 0〜 4 8 X 1 0 - 7ノ° Cの範囲内に納まる。 In addition, when the composition of the glass shown in the second example is changed, the content of each component by mol% is 55 to 65% for S i 〇2, and 7 to 11% for A1203. , Pb0 is 1 to 11%, Mg0 is 3 to 13%, Ca0 is 7 to 20%, Zn0 is 3 to 13%, Zr〇2 force is 0 to 3% , F2 force is 0-3%, As203 force is 0-5%, Sb203 force is '0-5% glass', the average linear thermal expansion coefficient is 30- 4 8 X 1 0 - 7 fall within the scope of Bruno ° C.
次に、 図 1 に示すベアチップ搭載ボー ドの製造方法について 説明する。 製造工程は大別して、 パッ ドの無いベアチップ （パ ッ ド レスベアチップ） に電極端子を設ける工程、 プリ ン ト配線 基板に電極を配線する工程、 及びプリ ン 卜配線基板上にパッ ド レスベアチップを実装する工程に分けるこ とができる。  Next, a method of manufacturing the bare chip mounting board shown in FIG. 1 will be described. The manufacturing process is roughly divided into the steps of providing electrode terminals on bare chips without pads (padless bare chips), wiring the electrodes on the printed wiring board, and placing the padless bare chips on the printed wiring board. It can be divided into mounting processes.
図 3はベアチップに電極端子を設ける工程を示す図である。 図には、 各工程毎のベアチップの断面図を示している。  FIG. 3 is a diagram illustrating a process of providing an electrode terminal on a bare chip. The figure shows a cross-sectional view of a bare chip for each step.
ステップ 1 ( S 1 ) において、 パッ ドの無いベアチップ 1 0 を用意する。 このベアチップ 1 0は、 シ リ コ ン （ S i ) 基板 1 1上に成膜された保護膜 1 2の間に、 薄膜電子素子が形成され ている。 この薄膜電子素子は内部回路の配線 1 4 a〜 l 4 c と、 A 1 配線 1 3 a〜 l 3 c とで構成されている。  In step 1 (S1), a bare chip 10 without a pad is prepared. In the bare chip 10, a thin-film electronic element is formed between protective films 12 formed on a silicon (Si) substrate 11. This thin-film electronic device is composed of internal circuit wirings 14a to 14c and A1 wirings 13a to 13c.
なお、 A 】 配線 1 3 a〜 1 3 c 自体に外部と接続するための 特別な処置を必要と しない。 つま り、 従来のベアチップに設け られていた電極パッ ドと比べて接合部は非常に小さ くてよい。 通常電極パッ ドは 1 0 0 ^ m程であつたが、 A 1 配線 1 3 a〜 1 3 cの大きさは 2 m以下にまで小さ くするこ ともできる。 ステップ 2 ( S 2 ) において、 ベアチップ 1 0の表面に保護 膜の保護層 1 5を成膜する。 保護膜 1 2 と保護層 1 5 とを合わ せた厚さは、 プリ ン ト配線基板側の電極接合部の凹凸状態を考 慮し、 5 z m前後から 1 0 m前後程度の開きがある。 A] No special measures are required for connecting the wiring 13a to 13c to the outside. In other words, provided on a conventional bare chip The junction may be very small compared to the electrode pad that has been used. Normally, the electrode pad is about 100 ^ m, but the size of the A1 wirings 13a to 13c can be reduced to 2m or less. In step 2 (S 2), a protective layer 15 of a protective film is formed on the surface of the bare chip 10. The combined thickness of the protective film 12 and the protective layer 15 has an opening of about 5 zm to about 10 m in consideration of the unevenness of the electrode junction on the printed wiring board side.
ステップ 3 ( S 3 ) において、 電極を取り出すべき位置に穴 の開けられた配線層取り出し用コンタク 卜マスクを用いてリ ソ グラフィーを行い、 A 1 配線 1 3 a〜 l 3 c上の保護層 1 5に 穴 1 6 a ~ 1 6 cを設ける。 なお、 電極を取り出すべき位置は 任意であり、 チップの周辺でなければならない等の特別の制約 はない。  In step 3 (S 3), lithography is performed using a contact mask for wiring layer extraction with a hole at the position where the electrode is to be extracted, and the protective layer 1 on the A 1 wiring 13 a to l 3 c 5 is provided with holes 16a to 16c. The position from which the electrode is to be taken out is arbitrary, and there is no special restriction such as that it must be around the chip.
ステップ 4 ( S 4 ) において、 表面にアルミや銅等の金属を 蒸着， スパッタ リ ング又はメ ツキし、 電極を取り出すべき位置 に穴の開けられた配線層形成用マスクを用いてリ ソグラフィ 一 を行い、 結線用の A 1 配線 1 Ί a 〜 l 7 c を形成する。 そして、 ステップ 2において設けられた保護層 1 5を除去する。 残され た A 1 配線 1 7 a 〜 1 7 c力 プリ ン ト配線基板に結線するた めの電極となる。  In step 4 (S4), a metal such as aluminum or copper is vapor-deposited, sputtered, or plated on the surface, and the lithography is performed using a wiring layer forming mask having a hole at a position where the electrode is to be taken out. Then, A 1 wiring 1 Ί a to l 7 c for connection is formed. Then, the protective layer 15 provided in Step 2 is removed. The remaining A1 wiring 17a to 17c is used as an electrode to connect to the printed wiring board.
図 4はプリ ン ト配線基板 （ P C B ) に電極を配線する工程を 示す図である。 この工程は、 ベアチップに電極端子を設けるェ 程と並行して行われる。 図には、 各工程毎のプリ ン ト配線基板 2 0の断面図を示している。  FIG. 4 is a view showing a process of wiring electrodes on a printed wiring board (PCB). This step is performed in parallel with the step of providing electrode terminals on the bare chip. The figure shows a cross-sectional view of the printed wiring board 20 in each step.
ステップ 5 ( S 5 ) において、 このプリ ン ト配線基板 2 0は、 ガラス基板 2 1 に薄膜電子素子と A 】 配線 2 7 a 〜 2 7 f とが リ ソグラフィ 一により形成されている。 リ ソグラフィ 一は、 従 来より L C Dの基板の製造に用いられている ものである。 これ により、 ガラス基板 2 1上に T F T 2 3、 ダイオー ド 2 4、 コ ンデンサ 2 5、 及び抵抗 2 6が形成されている。 これらの薄膜 電子素子及び A 〗 配線 2 7 a〜 2 7 f は、 保護膜 2 2で覆われ ている。 In step 5 (S5), the printed wiring board 20 is formed by attaching the thin film electronic element and the A] wirings 27a to 27f to the glass substrate 21. It is formed by lithography. Lithography has been used in the manufacture of LCD substrates. Thus, a TFT 23, a diode 24, a capacitor 25, and a resistor 26 are formed on the glass substrate 21. These thin-film electronic elements and A〗 wirings 27 a to 27 f are covered with a protective film 22.
ステップ 6 ( S 6 ) において、 八 1 配線 2 7 じ 〜 2 7 6を覆 つている保護膜 2 2に対し、 ベアチップ 1 0 (図 3に示す） と の接続のための穴 2 8 a〜 2 8 cをあける。 この穴 2 8 a〜 2 8 cの位置は、 ベアチップ 1 0の A 1 配線 1 7 a〜 ： I 7 cの位 置と一致するよう な位置である。  In step 6 (S6), the protective film 22 covering the wirings 27 to 27 is connected to the holes 28a to 2 for connection with the bare chip 10 (shown in FIG. 3). 8 Open c. The positions of the holes 28a to 28c are positions that match the positions of the A1 wiring 17a to I7c of the bare chip 10.
ステップ 7 ( S 7 ) において、 穴から露出 した A 1 配線 2 7 c〜 2 7 e上に結線用の A 1 配線 2 9 a〜 2 9 cを設ける。 こ の A 1 配線 2 9 a〜 2 9 cがベアチップ 1 0 (図 3 に示す） を 接続するための端子となる。  In step 7 (S7), A1 wires 29a to 29c for connection are provided on the A1 wires 27c to 27e exposed from the holes. The A1 wirings 29a to 29c are terminals for connecting the bare chip 10 (shown in Fig. 3).
図 5はプリ ン ト配線基板にベアチップを実装する工程を示す 図である。  FIG. 5 is a diagram showing a process of mounting a bare chip on a printed wiring board.
ステップ 8 ( S 8 ) において、 ステップ 4 (図 3に示す） で 作成されたベアチップ 1 0を、 ステップ 7 (図 4 に示す） で作 成されたプリ ン ト配線基板 2 0上に重ね合わせる。 この際、 プ リ ン ト配線基板 2 0の A 1 配線 2 9 a〜 2 9 c とベアチップ 1 0の A 1 配線 1 7 a ~ 1 7 c との表面を活性化させておく 。 そ して、 プリ ン ト配線基板 2 0の A 1 配線 2 9 a〜 2 9 c とベア チップ 1 0の A 1 配線 1 7 a〜 l 7 c との位置が一致するよう に位置決めを行い電気的に接触させる。 これによ り、 プリ ン ト 配線基板 2 0の A I 配線 2 9 a〜 2 9 c とベアチップ 1 0の A 1 配線 1 7 a 〜 1 7 c とが表面活性化常温結合により結合され る o In step 8 (S8), the bare chip 10 created in step 4 (shown in FIG. 3) is overlaid on the printed wiring board 20 created in step 7 (shown in FIG. 4). At this time, the surfaces of the A1 wirings 29a to 29c of the printed wiring board 20 and the A1 wirings 17a to 17c of the bare chip 10 are activated. Then, positioning is performed so that the positions of the A1 wirings 29 a to 29 c of the printed wiring board 20 and the A1 wirings 17 a to l 7 c of the bare chip 10 coincide with each other, and the electric power is supplied. Contact. As a result, the AI wiring 29 a to 29 c of the printed wiring board 20 and the A 1 Wires 17a to 17c are bonded by surface activated cold bonding o
表面活性化常温結合は、 接合界面に反応層のない原子レベル の直接接合であるため、 可逆的に分離するこ とができる。 この よう な結合は、 可逆的ィ ンターコネク シ ョ ンと呼ばれる。  Surface-activated cold bonding is a direct bonding at the atomic level without a reaction layer at the bonding interface, and can be separated reversibly. Such a connection is called a reversible interconnection.
ステップ 9 ( S 9 ) において、 融合した A 1 配線 3 1 〜 3 3 の周りを絶縁樹脂 3 4で固める。  In step 9 (S 9), the periphery of the fused A 1 wirings 31 to 33 is hardened with insulating resin 34.
図 6 はプリ ン ト配線基板とベアチップとの接合部の拡大図で ある。 ベアチップ 1 0の電極付近の断面は、 複数の層から成つ ている。 図示されている層は、 上からチ ップ内部回路の配線 1 4、 保護膜 1 2である。 配線 1 4 には A 1 配線 1 3が接続され ており、 さ らに A I 配線 1 3 には表面が活性化された A 1 配線 1 7が接続されている。 チップ内部の配線 1 4 の厚さは 0 . 8 / mであり、 A 】 配線 1 7の厚さは 5 rr！〜 1 O ^ mである。 プリ ン ト配線基板 2 0 には 1 . 0 〜 1 . 2 m幅の A 1 配線 FIG. 6 is an enlarged view of the joint between the printed wiring board and the bare chip. The cross section near the electrode of the bare chip 10 is composed of a plurality of layers. The layers shown are the wiring 14 of the chip internal circuit and the protective film 12 from above. An A1 wiring 13 is connected to the wiring 14, and an A1 wiring 17 whose surface is activated is connected to the AI wiring 13. The thickness of wiring 14 inside the chip is 0.8 / m, and the thickness of A] wiring 17 is 5 rr! ~ 1 O ^ m. The printed wiring board 20 has an A1 wiring with a width of 1.0 to 1.2 m.
2 7が設けられている。 A 1 配線 2 7 のベアチ ップと接続すベ き部分には保護層に穴があけられており 、 表面が活性化された A 1 配線 2 9が設けられている。 この A 1 配線 2 9の位置にベ ァチップ 1 0の A 1 配線 1 7を密着させるこ とによ り可逆的ィ ン夕一コネク シ ョ ンが行われる。 なお、 A 1 配線 2 9 に対し、 ベアチップ接合用と して金などの金属バンプをあらかじめ形成 しておく と、 接合の信頼性が一層向上する。 27 are provided. A portion of the A 1 wiring 27 to be connected to the bare chip is provided with a hole in the protective layer, and an A 1 wiring 29 whose surface is activated is provided. By bringing the A1 wiring 17 of the bay chip 10 into close contact with the position of the A1 wiring 29, reversible connection is performed. In addition, if metal bumps such as gold are previously formed on the A 1 wiring 29 for bare chip bonding, the bonding reliability is further improved.
プリ ン ト配線基板 2 0 には、 イ ンタフ ェース 2 0 aが設けら れており、 イ ンタフェース 2 0 a を介してコン ピュータのバス に接続するこ とができる。  The printed wiring board 20 is provided with an interface 20a, and can be connected to a computer bus via the interface 20a.
なお、 上記の例では、 配線金属にアルミ を使用したものにつ いて説明したが、 配線金属と してはアルミ の他に銅やその他の 各種合金を使用してもよい。 In the above example, the case where aluminum was used for the wiring metal was used. As the wiring metal, copper or other various alloys may be used in addition to aluminum.
以上のよう にして、 ガラス基板を用いたプリ ン 卜配線基板に ノ、。ッ ドレスべァチップを実装するこ とができる。 こ こで、 ガラ ス基板は表面の平滑度が非常に高いため、 リ ソグラフィ 一の技 術を用いて高密度の配線を行う こ とができる。 従って、 ガラス エポキシの基板において 7層や 8層に していた配線を、 2層程 度で十分に賄う こ とができる。 しかも、 このリ ソグラフィ ーを 用いれば、 ガラス基板上に高集積度の薄膜電子素子を形成する こ とができる。  As described above, a printed wiring board using a glass substrate was not used. A dressless chip can be mounted. Here, since the glass substrate has a very high surface smoothness, high-density wiring can be performed using a technique of lithography. Therefore, about 7 or 8 layers of wiring on a glass epoxy substrate can be covered by about 2 layers. Moreover, by using this lithography, a highly integrated thin-film electronic device can be formed on a glass substrate.
また、 ベアチップにパッ ドが不要になるこ とによ り、 ベアチ ップを小さ くするこ とができる。 例えば、 周辺にパッ ドが設け られている一般的なベアチップのパッ ド用のスペースは、 正方 形のパッ ドの一辺が 1 0 0 〜 1 5 0 〃 m、 パッ ドの周辺に設け られるスペースが 4 0 mである。 こ こで、 パッ ド用のスぺ一 スの幅を 2 0 0 i mと した場合、 ベアチップの大きさに対する ノぐ ッ ド用のスペースの占める割合は以下のよう になる。  Further, since no pad is required for the bare chip, the size of the bare chip can be reduced. For example, the space for a pad of a general bare chip with a pad around it is 100 to 150 m on one side of a square pad, and the space around the pad is 40 m. Here, assuming that the width of the pad space is 200 im, the ratio of the space for the nod to the size of the bare chip is as follows.
チップサイズが 3 . 5 m m 2 の場合、 2 2 % 。 22% if the chip size is 3.5 mm2.
チップサイズが 4 . 0 m m の場合、 1 9 % 。 If the chip size is 4.0 mm, 19%.
チップサイズが 4 · 5 m m の場合、 1 7 % 。 17% for chip sizes of 4.5 mm.
チップサイズが 5 . 0 m m 2 の場合、 1 5 % 。 15% if the chip size is 5.0 mm2.
このよう に、 チップサイズが小さい程パッ ドレスの効果が大 き く なる。 チップサイズが小さいという こ とはベアチップ搭載 ボー ドを小型化できる と同時に、 ベアチップの製造工程におい て、 1枚の基板からより多く のチップが切り 出せるよう になる。 以上説明したよう に本発明では、 ガラス基板上に各種薄膜電 子素子が形成されたプリ ン ト配線基板上にベアチップを直接実 装するよう にしたため、 ベアチップ搭載ボー ドを小型化するこ とができる。 Thus, the smaller the chip size, the greater the effect of the pad. The small chip size means that the bare chip mounting board can be made smaller, and at the same time, more chips can be cut out from a single substrate in the bare chip manufacturing process. As described above, in the present invention, various thin film electrodes are formed on a glass substrate. Since the bare chip is directly mounted on the printed wiring board on which the child elements are formed, the size of the bare chip mounting board can be reduced.
また、 無アルカ リ ガラス、 あるいは熱膨張率がシ リ コンと近 似しているガラス基板を用いたプリ ン ト配線基板を使用するこ とにより、 ベアチップ搭載ボー ドの高信頼性を得るこ とができ る。 このよう なプリ ン 卜配線と しては上記の説明で述べたもの 以外に、 重量％で S i O 2 が 5 6〜 6 4 %、 A 1 2 0 3 が 1 8〜 2 4 %、 N a 2 0力 2〜 3 %、 M g O力 2〜 6 %、 Z n力く 2〜 1 1 %の組成であり、 熱膨張係数が 1 0 0〜 3 0 0 ° じの 温度帯域で 3 1〜 3 6 X 1 0 -7 ° Cであるガラスを用いるこ ともできる。  In addition, high reliability of bare chip mounting boards can be obtained by using non-alkali glass or a printed wiring board using a glass substrate whose coefficient of thermal expansion is similar to that of silicon. Can be done. In addition to those described in the above description, such print wirings include 56 to 64% by weight of SiO 2, 18 to 24% by A1203, and N by weight%. It has a composition of a 20 force 2-3%, Mg O force 2-6%, Zn force 2-11%, and a thermal expansion coefficient of 3 in the same temperature range of 100-300 °. Glass having a temperature of 1 to 36 X 10 -7 ° C can also be used.
また、 リ ソグラフ ィ 一によりベアチップの内部配線から直接 電極を取り出すよう に したため、 電極用のパッ ドが不要となり ベアチップをさ らに小さ くするこ とができる。  In addition, since the electrodes are directly extracted from the internal wiring of the bare chip by lithography, a pad for the electrode is not required, and the bare chip can be further reduced in size.

Claims

請 求 の 範 囲 1 . 基板上に各種半導体部品が設けられたベアチップ搭載 ボー ドにおいて、 Scope of request 1. On a bare chip mounting board on which various semiconductor components are provided on a substrate,
ガラス基板上に薄膜電子素子と配線層とが形成されたプリ ン ト配線基板と、  A printed wiring board in which a thin film electronic element and a wiring layer are formed on a glass substrate,
前記プリ ン 卜配線基板上に実装され、 電極が前記配線層に直 に結線されたベアチップと、  A bare chip mounted on the printed wiring board and having electrodes directly connected to the wiring layer;
を有するこ とを特徴とするベアチップ搭載ボー ド。  A board equipped with bare chips, characterized by having:
2 . 前記ベアチ ップは、 内部配線の任意の位置において、 実質的に前記内部配線と同程度の大きさの電極が取り出されて いるこ とを特徴とする請求項 1 記載のベアチップ搭載ボー ド。  2. The bare chip mounting board according to claim 1, wherein the bare chip has an electrode of substantially the same size as the internal wiring taken out at an arbitrary position of the internal wiring. .
3 . 前記プリ ン ト配線基板は、 前記ガラス基板と して、 無 アルカ リガラスを用いているこ とを特徴とする請求項 1 記載の ベアチップ搭載ボー ド。  3. The bare chip mounting board according to claim 1, wherein the printed wiring board uses non-alkali glass as the glass substrate.
4 . 前記プリ ン 卜配線基板は、 前記ガラス基板と して、 熱 膨張係数がシ リ コンと近似したガラスを用いているこ とを特徴 とする請求項 1 記載のベアチップ搭載ボー ド。  4. The bare chip mounting board according to claim 1, wherein the printed wiring board is made of glass having a thermal expansion coefficient similar to that of silicon as the glass substrate.
δ . 前記プリ ン 卜配線基板は、 前記ガラス基板として、 1 0 0 〜 3 0 0 ° Cの温度帯域における平均線熱膨張係数が 3 0 〜 4 8 X 1 0 - 7 / ° Cの範囲内のガラスを用いているこ とを特 徴とする請求項 4記載のベアチップ搭載ボ一 ド。  δ. The printed circuit board has an average linear thermal expansion coefficient in a temperature range of 100 to 300 ° C. of 30 to 48 × 10−7 / ° C. as the glass substrate. 5. The bare chip mounting board according to claim 4, wherein said glass is used.
6 . 基板上に各種半導体部品が設けられたベアチップ搭載 ボー ドにおいて、  6. On a bare chip mounting board on which various semiconductor components are provided on a substrate,
無アル力 リ ガラス基板上に薄膜電子素子と配線層とが形成さ れたプリ ン ト配線基板と、 前記プリ ン ト配線基板上に実装されたベアチップと、 を有するこ とを特徴とするベアチップ搭載ボー ド。 A printed wiring board in which a thin-film electronic element and a wiring layer are formed on a glass substrate; A bare chip mounting board comprising: a bare chip mounted on the printed wiring board.
7. 前記プリ ン 卜配線基板は、 前記ガラス基板と して、 シ リ コ ンと熱膨張係数が近似したガラスを用いているこ とを特徴 とする請求項 6記載のベアチップ搭載ボ一 ド。  7. The bare chip mounting board according to claim 6, wherein the printed wiring board is made of glass having a thermal expansion coefficient similar to that of silicon as the glass substrate.
8. 前記プリ ン ト配線基板は、 前記ガラス基板と して、 1 0 0〜 3 0 0 ° Cの温度帯域における平均線熱膨張係数が 3 0 〜 4 8 X 1 0 - 7Z° Cの範囲内のガラスを用いているこ とを特 徵とする請求項 7記載のベアチップ搭載ボー ド。 8. The purine DOO wiring board, and with the glass substrate, 1 0 0~ 3 0 0 ° C average linear thermal expansion coefficient of 3 0 ~ 4 8 X 1 0 in the temperature range of - 7 of Z ° C 8. The bare chip mounting board according to claim 7, wherein glass within the range is used.
9. 基板上に各種半導体部品が設けられたベアチップ搭載 ボー ドにおいて、  9. On a bare chip mounting board with various semiconductor components provided on a board,
熱膨張係数がシ リ コンと近似しているガラス基板上に薄膜電 子素子と配線層とが形成されたプリ ン ト配線基板と、  A printed wiring board in which a thin-film electronic element and a wiring layer are formed on a glass substrate having a thermal expansion coefficient similar to that of silicon;
前記プリ ン ト配線基板上に実装されたべァチップと、 を有するこ とを特徴とするベアチップ搭載ボー ド。  A bare chip mounting board comprising: a base chip mounted on the printed wiring board.
1 0. 前記プリ ン ト配線基板は、 前,dガラス基板と して、 1 0 0〜 3 0 0 ° Cの温度帯域における平均線熱膨張係数が 3 0〜 4 8 X 1 0 -7/° Cの範囲内のガラスを用いているこ とを 特徴とする請求項 9記載のベアチップ搭載ボー ド。 1 0. The purine DOO wiring board, prior to, and the d glass substrate, 1 0 0-3 0 0 average linear thermal expansion coefficient in a temperature range of ° C is 3 0~ 4 8 X 1 0 - 7 / 10. The bare chip mounting board according to claim 9, wherein glass within a temperature range of ° C is used.
1 1. 各種半導体部品を搭載するベアチ ップ搭載ボー ドの 製造方法において、  1 1. In the manufacturing method of the bare chip mounting board for mounting various semiconductor parts,
内部半導体素子に接続された配線層のう ち適当な部分を リ ソ グラフ ィーを用いて露出させた状態のベアチップの表面に、 リ ソグラフィ ー又はメ ツキにより電極を形成する とともに、 前記 電極に接続するための配線層を、 ガラス基板を用いたプリ ン 卜 配線基板の表面にリ ソグラフィ一によ り形成し、 前記電極を前記配線層に結線するこ とによ り前記ベアチップ を前記プリ ン ト配線基板に実装する、 An electrode is formed by lithography or plating on the surface of the bare chip in which an appropriate portion of the wiring layer connected to the internal semiconductor element is exposed using lithography, and an electrode is formed on the bare chip. A wiring layer for connection is formed by lithography on the surface of a printed wiring board using a glass substrate. Mounting the bare chip on the printed wiring board by connecting the electrodes to the wiring layer;
こ とを特徴とするベアチップ搭載ボー ドの製造方法。  A method for manufacturing a board mounted with bare chips, characterized by the above.
1 2 . 前記ベアチップを前記プリ ン ト配線基板に実装する 際には、 表面が活性化された金属同士を接合するこ とによ り、 ベアチップの電極を前記プリ ン 卜配線基板の配線層に結線する こ とを特徴とする請求項 1 1 記載のベアチップ搭載ボー ドの製 造方法。  12. When mounting the bare chip on the printed wiring board, the electrodes of the bare chip are connected to the wiring layer of the printed wiring board by bonding the metals whose surfaces are activated. 12. The method for producing a bare chip mounting board according to claim 11, wherein the connection is performed.
1 3 . プリ ン ト配線基板に直接実装されるベアチップの電 極形成方法において、  1 3. In the method of forming bare chip electrodes directly mounted on the printed circuit board,
内部回路の配線層が形成された状態のベアチップの表面を保 護膜で覆い、  Cover the surface of the bare chip with the wiring layer of the internal circuit formed with a protective film,
電極を取り出すべき位置の前記保護膜を リ ソグラフィ 一によ り除去し、  The protective film at the position where the electrode is to be removed is removed by lithography,
前記保護膜が除去された位置に リ ソグラフィ ー又はメ ツキに より電極用金属を形成する、  Forming an electrode metal by lithography or plating at a position where the protective film has been removed;
こ とを特徴とするベアチップの電極形成方法。  A method for forming bare chip electrodes, comprising:
PCT/JP1996/001905 1995-07-12 1996-07-09 Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip WO1997003460A1 (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0900971A1 (en) * 1997-09-09 1999-03-10 Glasbau Hahn GmbH & Co. KG Illumination device with LED's mounted on a glass plate
US6377292B1 (en) * 1999-04-23 2002-04-23 Oki Data Corporation LED print head with reduced reflection of light leaking from edges of LED array chips
US6610934B2 (en) 2001-05-31 2003-08-26 Hitachi, Ltd. Semiconductor module and method of making the device
AT413170B (en) * 2003-09-09 2005-11-15 Austria Tech & System Tech Thin film arrangement has substrate in form of circuit board with insulating material base body, metal lamination as conducting coating forming base electrode and flattened at thin film component position
AT500259B1 (en) * 2003-09-09 2007-08-15 Austria Tech & System Tech THIN-LAYER ASSEMBLY AND METHOD FOR PRODUCING SUCH A THIN-LAYER ASSEMBLY
US8103739B1 (en) 1998-08-20 2012-01-24 Gautier Taylor S Optimizing server delivery of content by selective inclusion of optional data based on optimization criteria
US11744015B2 (en) 2010-07-02 2023-08-29 Schott Ag Interposer and method for producing holes in an interposer

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150671A (en) * 1975-06-19 1976-12-24 Sharp Kk Method of fixing electronic parts
JPS6042246A (en) * 1983-08-18 1985-03-06 Toshiba Corp Glass for substrate
JPS61124145A (en) * 1984-11-20 1986-06-11 Fujitsu Ltd Manufacture of semiconductor device
JPS61296729A (en) * 1985-06-26 1986-12-27 Fujitsu Ltd Formation of bonding part of integrated circuit
JPS6213085A (en) * 1985-07-11 1987-01-21 Fujitsu Ltd Manufacture of photodetector
JPS63101085A (en) * 1986-10-16 1988-05-06 Fuji Electric Co Ltd Diffused joining method
JPS63122132A (en) * 1986-11-11 1988-05-26 Matsushita Electric Ind Co Ltd Micro-forming method for electrically connecting material
JPH01140635A (en) * 1987-11-27 1989-06-01 Hitachi Ltd Minute conductor electric connection board
JPH04103142A (en) * 1990-08-23 1992-04-06 Hitachi Ltd Glass plate package and semiconductor device
JPH05235099A (en) * 1992-02-21 1993-09-10 Toshiba Corp Circuit device mounting semiconductor

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150671A (en) * 1975-06-19 1976-12-24 Sharp Kk Method of fixing electronic parts
JPS6042246A (en) * 1983-08-18 1985-03-06 Toshiba Corp Glass for substrate
JPS61124145A (en) * 1984-11-20 1986-06-11 Fujitsu Ltd Manufacture of semiconductor device
JPS61296729A (en) * 1985-06-26 1986-12-27 Fujitsu Ltd Formation of bonding part of integrated circuit
JPS6213085A (en) * 1985-07-11 1987-01-21 Fujitsu Ltd Manufacture of photodetector
JPS63101085A (en) * 1986-10-16 1988-05-06 Fuji Electric Co Ltd Diffused joining method
JPS63122132A (en) * 1986-11-11 1988-05-26 Matsushita Electric Ind Co Ltd Micro-forming method for electrically connecting material
JPH01140635A (en) * 1987-11-27 1989-06-01 Hitachi Ltd Minute conductor electric connection board
JPH04103142A (en) * 1990-08-23 1992-04-06 Hitachi Ltd Glass plate package and semiconductor device
JPH05235099A (en) * 1992-02-21 1993-09-10 Toshiba Corp Circuit device mounting semiconductor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MICROFILM OF THE SPECIFICATION AND DRAWINGS ANNEXED TO THE WRITTEN APPLICATION OF JAPANESE UTILITY MODEL, Application No. 111208/1980 (Laid-open No. 35051/1982) (ROCOH CO., LTD.), 24 February 1982. *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0900971A1 (en) * 1997-09-09 1999-03-10 Glasbau Hahn GmbH & Co. KG Illumination device with LED's mounted on a glass plate
US8103739B1 (en) 1998-08-20 2012-01-24 Gautier Taylor S Optimizing server delivery of content by selective inclusion of optional data based on optimization criteria
US6377292B1 (en) * 1999-04-23 2002-04-23 Oki Data Corporation LED print head with reduced reflection of light leaking from edges of LED array chips
US6610934B2 (en) 2001-05-31 2003-08-26 Hitachi, Ltd. Semiconductor module and method of making the device
AT413170B (en) * 2003-09-09 2005-11-15 Austria Tech & System Tech Thin film arrangement has substrate in form of circuit board with insulating material base body, metal lamination as conducting coating forming base electrode and flattened at thin film component position
AT500259B1 (en) * 2003-09-09 2007-08-15 Austria Tech & System Tech THIN-LAYER ASSEMBLY AND METHOD FOR PRODUCING SUCH A THIN-LAYER ASSEMBLY
US7551454B2 (en) 2003-09-09 2009-06-23 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Thin-film assembly and method for producing said assembly
US11744015B2 (en) 2010-07-02 2023-08-29 Schott Ag Interposer and method for producing holes in an interposer

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