JPS61269351A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS61269351A
JPS61269351A JP60111214A JP11121485A JPS61269351A JP S61269351 A JPS61269351 A JP S61269351A JP 60111214 A JP60111214 A JP 60111214A JP 11121485 A JP11121485 A JP 11121485A JP S61269351 A JPS61269351 A JP S61269351A
Authority
JP
Japan
Prior art keywords
lead frame
plating
stitching
section
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60111214A
Other languages
Japanese (ja)
Inventor
Yasuhiko Ishii
康彦 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP60111214A priority Critical patent/JPS61269351A/en
Publication of JPS61269351A publication Critical patent/JPS61269351A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive the decrease of the consumption of noble metals and the improvement of demolding characteristics between a gate section for a plastic runner and a lead frame simultaneously by plating only a stitching land, an island section and the lower surface of the gate section for the plastic runner with Ag or Au in an uppermost layer. CONSTITUTION:A semiconductor chip is loaded on an island section, stitching leads and electrodes for the semiconductor chip are connected by metallic small- gage wires, and a lead frame is sealed with a resin including the semiconductor chip and the stitching lands 2. Plating layers 9 consisting of Au or Ag in uppermost layers are also shaped in a section 12 where a resin injection runner passes on a resin mold process besides the island section and the stitching lands at that time. There is no plating layer 9 composed of Au or Ag in other sections. Accordingly, not only the consumption of the noble metals can be reduced but also demolding characteristics on molding are improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームの構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a lead frame for a semiconductor device.

〔従来の技術〕[Conventional technology]

従来半導体装置は、第４図に示す通りリードフレームｌ
の全体を０．１〜１．０關厚程度の金属板からプレス又
はエツチングの技術で所定の形状を形成し、ステッチラ
ンド２およびアイランド部３に金や銀のメッキを施した
もので、半導体チップ４をアイランド部３に搭載した後
ステッチランド２と半導体チップ４の電極とを金属細線
５で結線、シ、その後半導体チップ４とステッチ２ンド
２を含んで樹脂で封止している。リードフレームの金属
構造は一般的には第４図（ロ）の如く、素材６はＦｅ。A conventional semiconductor device has a lead frame l as shown in Fig. 4.
A predetermined shape is formed from a metal plate approximately 0.1 to 1.0 thick by pressing or etching technology, and the stitch land 2 and island portion 3 are plated with gold or silver. After the chip 4 is mounted on the island part 3, the stitch lands 2 and the electrodes of the semiconductor chip 4 are connected with thin metal wires 5, and then the semiconductor chip 4 and the stitch lands 2 are sealed with resin. The metal structure of the lead frame is generally as shown in FIG. 4 (b), and the material 6 is Fe.

Ｎｉ、Ｃｕ又はそれらの合金を薄く圧延した板を用い、
所定の形状にプレス又はエツチングで形成する。次に防
錆を目的としたＣｕメッキ層７と製造工程中の熱履歴に
よる相互拡散を防止するバリヤ一層８をはさんでＡｇメ
ッキ又はＡｕメッキ９を施こしている。この最上層のメ
ッキ層９は、ワイヤーポンディングに於ける強度確保と
耐腐食性及びチップとアイランドの電気的、熱的特性を
確保する為に行なわれ、第２図に示すように、アイラン
ド部３とステッチランド３とにのみ設けられる。Using a thinly rolled plate of Ni, Cu or their alloys,
Form into a predetermined shape by pressing or etching. Next, Ag plating or Au plating 9 is applied between a Cu plating layer 7 for rust prevention and a barrier layer 8 for preventing mutual diffusion due to thermal history during the manufacturing process. This uppermost plating layer 9 is applied to ensure strength and corrosion resistance during wire bonding, as well as to ensure electrical and thermal characteristics of the chip and the island. 3 and stitch land 3 only.

この中で素材６の種類によｌｃｕメッキ層７とバリヤ一
層８とは省略される事もある。Depending on the type of material 6, the LCU plating layer 7 and the barrier layer 8 may be omitted.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来％Ａｇメッキ又はＡｕメッキ９は、リードフレーム
全体かもしくは近年貴金属削減を目的にステッチランド
２及びアイランド３にのみ施されている。しかし、ステ
ッチランド２及びアイランド３のみにＡｇメッキ又はＡ
ｕメッキ９を施こすと、第３図（５）、（Ｂ）に示す通
シブラスチックモールド成形済品１０をプラスチックラ
ンナーのゲート部１１と切り離す際、プラスチックラン
ナーのゲート部１１とリードフレームの離型性が悪く、
プラスチックランナーのゲート残シが発生する問題があ
る。Conventionally, Ag plating or Au plating 9 has been applied to the entire lead frame or only to stitch lands 2 and islands 3 in recent years for the purpose of reducing precious metals. However, only stitch land 2 and island 3 are plated with Ag or A.
When the U-plating 9 is applied, when separating the through plastic molded product 10 shown in FIGS. 3(5) and 3(B) from the gate part 11 of the plastic runner, the separation between the gate part 11 of the plastic runner and the lead frame will be reduced. Poor shape,
There is a problem with gate residue on the plastic runner.

〔問題点を解決するための手段〕[Means for solving problems]

本発明では、最上層のＡｇメッキ又はＡｕメッキをステ
ッチランド、アイランド部の他に、プラスチックランナ
ーのゲート部の下面にのみ施こし、貴金属削減とプラス
チックランナーのゲート部とリードフレームの離型性と
を同時に図っている。In the present invention, the top layer of Ag plating or Au plating is applied only to the bottom surface of the gate part of the plastic runner in addition to the stitch land and island parts, thereby reducing the amount of precious metal and improving the mold releasability of the gate part of the plastic runner and the lead frame. We are trying to do this at the same time.

〔実施例〕〔Example〕

次に図面を用いて本発明を説明する。 Next, the present invention will be explained using the drawings.

第１図は本発明の一実施例によるリードフレームを示し
たもので、ＡｕもしくはＡｇのメッキ層９はアイランド
部３とステッチランド２の外に樹脂モールド工程時に樹
脂注入ランナーが通る部分１２にも設けられている。そ
の他の部分にはＡｕもしくはＡｇのメッキ層９はない。FIG. 1 shows a lead frame according to an embodiment of the present invention, in which a plating layer 9 of Au or Ag is applied not only to the island portion 3 and the stitch land 2 but also to a portion 12 through which a resin injection runner passes during the resin molding process. It is provided. There is no Au or Ag plating layer 9 in other parts.

このため、貴金属の消費量を削減できる上にモールド時
の離型性も改善される。Therefore, not only can consumption of precious metals be reduced, but also mold releasability during molding is improved.

〔発明の効果〕〔Effect of the invention〕

このように、本発明によれば安価でモールド工程時の離
型性も良い半導体装置用リードフレームを得ることがで
きる。As described above, according to the present invention, it is possible to obtain a lead frame for a semiconductor device that is inexpensive and has good mold releasability during the molding process.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す平面図である。 第２図は従来のリードフレームの平面図である。 第３図（Ａ）、（Ｂ）はプラスチックモールド工程を示
す平面図とそのＡ−Ａ’断面図である。 第４図（５）、（Ｂ）は従来の半導体装置に使用されて
いるリードフレームを示す素子取付後の平面図およびそ
のＢ−Ｂ／断面での金属構造を示す断面図である。 １・・・・・・リードフレーム、２・・・・・・ステッ
チランド、３・・・・・・アイランド部、４・・・・・
・半導体チップ、５・・・・・・ボンディング細線、６
・・・・・・Ｆｅ、Ｎｉ、Ｃｕ又はその合金、７・・・
・・・Ｃｕメッキ層、８・・・・・・バリヤ一層（Ｎｉ
等）、９・・・・・・Ａｇメッキ層（又はＡｕメッキ）
。 １０・・・・・・プラスチックモールド成形品、１１・
・・・・・プラスチックランナーのゲート部、１２・・
・・・・リードフレームプラスチックランナーの下面。FIG. 1 is a plan view showing one embodiment of the present invention. FIG. 2 is a plan view of a conventional lead frame. FIGS. 3(A) and 3(B) are a plan view and a sectional view taken along the line AA' of the plastic molding process. FIGS. 4(5) and 4(B) are a plan view showing a lead frame used in a conventional semiconductor device after an element is attached, and a cross-sectional view showing the metal structure taken along the line B-B. 1...Lead frame, 2...Stitch land, 3...Island part, 4...
・Semiconductor chip, 5... Bonding thin wire, 6
...Fe, Ni, Cu or alloy thereof, 7...
... Cu plating layer, 8 ... Barrier layer (Ni
etc.), 9...Ag plating layer (or Au plating)
. 10...Plastic molded product, 11.
...Gate part of plastic runner, 12...
...The bottom surface of the lead frame plastic runner.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を搭載するアイランドと外部リードとを持つ
リードフレームにおいて、樹脂封入時樹脂ランナーのゲ
ート部の下面に相当する部分およびアイランド部とステ
ッチランド部とにのみ銀又は金のメッキを有する事を特
徴とする半導体装置用リードフレーム。A lead frame having an island on which a semiconductor element is mounted and an external lead is characterized by having silver or gold plating only on the part corresponding to the lower surface of the gate part of the resin runner when resin is encapsulated, and on the island part and stitch land part. Lead frame for semiconductor devices.
JP60111214A 1985-05-23 1985-05-23 Lead frame for semiconductor device Pending JPS61269351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60111214A JPS61269351A (en) 1985-05-23 1985-05-23 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60111214A JPS61269351A (en) 1985-05-23 1985-05-23 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS61269351A true JPS61269351A (en) 1986-11-28

Family

ID=14555414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60111214A Pending JPS61269351A (en) 1985-05-23 1985-05-23 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS61269351A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS554922A (en) * 1978-06-26 1980-01-14 Hitachi Ltd Lead frame
JPS6017939A (en) * 1983-07-11 1985-01-29 Nec Corp Lead frame for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS554922A (en) * 1978-06-26 1980-01-14 Hitachi Ltd Lead frame
JPS6017939A (en) * 1983-07-11 1985-01-29 Nec Corp Lead frame for semiconductor device

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