JPS61256267A - Method for testing semiconductor integrated circuit - Google Patents
Method for testing semiconductor integrated circuitInfo
- Publication number
- JPS61256267A JPS61256267A JP60098097A JP9809785A JPS61256267A JP S61256267 A JPS61256267 A JP S61256267A JP 60098097 A JP60098097 A JP 60098097A JP 9809785 A JP9809785 A JP 9809785A JP S61256267 A JPS61256267 A JP S61256267A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- voltage
- semiconductor integrated
- frequency amplifier
- under test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、アナログ加算、減算機能を有する半導体集積
回路（以下、被試験集積回路と称す）の動特性試験方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for testing dynamic characteristics of a semiconductor integrated circuit (hereinafter referred to as an integrated circuit under test) having analog addition and subtraction functions.
（従来の技術）
従来の被試験集積回路の動特性試験のための回路を第３
図に示す。同図において、被試験集積回路１に電源２を
供給し、正弦波信号発生器３から規定の入力信号電圧を
可変抵抗器４、位相調節器５を通して被試験集積回路１
の測定入力端子６゜７に印加する方式で行なわれる。こ
のとき、位相調節器５で入力端子６，７間の入力信号位
相差を１８０度に設定固定化し、可変抵抗器４を調節し
て、被試験集積回路１の加算出力端子８および減算出力
端子９の出力電圧を最小値に合わせる。なお、被試験集
積回路１は電源２より動作電圧ＶＣＣが与えられ、内部
の加算回路１０および減算回路１１が動作状態に保たれ
る。この状態を変えずに、電子電圧計１２．１３を用い
て、被試験集積回路１の動特性を試験することができる
。つぎに被試験集積回路１を交換して、同一品種で別の
集積回路の動特性を測定する場合は、上記の調節、再設
定を実行する必要がある。集積回路では、１８０度位相
差設定のばらつきは極めて小さく無視できるが、アナロ
グ加減算の回路利得のばらつきは測定上無視できないの
で、通常、動特性試験の際に５可変抵抗器４によるレベ
ル調整が個々の被測定集積回路ごとに必要となる。(Prior art) A conventional circuit for dynamic characteristic testing of an integrated circuit under test is
As shown in the figure. In the figure, a power supply 2 is supplied to the integrated circuit under test 1, and a specified input signal voltage is applied from a sine wave signal generator 3 to the integrated circuit under test through a variable resistor 4 and a phase adjuster 5.
This is done by applying the signal to the measurement input terminal 6°7. At this time, the input signal phase difference between the input terminals 6 and 7 is set and fixed at 180 degrees using the phase adjuster 5, and the variable resistor 4 is adjusted to connect the addition output terminal 8 and the subtraction output terminal of the integrated circuit under test 1. Adjust the output voltage of 9 to the minimum value. Note that the integrated circuit under test 1 is supplied with the operating voltage VCC from the power supply 2, and the internal addition circuit 10 and subtraction circuit 11 are kept in an operating state. The dynamic characteristics of the integrated circuit under test 1 can be tested using the electronic voltmeters 12 and 13 without changing this state. Next, when replacing the integrated circuit under test 1 and measuring the dynamic characteristics of another integrated circuit of the same type, it is necessary to perform the above adjustment and resetting. In integrated circuits, the variation in the 180 degree phase difference setting is extremely small and can be ignored, but the variation in the circuit gain of analog addition and subtraction cannot be ignored in measurement. required for each integrated circuit under test.
（発明が解決しようとする問題点）
従来の技術では、入力信号調整用に可変抵抗器を使用し
ていたが、これは入力電圧を変化さゼでも、位相変化が
ない反面、被試験集積回路の個々ごとに機械的調整が必
要なため自動化に適していない欠点があった。(Problem to be Solved by the Invention) In the conventional technology, a variable resistor was used to adjust the input signal, but although this did not cause any phase change even when the input voltage was changed, It has the disadvantage that it is not suitable for automation because it requires mechanical adjustment for each individual.
本発明の目的は、従来の欠点を解消し、外部からの電圧
または、電流で制御が可能であり、位相特性のフラット
な電子式アッテネータを提供し、自動計測を可能にする
ことである。An object of the present invention is to eliminate the conventional drawbacks, provide an electronic attenuator that can be controlled by an external voltage or current, and has a flat phase characteristic, and enables automatic measurement.
（問題点を解決するための手段）
本発明の半導体集積回路の試験方法は、被試験集積回路
の入力端子に対して、電圧制御型可変容量素子と高入力
インピーダンスを有する高周波増幅器とを組合わせて構
成された電子式アッテネータおよび位相調節器を介して
、所定の入力信号を結合したものである。(Means for Solving the Problems) The semiconductor integrated circuit testing method of the present invention combines a voltage-controlled variable capacitance element and a high-frequency amplifier having high input impedance with respect to the input terminal of the integrated circuit under test. A predetermined input signal is coupled through an electronic attenuator and a phase adjuster configured as follows.
（作 用）
本発明によると、電圧制御型可変容量素子への印加電圧
を制御することによって、個々の被試験集積回路のレベ
ル調整が容易に行なわれる。また。(Function) According to the present invention, level adjustment of each integrated circuit under test can be easily performed by controlling the voltage applied to the voltage-controlled variable capacitance element. Also.
位相変化は、人力信号をコンデンサの直列分割構成を通
じて高人力インピーダンス高周波増幅器に結合すること
により、微小範囲に留めることができ、実質的番、：も
無視することができる。The phase change can be kept to an infinitesimal range and virtually negligible by coupling the human power signal to a high human power impedance high frequency amplifier through a series division configuration of capacitors.
（実施例）
本発明の一実施例を第１図および第２図に基づいて説明
する。(Example) An example of the present invention will be described based on FIGS. 1 and 2.
第１図は本発明の被試験集積回路の動特性試験ブロック
回路図である。同図において、第３図と同一部分に関し
ては同一符号を付し、その説明を省略する。FIG. 1 is a block circuit diagram for dynamic characteristic testing of an integrated circuit under test according to the present invention. In this figure, the same parts as in FIG. 3 are designated by the same reference numerals, and the explanation thereof will be omitted.
第１図中の電子式アッテネータ１４と、その制御用可変
電圧電源１５とが、従来方法の第３図中の可変抵抗器５
にかわって用いられている。測定周波数を設定しくたと
えば、５Ｍ）ｔｚ）、入力端子７の入力電圧可変範囲を
設定し、その応用範囲内では、伝達位相特性に変化を起
さないように対策が施こされたものである。The electronic attenuator 14 in FIG. 1 and the variable voltage power supply 15 for its control are replaced by the variable resistor 5 in FIG. 3 in the conventional method.
It is used instead of. The measurement frequency is set (for example, 5M) tz), the input voltage variable range of the input terminal 7 is set, and measures are taken to prevent changes in the transfer phase characteristics within that application range. .
第２図は１本発明の電子式アッテネータの詳細図である
。第１図の正弦波信号発生器３からの測定信号は、第２
図の入力端子１６に印加され、固定コンデンサ１７とバ
リアプルキャパシタンス１８で直列分割さねて、高周波
増幅器１９を通して、第２図の出力端子２０に発生する
。第２図中の可変電圧電源１５を調整することにより、
バリアプルキャパシタンス１８の容量値が変化すること
で、出力端子２０の出力電圧を変化させることができる
。その実施例によると、コンデンサの直列分割比を変え
るだけで、複雑な能動回路（たとえば、トランジスタ回
路）を応用していないため、位相変化は極めて少なく実
用可能な手段となる。なお第２図において、２１は減衰
量外部制御端子、２２は高抵抗である。FIG. 2 is a detailed diagram of an electronic attenuator according to the present invention. The measurement signal from the sine wave signal generator 3 of FIG.
The signal is applied to the input terminal 16 in the figure, is divided in series by a fixed capacitor 17 and a barrier pull capacitance 18, and is generated at the output terminal 20 in FIG. 2 through the high frequency amplifier 19. By adjusting the variable voltage power supply 15 in FIG.
By changing the capacitance value of the barrier pull capacitance 18, the output voltage of the output terminal 20 can be changed. According to this embodiment, only the series division ratio of the capacitors is changed, and no complicated active circuit (for example, a transistor circuit) is applied, so that the phase change is extremely small and becomes a practical means. In FIG. 2, 21 is an attenuation external control terminal, and 22 is a high resistance.
（発明の効果）
本発明によれば、電子式アッテネータを用いることによ
り、アナログ加算、減算機能を有する半導体集積回路の
自動計測を容易に可能とする効果がある。(Effects of the Invention) According to the present invention, by using an electronic attenuator, automatic measurement of a semiconductor integrated circuit having analog addition and subtraction functions can be easily performed.
第１図は本発明の一実施例による被試験集積回路の動特
性試験ブロック回路図、第２図は同電子式アッテネータ
の詳細図、第３図は従来の被試験集積回路の動特性試験
ブロック回路図である。
１ ・・・被試験集積回路、 ２ ・・供給電源、３
・・・正弦波信号発生器、 ４ ・・・可変抵抗器。
５・・・位相調節器、 ６，７・・・入力端子、８ ・
・・加算出力端子、 ９ ・・・減算出力端子、ＩＯ・
・・加算回路、１１ ・・減算回路、１２．１３・・
・電子電圧計、１４・・・電子式アッテネータ、１５・
・・可変電圧電源、１６・・・入力端子、１７・・・固
定コンデンサ、１８・・・バリアプルキャパシタンス、
１９・・・高周波増幅器、２０・・出力端子、２１・・
・減衰量外部制御端子、２２・・・高抵抗。
特許出願人 松下電子工業株式会社
パべ
代理人 星 野 恒 司７．旨）
□１．：、、Ｊ−ノ
第２図
Ｉ４
トFIG. 1 is a circuit diagram of a dynamic characteristic test block of an integrated circuit under test according to an embodiment of the present invention, FIG. 2 is a detailed diagram of the same electronic attenuator, and FIG. 3 is a conventional dynamic characteristic test block of an integrated circuit under test. It is a circuit diagram. 1... Integrated circuit under test, 2... Power supply, 3
... Sine wave signal generator, 4 ... Variable resistor. 5... Phase adjuster, 6, 7... Input terminal, 8 ・
・・Addition output terminal, 9 ・・Subtraction output terminal, IO・
... Addition circuit, 11 ... Subtraction circuit, 12.13...
・Electronic voltmeter, 14...Electronic attenuator, 15・
...Variable voltage power supply, 16...Input terminal, 17...Fixed capacitor, 18...Barrier pull capacitance,
19... High frequency amplifier, 20... Output terminal, 21...
- Attenuation external control terminal, 22...high resistance. Patent applicant: Matsushita Electronics Co., Ltd. Pabe agent: Hisashi Hoshino 7. ) □1. ：、、J-ノFigure 2 I4
Claims (1)
端子に対して、電圧制御型可変容量素子と高入力インピ
ーダンスを有する高周波増幅器とを組合わせて構成され
た電子式アッテネータおよび位相調節器を介して、所定
の入力信号を結合することを特徴とする半導体集積回路
の試験方法。Through an electronic attenuator and phase adjuster configured by combining a voltage-controlled variable capacitance element and a high-frequency amplifier with high input impedance, the input terminal of a semiconductor integrated circuit having analog addition and subtraction functions is A method for testing a semiconductor integrated circuit, characterized by combining predetermined input signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60098097A JPS61256267A (en) | 1985-05-10 | 1985-05-10 | Method for testing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60098097A JPS61256267A (en) | 1985-05-10 | 1985-05-10 | Method for testing semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61256267A true JPS61256267A (en) | 1986-11-13 |
Family
ID=14210835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60098097A Pending JPS61256267A (en) | 1985-05-10 | 1985-05-10 | Method for testing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61256267A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115808611A (en) * | 2022-12-13 | 2023-03-17 | 深圳市耀星微电子有限公司 | Integrated circuit test system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132250B1 (en) * | 1970-10-05 | 1976-09-11 |
-
1985
- 1985-05-10 JP JP60098097A patent/JPS61256267A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132250B1 (en) * | 1970-10-05 | 1976-09-11 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115808611A (en) * | 2022-12-13 | 2023-03-17 | 深圳市耀星微电子有限公司 | Integrated circuit test system |
| CN115808611B (en) * | 2022-12-13 | 2023-11-17 | 深圳市耀星微电子有限公司 | Integrated circuit test system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5432475A (en) | Method of offset voltage trim for automatic gain controls | |
| JPS61226651A (en) | Control circuit for enthalpy response device | |
| JPH09138248A (en) | Device and method for measuring rf electric power | |
| US4608533A (en) | Automatic compensation circuit for use with analog multiplier | |
| US4370615A (en) | High speed temperature controlled electrometer | |
| JPS6362924B2 (en) | ||
| US5231360A (en) | Multi-range voltage amplifier having multiplying digital/analog converters and programmable filter using multiplying DAC in feedback loop | |
| US4794325A (en) | Calibrated power detector | |
| JPS61256267A (en) | Method for testing semiconductor integrated circuit | |
| US4207536A (en) | Dual-adjustment balance circuit for operational amplifiers | |
| US4029972A (en) | Ramping circuit | |
| US4858208A (en) | Apparatus and method for testing semiconductor devices | |
| US4855627A (en) | Filter circuit | |
| US4733173A (en) | Electronic component measurement apparatus | |
| GB2035577A (en) | Device for measuring a quantity which influences a field-effect transistor | |
| JP2002261632A (en) | Transmission device | |
| JPH0511585B2 (en) | ||
| US4644193A (en) | Analog circuit for simulating a digitally controlled rheostat | |
| Faber | Algorithmic trimming on active circuitry | |
| US4336499A (en) | Dynamic headroom test generator | |
| JPS6339122B2 (en) | ||
| Sugiyama et al. | Pulsewidth modulation DC potentiometer | |
| US4124827A (en) | Variable sinusoidal oscillator | |
| US2857531A (en) | Method of and apparatus for noise measurement or indication in an electric circuit | |
| SU784010A1 (en) | Programmable pulse shaper |