JPS61241976A - Manufacture of field effect transistor - Google Patents
Manufacture of field effect transistorInfo
- Publication number
- JPS61241976A JPS61241976A JP60083168A JP8316885A JPS61241976A JP S61241976 A JPS61241976 A JP S61241976A JP 60083168 A JP60083168 A JP 60083168A JP 8316885 A JP8316885 A JP 8316885A JP S61241976 A JPS61241976 A JP S61241976A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- tantalum
- tantalum layer
- gate
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 230000005669 field effect Effects 0.000 title description 5
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 25
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000007743 anodising Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 13
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 7
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 abstract description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- 229910001936 tantalum oxide Inorganic materials 0.000 abstract description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 3
- 239000007864 aqueous solution Substances 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 238000003754 machining Methods 0.000 abstract 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052711 selenium Inorganic materials 0.000 description 3
- 239000011669 selenium Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- AQCDIIAORKRFCD-UHFFFAOYSA-N cadmium selenide Chemical compound [Cd]=[Se] AQCDIIAORKRFCD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、マトリックス型表示素子等において、特性を
上げるために絵素毎に付加される薄膜型の電界効果トラ
ンジスター（以下ｒＦＥＴＪと称す）の製造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a thin-film field effect transistor (hereinafter referred to as rFETJ) that is added to each picture element in order to improve characteristics in a matrix display element, etc. It is related to.
従来の技術
液晶あるいは電場発光材料を用いて作られたマトリック
ス型表示素子において、光の透過率あるいは反射率ある
いは発光輝度と電圧との特性の非直線性をより顕著にし
、結果としてさらに表示容量を大きくするとか、ある場
合にはＦＥＴと同時に設けられた容量とあいまって、コ
ントラストを向上させた表示素子の開発は盛んである〔
例えば、テレビジョン学会誌Ｖｏ１．３８．Ｎｏ、４（
’ ８４））。Conventional technology In matrix type display elements made using liquid crystals or electroluminescent materials, non-linearity in the characteristics between light transmittance or reflectance or luminance and voltage is made more pronounced, and as a result, the display capacity is further increased. There is active development of display elements with improved contrast by increasing the size of the FET, or in some cases by adding a capacitor installed at the same time as the FET.
For example, Television Society Journal Vol. 1.38. No, 4 (
'84)).
これらのＦＥＴの製造方法、とりわけゲート絶縁層の形
成に関しては、窒化硅素をプラズマ化学蒸着法で形成す
るとか、酸化硅素を硅素（Ｓｉ）の熱酸化により形成す
るか、同じく酸化硅素を化学蒸着法で形成するか、酸化
タンタルをスパッター法で形成する等により得られる。Regarding the manufacturing method of these FETs, especially regarding the formation of the gate insulating layer, silicon nitride is formed by plasma chemical vapor deposition, silicon oxide is formed by thermal oxidation of silicon (Si), or silicon oxide is formed by chemical vapor deposition. or by forming tantalum oxide by a sputtering method.
発明が解決しようとする問題点
しかし、このようなＦＥＴの製法に従うならば、ゲート
絶縁層の不完全性による製造歩留りの低下、及びこれに
よる製造コストの上昇を招く傾向にある。また、ゲート
絶縁層の不完全性に関して、唯一の例外とみなされてい
るものは、前述の硅素（ＳＬ）の熱酸化膜である。しか
し、この方法では１０００℃近辺の高温の処理を要し、
従って、基板材料が高価な石英等に限定される等、総合
的に見て著しく不満足である。Problems to be Solved by the Invention However, if such an FET manufacturing method is followed, the manufacturing yield tends to decrease due to imperfections in the gate insulating layer, and the manufacturing cost tends to increase due to this. Furthermore, regarding the imperfection of the gate insulating layer, the only exception is the aforementioned thermal oxide film of silicon (SL). However, this method requires high temperature treatment of around 1000℃,
Therefore, the substrate material is limited to expensive quartz or the like, which is extremely unsatisfactory overall.
問題点を解決するための手段
上記問題点を解決するため、本発明の電界効果トランジ
スターの製造方法は、絶縁性基板上に所定の形状のタン
タル層を形成する第１の工程と、つぎに前記タンタル層
の上に絶縁層を形成してゲート絶縁層を得る第２の工程
と、つぎに前記タンタル層を陽極酸化処理する第３の工
程とを含む方法としたものである。Means for Solving the Problems In order to solve the above problems, the method for manufacturing a field effect transistor of the present invention includes a first step of forming a tantalum layer of a predetermined shape on an insulating substrate, and then The method includes a second step of forming an insulating layer on the tantalum layer to obtain a gate insulating layer, and a third step of anodizing the tantalum layer.
作用
上記方法によれば、ゲート漏洩電流を大幅に低減できる
。これは、陽極酸化処理の工程において。Effect: According to the above method, gate leakage current can be significantly reduced. This is done in the anodizing process.
絶縁層の不完全部分に接するタンタル層のみが酸化タン
タルに変換され、前記不完全部分が絶縁化するためであ
ると考えられる。This is thought to be because only the tantalum layer in contact with the imperfect portion of the insulating layer is converted into tantalum oxide, and the imperfect portion becomes insulated.
実施例 以下、本発明の一実施例を図面に基づいて説明する。Example Hereinafter, one embodiment of the present invention will be described based on the drawings.
図面は本発明の一実施例における電界効果トランジスタ
ーの製造方法により得られたＦＥＴの断面図で、１はガ
ラス等の絶縁性基板、２はタンタル層、３は窒化硅素や
酸化アルミニウム、酸化硅素、酸化タンタル等から形成
された絶縁層、４は多結晶硅素（Ｓｉ）、非晶質硅素、
セレン（Ｓｓ）、セレン化カドミウム（ＣｄＳｅ）等の
半導体からなる半導体層、５はソース電極及びドレイン
電極である。前記タンタル層２はゲート電極を構成して
おり、前記絶縁層３はゲート絶縁層を構成している。前
記絶縁層３の形成においては、窒化硅素はプラズマ化学
蒸着法で、酸化硅素は比較的低温での化学蒸着法で、酸
化アルミニウムや酸化タンタルはスパッター法で形成さ
れる。The drawing is a cross-sectional view of an FET obtained by the method for manufacturing a field effect transistor according to an embodiment of the present invention, in which 1 is an insulating substrate such as glass, 2 is a tantalum layer, 3 is silicon nitride, aluminum oxide, silicon oxide, An insulating layer made of tantalum oxide or the like; 4 is polycrystalline silicon (Si), amorphous silicon,
A semiconductor layer 5 is made of a semiconductor such as selenium (Ss) or cadmium selenide (CdSe), and 5 is a source electrode and a drain electrode. The tantalum layer 2 constitutes a gate electrode, and the insulating layer 3 constitutes a gate insulating layer. In forming the insulating layer 3, silicon nitride is formed by plasma chemical vapor deposition, silicon oxide is formed by chemical vapor deposition at a relatively low temperature, and aluminum oxide and tantalum oxide are formed by sputtering.
本発明の発明者らは、研究の結果、従来法によるＦＥＴ
に比較して１本発明に係るＦＥＴのゲート漏洩電流が格
段に小さいことを見い出した。これは、専ら、陽極酸化
処理をする第３の工程の効果である。これは、第３の工
程、すなわち陽極酸化処理において、絶縁層３の不完全
部分に接するタンタル層のみが酸化タンタルに変換され
、その不完全部分が絶縁化すると推察している。なお、
ここでいうゲート漏洩電流とは、しかるべき直流バイア
ス電圧のもとで、タンタル層２からなるゲート電極とソ
ース電極あるいはドレイン電極５との間に電流が発生す
ることであり、ＦＥＴの使用上、これが小さいことが望
ましい、前記陽極酸化処理は、望ましくは室温よりやや
高めに保持された適当な、たとえば燐酸水溶液中で、陽
極酸化すべきタンタル層を陽極とし、適当なタンタル板
を陰極として、 ２０Ｖ〜１００Ｖの直流電圧を印加し
て行う。As a result of research, the inventors of the present invention found that
It has been found that the gate leakage current of the FET according to the present invention is much smaller than that of the present invention. This is exclusively an effect of the third step of anodizing. This is because in the third step, that is, the anodic oxidation treatment, only the tantalum layer in contact with the incomplete portion of the insulating layer 3 is converted to tantalum oxide, and the incomplete portion is insulated. In addition,
The gate leakage current here refers to the generation of current between the gate electrode made of the tantalum layer 2 and the source or drain electrode 5 under an appropriate DC bias voltage. The anodic oxidation treatment, which is preferably small, is carried out in an appropriate, for example, phosphoric acid aqueous solution, which is preferably maintained at a temperature slightly higher than room temperature, with the tantalum layer to be anodized used as an anode and a suitable tantalum plate used as a cathode, at 20V. This is done by applying a DC voltage of ~100V.
以下、具体的実施例について説明する。まず、二酸化硅
素（ＳｉＯ□）を約５０００人被覆したガラス板上に、
タンタル（Ｔａ）層を厚みが約３０００人になるように
スパッター法で形成し、そのあと、フォトリソグラフィ
ー法及びフレオンプラズマによる乾式エツチング法でも
って、前記タンタル（Ｔａ）層を微細加工した。つぎに
、前記タンタル（Ｔａ）層の上に、窒化硅素層をプラズ
マ化学蒸着法で（サンプルＣ−２群、サンプルＡ−２群
）、二酸化硅素（Ｓｉｎ、 ）層は基板温度を４００℃
に保って化学蒸着法で（サンプルＣ−２群、サンプルＣ
−２群）、酸化アルミニウム層をスパッター法で（サン
プルＣ−を群、サンプルＣ−２群）、酸化タンタル層を
スパッター法で（サンプルＣ−２群、サンプルＣ−２群
）各々形成した。かくて絶縁層３が得られた。前記各層
の膜厚は約１５００人とした。つぎに、前記サンプルＡ
−１群、Ｂ−１群、Ｃ−１群、Ｄ−１群を５０℃に保た
れた０、３％の燐酸水溶液中に浸漬し、前記タンタル（
Ｔａ）層に、同じく浸漬された適当なタンタル（Ｔａ）
板に対して５０ｖの正の直流電圧を印加し、陽極酸化処
理を行った。一方、比較例として、前記サンプルＡ−２
群、Ｂ−２群、Ｃ−２群、Ｄ−２群については、この陽
極酸化処理を省略した。つぎに、半導体層４の材料とし
てセレン（Ｓｓ）を採用し、下地温度を５０℃に保ち、
抵抗加熱蒸着法で、厚み約３０００人のセレン（Ｓｓ）
層を形成した。つぎに、アルミニウム（Ａ１）を蒸着し
、フォトリソグラフィー法及び湿式エツチング法でもっ
て微細加工して、ソース電極およびドレイン電極５を得
た。タンタル層２からなるゲート電極とソース電極、及
びゲート電極とドレイン電極との重なりは、それぞれ５
μ■Ｘ５０μ■＝２５０平方μＩであった。かくして、
ＦＥＴが得られた。Specific examples will be described below. First, on a glass plate coated with about 5000 silicon dioxide (SiO□),
A tantalum (Ta) layer was formed to a thickness of about 3,000 mm by sputtering, and then finely processed by photolithography and dry etching using Freon plasma. Next, a silicon nitride layer was formed on the tantalum (Ta) layer by plasma chemical vapor deposition (sample C-2 group, sample A-2 group), and a silicon dioxide (Sin) layer was formed at a substrate temperature of 400°C.
(sample C-2 group, sample C
-2 group), an aluminum oxide layer was formed by sputtering (sample C- group, sample C-2 group), and a tantalum oxide layer was formed by sputtering (sample C-2 group, sample C-2 group). Insulating layer 3 was thus obtained. The thickness of each layer was approximately 1,500. Next, the sample A
-1 group, B-1 group, C-1 group, and D-1 group were immersed in a 0.3% phosphoric acid aqueous solution kept at 50°C.
A suitable tantalum (Ta) layer is also immersed in the Ta) layer.
A positive DC voltage of 50 V was applied to the plate to perform anodizing treatment. On the other hand, as a comparative example, the sample A-2
This anodizing treatment was omitted for Group B-2, Group C-2, and Group D-2. Next, selenium (Ss) was adopted as the material for the semiconductor layer 4, and the base temperature was kept at 50°C.
Selenium (Ss) with a thickness of approximately 3000 mm is produced using resistance heating vapor deposition method.
formed a layer. Next, aluminum (A1) was deposited and microfabricated using photolithography and wet etching to obtain source and drain electrodes 5. The overlap between the gate electrode and the source electrode made of the tantalum layer 2, and the overlap between the gate electrode and the drain electrode are 5, respectively.
μ■×50μ■=250 square μI. Thus,
An FET was obtained.
ＦＥＴ特性の測定の結果、各サンプルには相互コンダク
タンスにかなりの差が認められたが、大略良好な特性を
示した。下記表に各サンプルについてゲート漏洩電流の
平均的な値を示す、測定時。As a result of measuring FET characteristics, each sample showed a considerable difference in mutual conductance, but generally showed good characteristics. The table below shows the average value of gate leakage current for each sample during measurement.
印加された直流電圧は３０Ｖであった。下記表から、本
発明の優位性がよく理解される。The applied DC voltage was 30V. From the table below, the superiority of the present invention can be clearly understood.
発明の効果
以上Ｉ述べたごとく本発明によれば、陽極酸化処理によ
りゲート漏洩電流の小さいＦＥＴを得ることができ、こ
れによりＦＥＴの特性の向上は勿論、製造歩留りも向上
し、コストの低減にも資すること大である。Effects of the Invention As described above, according to the present invention, an FET with low gate leakage current can be obtained by anodizing treatment, which not only improves the characteristics of the FET but also improves the manufacturing yield and reduces costs. It is also a great contribution.
図面は本発明の一実施例における電界効果トランジスタ
ーの製造方法により得られたＦＥＴの断面図である。The drawing is a cross-sectional view of an FET obtained by a method for manufacturing a field effect transistor according to an embodiment of the present invention.
Claims (1)
第１の工程と、つぎに前記タンタル層の上に絶縁層を形
成してゲート絶縁層を得る第２の工程と、つぎに前記タ
ンタル層を陽極酸化処理する第３の工程とを含む電界効
果トランジスターの製造方法。1. A first step of forming a tantalum layer in a predetermined shape on an insulating substrate, then a second step of forming an insulating layer on the tantalum layer to obtain a gate insulating layer, and then and a third step of anodizing the tantalum layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60083168A JPS61241976A (en) | 1985-04-18 | 1985-04-18 | Manufacture of field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60083168A JPS61241976A (en) | 1985-04-18 | 1985-04-18 | Manufacture of field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61241976A true JPS61241976A (en) | 1986-10-28 |
Family
ID=13794737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60083168A Pending JPS61241976A (en) | 1985-04-18 | 1985-04-18 | Manufacture of field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61241976A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0653509A (en) * | 1991-05-11 | 1994-02-25 | Semiconductor Energy Lab Co Ltd | Insulated gate field effect semiconductor device and fabrication thereof |
| JPH06196500A (en) * | 1991-05-16 | 1994-07-15 | Semiconductor Energy Lab Co Ltd | Insulated gate field effect semiconductor device and manufacture thereof |
-
1985
- 1985-04-18 JP JP60083168A patent/JPS61241976A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0653509A (en) * | 1991-05-11 | 1994-02-25 | Semiconductor Energy Lab Co Ltd | Insulated gate field effect semiconductor device and fabrication thereof |
| JPH06196500A (en) * | 1991-05-16 | 1994-07-15 | Semiconductor Energy Lab Co Ltd | Insulated gate field effect semiconductor device and manufacture thereof |
| US6017783A (en) * | 1991-05-16 | 2000-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device using an insulated gate electrode as a mask |
| US6555843B1 (en) | 1991-05-16 | 2003-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4469568A (en) | Method for making thin-film transistors | |
| JP3054862B2 (en) | Gate insulating film including diamond-like carbon film, thin film transistor using the same, method of forming gate insulating film, and manufacturing method thereof | |
| JPH03161938A (en) | Manufacture of thin-film transistor | |
| KR970013427A (en) | Thin film transistor for liquid crystal display device and manufacturing method thereof | |
| JPH0311635A (en) | Manufacture of compound semiconductor device | |
| JPS61241976A (en) | Manufacture of field effect transistor | |
| JPS63308384A (en) | Thin film transistor | |
| JP2003258261A (en) | Organic tft and its manufacturing method | |
| JPS61241975A (en) | Manufacture of field effect transistor | |
| JPH03217059A (en) | Thin film transistor | |
| JPH0832083A (en) | Thin film transistor | |
| US3585071A (en) | Method of manufacturing a semiconductor device including a semiconductor material of the aiibvi type,and semiconductor device manufactured by this method | |
| JPS59149060A (en) | Manufacture of thin-film transistor | |
| JPH0689968A (en) | Capacitor and its manufacture | |
| JPH0530053B2 (en) | ||
| JPS62221159A (en) | Formation of thin film transistor matrix | |
| JPH0353787B2 (en) | ||
| JP2987789B2 (en) | Method of anodizing silicon and method of manufacturing thin film transistor using the method | |
| JPS5948961A (en) | Manufacture of semiconductor device | |
| WO1989009494A1 (en) | Gate dielectric for a thin film field effect transistor | |
| JPH0348670B2 (en) | ||
| JPH04299571A (en) | Thin film transistor | |
| JPH09232250A (en) | Manufacture of film | |
| JPH0336313B2 (en) | ||
| JPS5914673A (en) | Manufacture of thin film transistor |