JPS612350A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS612350A
JPS612350A JP59121846A JP12184684A JPS612350A JP S612350 A JPS612350 A JP S612350A JP 59121846 A JP59121846 A JP 59121846A JP 12184684 A JP12184684 A JP 12184684A JP S612350 A JPS612350 A JP S612350A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
solder
circuit chip
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59121846A
Other languages
Japanese (ja)
Inventor
Ryohei Sato
了平 佐藤
Muneo Oshima
大島　宗夫
Katsuhiro Arakawa
勝広 荒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59121846A priority Critical patent/JPS612350A/en
Publication of JPS612350A publication Critical patent/JPS612350A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To cool a semiconductor integrated circuit device directly by a refrigerant by mounting a plurality of semiconductor integrated circuit chips onto a substrate under the state in which the chips can be shielded from the refrigerant and fitting a cap for cooling with an inflow port and an outflow port for the refrigerant onto the substrate in an arrangement in which a mounting surface is covered. CONSTITUTION:Semiconductor integrated circuit chips 1 are face-down mounted onto a ceramic substrate 2 by solder 3, and the outer circumferences of the chips 1 are coated with solder 11 for sealing. Corrosion-resistant coating layers 12 are formed to the surfaces of the chips 1 and solder 11. Consequently, the face-down mounted chips 1 are covered with a cooling cap 13 with an inflow port 14 and an outflow port 15 for a refrigerant. According to the constitution, the chip 1 can be cooled directly by the refrigerant, and the chip 1 can be protected by solder 11 and the coating layer 12.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体集積回路に関するものであり、更に詳し
くは半導体集積回路チップから効率良く熱放散を行なう
様にした半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that efficiently dissipates heat from a semiconductor integrated circuit chip.

〔発明の背景〕[Background of the invention]

近年、半導体技術の急速な進歩に伴って、超ＬＳＩが製
作され、使用されている。この超ＬＳＩは論理回路で数
万個のゲート数を有する様になり、１０ワット以上の大
きな電力を消費している。このため、この種の半導体集
積回路装置は、チップ当りの発熱量が増大しており、高
密度実装の設計を行なう場合、熱設計が重要な問題にな
っている。2. Description of the Related Art In recent years, with rapid progress in semiconductor technology, VLSIs have been manufactured and used. This VLSI has a logic circuit with tens of thousands of gates, and consumes a large amount of power of 10 watts or more. For this reason, in this type of semiconductor integrated circuit device, the amount of heat generated per chip is increasing, and thermal design has become an important issue when designing for high-density packaging.

次に、従来の半導体集積回路装置における放熱手段につ
いて説明する。第１図に示す半導体装置は、多数の半導
体集積回路チップ１をハンダ３によりセラミック基板２
上にフェイスダウン実装したものである。一般に、この
種の半導体集積回路装置の放熱手段は、半導体集積回路
チップ１の裏面（第１図に示す半導体集積回路チップ１
の上側）からこの半導体集積回路チップ１の発熱量に応
じて、空気の自然対流やファンを用いた強制対流によっ
て放熱させるものである。しかし、発熱量が大きい場合
には、対応できない問題点がある。Next, heat dissipation means in a conventional semiconductor integrated circuit device will be explained. The semiconductor device shown in FIG.
This is a face-down implementation of the above. Generally, the heat dissipation means of this type of semiconductor integrated circuit device is provided on the back side of the semiconductor integrated circuit chip 1 (the back side of the semiconductor integrated circuit chip 1 shown in FIG.
According to the amount of heat generated by the semiconductor integrated circuit chip 1, heat is radiated from the upper side of the semiconductor integrated circuit chip 1 by natural convection of air or forced convection using a fan. However, if the amount of heat generated is large, there is a problem that cannot be addressed.

第２図は、半導体集積回路チップ１の発熱量が大きい場
合の冷却手段の一例を示す図であり、半導体集積回路チ
ップ１の裏面に冷却された金属棒４を押しあて、この金
属棒４によって冷却するものである。この冷却手段は、
冷却した金属棒４を用いるため、かなりの放熱効果が得
られる。しかし、半導体集積回路装置全体では、多数の
金属棒４とこれらを冷却するシステムが必要となり、冷
却システムが複雑で半導体集積回路装置全体が太き（な
り、高密度化でもないという問題点がある。FIG. 2 is a diagram showing an example of a cooling means when the amount of heat generated by the semiconductor integrated circuit chip 1 is large. It is for cooling. This cooling means
Since the cooled metal rod 4 is used, a considerable heat dissipation effect can be obtained. However, the entire semiconductor integrated circuit device requires a large number of metal rods 4 and a system to cool them, which poses the problem that the cooling system is complicated and the entire semiconductor integrated circuit device is thick (and not very dense). .

第３図は、第２図と同様に半導体集積回路チップ１の発
熱量が大きい場合の冷却手段の一例を示す図である。図
示する様に、半導体集積回路チップ１がＡｕ−３ｔ共晶
体（ろう剤）６で円筒状の放熱フィン９にグイボンディ
ングされており、更に放熱フィン９とセラミック基板２
が銀ろう７により接着されている。セラミック基板２は
、図示する様に半導体集積回路チップ１表面の電極にワ
イヤ１０を介して接続されたリード端子５をガラス８を
介して挟持している。この様な半導体集積回路チップ１
の放熱は、放熱フィン９を冷却することによって行なわ
れるが、第２図に関連して述べたのと同様に、放熱フィ
ン９の冷却システムが複雑で半導体集積回路装置全体が
大きくなり、高密度化できないという問題点がある。FIG. 3 is a diagram showing an example of a cooling means when the amount of heat generated by the semiconductor integrated circuit chip 1 is large, similar to FIG. 2. As shown in the figure, a semiconductor integrated circuit chip 1 is bonded to a cylindrical heat dissipation fin 9 using an Au-3t eutectic (brazing agent) 6, and the heat dissipation fin 9 and a ceramic substrate 2 are bonded together.
is bonded with silver solder 7. As shown in the figure, the ceramic substrate 2 holds lead terminals 5 connected to electrodes on the surface of the semiconductor integrated circuit chip 1 via wires 10 with a glass 8 interposed therebetween. Such a semiconductor integrated circuit chip 1
The heat dissipation is performed by cooling the heat dissipation fins 9, but as described in connection with FIG. The problem is that it cannot be converted into

以上に説明した様に、従来技術による半導体集積回路装
置は、超ＬＳＩの高密度実装を実現するのに重要な役割
を果たす冷却システムに問題点があり、高密度実装を効
果的に行なうことができなかった。As explained above, conventional semiconductor integrated circuit devices have problems with the cooling system, which plays an important role in realizing high-density packaging of VLSIs, making it difficult to effectively perform high-density packaging. could not.

〔発明の目的〕[Purpose of the invention]

本発明は、上記した従来の半導体集積回路装置の問題点
に鑑みなされたもので、半導体集積回路装置の高密度実
装を実現することが可能な様に、高い放熱効率が得られ
る放熱システムを有する半導体集積回路装置を提供する
ことを目的としている。The present invention has been made in view of the problems of the conventional semiconductor integrated circuit devices described above, and has a heat dissipation system that can obtain high heat dissipation efficiency so as to realize high-density packaging of semiconductor integrated circuit devices. The purpose is to provide a semiconductor integrated circuit device.

〔発明の概要〕[Summary of the invention]

本発明の半導体集積回路装置は、複数の半淳体集積回路
チップを冷媒からシールド可能な状態で基板上に実装し
、更に半導体集積回路チップ実装面を覆う配置で冷媒の
流入口と流出口を有する冷却用キャップが基板上に設け
られている。この様な構成をとることにより、半導体集
積回路チップを冷媒で直接冷却することが可能な半導体
集積回路装置が提供される。In the semiconductor integrated circuit device of the present invention, a plurality of semi-conductive integrated circuit chips are mounted on a substrate in a state in which they can be shielded from a coolant, and the coolant inlet and outlet are arranged to cover the semiconductor integrated circuit chip mounting surface. A cooling cap having a cooling cap is provided on the substrate. By adopting such a configuration, a semiconductor integrated circuit device is provided in which a semiconductor integrated circuit chip can be directly cooled with a refrigerant.

〔発明の実施例〕[Embodiments of the invention]

以下添付の図面に示す実施例により、更に詳細に本発明
について説明する。The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

第４図は、本発明の半導体集積回路装置の一実施例を示
す断面図である。図示する様に、半導体集積回路チップ
１はセラミック基板２上にハンダ３によってフェイスダ
ウン実装され、更に半瑯体集積回路チップ１の外周は封
止用ハンダ１１により被われている。第５図は、半導体
集積回路チップ１が封止用ハンダ１１で被われている状
態を示す斜視図である。そして、第４図に示す様に、半
導体集積回路チップ１と封止用ハンダ１１の表面には、
耐食性のコーティングＮ１２が設けられている。この様
にフェイスダウン実装された半導体集積回路チップ１は
、冷却媒体の流入口１４と流出口１５を有する冷却キャ
ップ１３によって覆われている。FIG. 4 is a sectional view showing an embodiment of the semiconductor integrated circuit device of the present invention. As shown in the figure, a semiconductor integrated circuit chip 1 is mounted face down on a ceramic substrate 2 with solder 3, and the outer periphery of the semi-circular integrated circuit chip 1 is covered with a sealing solder 11. FIG. 5 is a perspective view showing a state in which the semiconductor integrated circuit chip 1 is covered with sealing solder 11. As shown in FIG. 4, on the surfaces of the semiconductor integrated circuit chip 1 and the sealing solder 11,
A corrosion-resistant coating N12 is provided. The semiconductor integrated circuit chip 1 mounted face down in this manner is covered by a cooling cap 13 having an inlet 14 and an outlet 15 for cooling medium.

上記した封止用ハンダ１１は、第６図に示す様に、封止
用メタライズ１７を介して半導体集積回路チップ１に接
着され、かつ封止用端子１８を介してセラミック基板２
に接着されている。尚、ハンダ３は、半導体集積回路チ
ップ１の接続端子１６とセラミック基板２上の接続端子
１９間の電気伝導に寄与するが、封止用ハンダ１１は一
般にこの様な役割は有しておらず、導入された冷却媒体
が流入するのを防止する役割を有するのみである。As shown in FIG. 6, the above-mentioned sealing solder 11 is bonded to the semiconductor integrated circuit chip 1 via the sealing metallization 17, and is bonded to the ceramic substrate 1 via the sealing terminals 18.
is glued to. Note that the solder 3 contributes to electrical conduction between the connection terminals 16 of the semiconductor integrated circuit chip 1 and the connection terminals 19 on the ceramic substrate 2, but the sealing solder 11 generally does not have such a role. , only has the role of preventing the introduced cooling medium from flowing in.

以上に記載したこの実施例によれば、半導体集積回路チ
ップ１を流入口１４から流入される冷却媒体により直接
冷却することができ、しかも半導体集積回路チップ１は
封止用ハンダ１１と耐食性のコーティング１２によって
保護することができる。従って、半導体集積回路チップ
１の高密度実装と高効率冷却をを実現することが可能に
なる。According to this embodiment described above, the semiconductor integrated circuit chip 1 can be directly cooled by the cooling medium flowing in from the inlet 14, and the semiconductor integrated circuit chip 1 is coated with the sealing solder 11 and the corrosion-resistant coating. 12. Therefore, it becomes possible to realize high-density packaging and highly efficient cooling of the semiconductor integrated circuit chip 1.

次に、前記した実施例における封止用ハンダ１１及びコ
ーティング１２の形成方法について説明する。Next, a method of forming the sealing solder 11 and the coating 12 in the above embodiment will be explained.

第７図に示す様に、先ずＳｔの異方性エツチングを利用
してウェハ２０（後に、半導体集積回路チップ１を形成
する）に７字溝を形成し、その後真空蒸発法で金属を蒸
着し、フォトリソグラフィを用いて封止用メタライズ１
７を形成する。上記したＳｔの異方性エツチングには、
例えば苛性カリ溶液によるウェットエツチングを用いる
ことができる。As shown in FIG. 7, first, a 7-shaped groove is formed on the wafer 20 (later, the semiconductor integrated circuit chip 1 will be formed) using St anisotropic etching, and then metal is deposited by vacuum evaporation. , metallization for sealing using photolithography 1
form 7. For the above-mentioned anisotropic etching of St,
For example, wet etching using a caustic potash solution can be used.

又、上記した金属には、例えばＣｒ−ＣｕやＴｉ−Ｃｕ
等の金属を用い゛ることができる。このＶ字型をした封
止用メタライズ１７の形成と同時に接続端子１６を形成
する。接続用及び封止用ハンダはこれらの封止用メタラ
イズ１７及び接続端子１６上に蒸着あるいはメッキによ
り供給する。このハンダの供給後、７字溝をダイシング
により分割して、半導体集積回路チップ１を得る。Further, the above-mentioned metals include, for example, Cr-Cu and Ti-Cu.
Metals such as the following can be used. The connection terminals 16 are formed simultaneously with the formation of the V-shaped sealing metallization 17. Connecting and sealing solder is supplied onto the sealing metallization 17 and the connection terminals 16 by vapor deposition or plating. After supplying this solder, the 7-shaped groove is divided by dicing to obtain semiconductor integrated circuit chips 1.

次に、この様にして形成した半導体集積回路チップ１を
セラミック基板２に実装する。この実装方法は、半導体
集積回路チップ１をセラミック基板２に位置合わせした
後、真空中あるいはＡｒやＮ２等不活性ガス中でハンダ
を加熱溶融し、セラミック基板２へのハンダ接続を行な
い、これによって封止用ハンダ１１とハンダ３を同時に
形成する。Next, the semiconductor integrated circuit chip 1 thus formed is mounted on a ceramic substrate 2. In this mounting method, after aligning the semiconductor integrated circuit chip 1 to the ceramic substrate 2, the solder is heated and melted in a vacuum or in an inert gas such as Ar or N2, and the solder is connected to the ceramic substrate 2. Sealing solder 11 and solder 3 are formed at the same time.

この実装状態で、耐食性金属（例えば、Ｎ１−Ａｕ）や
有機材（例えば、ポリアミド〉等のコーテイング材を封
止用ハンダ１１や半導体集積回路チップ１の表面上にコ
ーティングし、コーティング層１２を形成する。この様
にして、多数の半導体集積回路チップ１をセラミック基
板２上に形成し、更に冷却用キャップ１３で全体を覆い
、冷却媒体を流す構造にする。In this mounted state, a coating material such as a corrosion-resistant metal (for example, N1-Au) or an organic material (for example, polyamide) is coated on the sealing solder 11 and the surface of the semiconductor integrated circuit chip 1 to form a coating layer 12. In this way, a large number of semiconductor integrated circuit chips 1 are formed on the ceramic substrate 2, and the entire structure is further covered with a cooling cap 13 to allow a cooling medium to flow therethrough.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかな様に、本発明によれば、半導体
集積回路チップを封止して保護した状態で、半導体集積
回路チップを直接冷却することができるため、高密度実
装を可能にした半導体集積回路装置を提供することがで
きる。従って、電子計算機における演算速度の向上を図
ったり、コストパーフォーマンスにすぐれた半導体集積
回路の実装を実現することができ、超高速・高密度計算
機システムに寄与すること大である。As is clear from the above description, according to the present invention, the semiconductor integrated circuit chip can be directly cooled while the semiconductor integrated circuit chip is sealed and protected. An integrated circuit device can be provided. Therefore, it is possible to improve the calculation speed of electronic computers, and to realize the implementation of semiconductor integrated circuits with excellent cost performance, which greatly contributes to ultra-high-speed, high-density computer systems.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図及び第３図は、従来の半導体集積回路
装置における冷却手段を示す断面図、第４図は本発明の
半導体集積回路の一実施例を示す断面図、第５図は第４
図に示す一実施例における半導体集積回路チップのセラ
ミック基板への取り付は状態を示す斜視図、第６図は第
４図に示す一実施例における半導体集積回路チ・ノブの
セラミ・ツク基板への取り付は状態を示す断面図、第７
図は第６図に示す封止用メタライズの形成方法を示すウ
ェハの断面図である。 １・・・半導体集積回路チップ、２・・・セラミ・ツク
基板、３・・・ハンダ、４・・・金属棒、５・・・リー
ド端子、９・・・放熱フィン、１１・・・封止用ハンダ
、１２・・・コーティング、１３・・・冷却用キャップ
、１４・・・流入口、１５・・・流出口、１６．１９・
・・接続端子、１７・・・封止用メタライズ、１８・・
・封止用端子。 代理人弁理士　秋　　本　　正　　実 第１図 第２図 第３図 第４図 第５図 第６図 第７図1, 2, and 3 are sectional views showing a cooling means in a conventional semiconductor integrated circuit device, FIG. 4 is a sectional view showing an embodiment of the semiconductor integrated circuit of the present invention, and FIG. 5 is a sectional view showing a cooling means in a conventional semiconductor integrated circuit device. Fourth
FIG. 6 is a perspective view showing how the semiconductor integrated circuit chip is attached to the ceramic substrate in the embodiment shown in FIG. The installation is shown in the sectional view showing the condition, No. 7
This figure is a cross-sectional view of a wafer showing a method of forming the sealing metallization shown in FIG. 6. DESCRIPTION OF SYMBOLS 1...Semiconductor integrated circuit chip, 2...Ceramic board, 3...Solder, 4...Metal rod, 5...Lead terminal, 9...Radiating fin, 11...Sealing Stopping solder, 12... Coating, 13... Cooling cap, 14... Inlet, 15... Outlet, 16.19.
...Connection terminal, 17...Metalization for sealing, 18...
・Sealing terminal. Representative Patent Attorney Tadashi Akimoto Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】 １、複数の半導体集積回路チップを冷媒からシールド可
能な状態で実装した基板と、冷媒の流入口と流出口を備
え、かつ上記基板上に半導体集積回路チップ実装面を覆
う配置で設けられた冷却用キャップとを備えてなる半導
体集積回路装置。 ２、前記基板は、半導体集積回路チップの周囲に形成さ
れた封止用メタライズと基板の半導体集積回路チップ実
装面外周に形成された封止用接続端子との間に、封止用
ハンダを介在させることにより、半導体集積回路チップ
を冷媒からシールド可能な状態で実装したことを特徴と
する特許請求の範囲第１項記載の半導体集積回路装置。 ３、前記半導体集積回路チップと前記封止用ハンダと基
板表面に耐食性コーティングを施すことを特徴とする特
許請求の範囲第２項記載の半導体集積回路装置。[Scope of Claims] 1. A substrate on which a plurality of semiconductor integrated circuit chips are mounted in a manner that can be shielded from a coolant, an inlet and an outlet for the coolant, and a surface on which the semiconductor integrated circuit chips are mounted is covered on the substrate. A semiconductor integrated circuit device comprising: a cooling cap provided in an arrangement; 2. The substrate has a sealing solder interposed between the sealing metallization formed around the semiconductor integrated circuit chip and the sealing connection terminal formed on the outer periphery of the semiconductor integrated circuit chip mounting surface of the substrate. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit chip is mounted in a state in which it can be shielded from a coolant. 3. The semiconductor integrated circuit device according to claim 2, wherein a corrosion-resistant coating is applied to the semiconductor integrated circuit chip, the sealing solder, and the surface of the substrate.
JP59121846A 1984-06-15 1984-06-15 Semiconductor integrated circuit device Pending JPS612350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59121846A JPS612350A (en) 1984-06-15 1984-06-15 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59121846A JPS612350A (en) 1984-06-15 1984-06-15 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS612350A true JPS612350A (en) 1986-01-08

Family

ID=14821380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59121846A Pending JPS612350A (en) 1984-06-15 1984-06-15 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS612350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1465252A1 (en) 2003-03-27 2004-10-06 STMicroelectronics, Inc. System and method for direct convective cooling of an exposed integrated circuit die surface
US7157793B2 (en) 2003-11-12 2007-01-02 U.S. Monolithics, L.L.C. Direct contact semiconductor cooling

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1465252A1 (en) 2003-03-27 2004-10-06 STMicroelectronics, Inc. System and method for direct convective cooling of an exposed integrated circuit die surface
US7157793B2 (en) 2003-11-12 2007-01-02 U.S. Monolithics, L.L.C. Direct contact semiconductor cooling

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