JPS61279157A - Cooling apparatus for semiconductor device - Google Patents
Cooling apparatus for semiconductor deviceInfo
- Publication number
- JPS61279157A JPS61279157A JP12049385A JP12049385A JPS61279157A JP S61279157 A JPS61279157 A JP S61279157A JP 12049385 A JP12049385 A JP 12049385A JP 12049385 A JP12049385 A JP 12049385A JP S61279157 A JPS61279157 A JP S61279157A
- Authority
- JP
- Japan
- Prior art keywords
- cooling
- bellows
- housing
- heat transfer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4332—Bellows
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体装置の冷却装置に係り、特に基板上に
多数配置された半導体チップの冷却に好適な冷却装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a cooling device for semiconductor devices, and particularly to a cooling device suitable for cooling a large number of semiconductor chips arranged on a substrate.
従来において、半導体技術の発達に伴い１個のチップ素
子から発生される熱量は増加をつづけ、強制空冷型の手
段等では半導体チップを充分に冷却することができず、
事実上はぼ冷却性能の限界に達している。このため、特
に高速データ処理装置等の半導体装置に関しては、例え
ば公開特許公報昭５９−１７７９９６や特許公報５６−
３１７４３に開示されているような液体を用いた冷却装
置が考案されている。第６図に、水冷構造の従来案を示
す。図において、ハウジング５５には冷却水を通すダク
ト５６が設けられ、半導体チップ２０上にはんだ付され
た中間熱伝達体５８とハウジング５５はベローズ５７に
よって接続され、中間熱伝達体５８が直接冷却水で冷却
されるとともに各半導体チップ２０にハウジングの歪が
伝わらない構造になっている。この従来案では、半導体
チップを中間熱伝達体を介して直接水冷しているため冷
却効率は非常に良く、１チップ当りの発熱量が５０Ｗ程
度でも充分半導体の動作温度範囲に冷却可能である。Conventionally, with the development of semiconductor technology, the amount of heat generated from a single chip element has continued to increase, and forced air cooling methods have not been able to sufficiently cool semiconductor chips.
In fact, the limit of cooling performance has been reached. For this reason, especially regarding semiconductor devices such as high-speed data processing devices, for example, Japanese Patent Publication No. 59-177996 and Japanese Patent Publication No. 56-56
A cooling device using a liquid has been devised as disclosed in US Pat. Figure 6 shows a conventional water cooling structure. In the figure, a housing 55 is provided with a duct 56 through which cooling water flows, and an intermediate heat transfer body 58 soldered on the semiconductor chip 20 and the housing 55 are connected by a bellows 57, so that the intermediate heat transfer body 58 is directly connected to the cooling water. The structure is such that the housing is cooled and the strain of the housing is not transmitted to each semiconductor chip 20. In this conventional method, since the semiconductor chip is directly cooled with water via an intermediate heat transfer body, the cooling efficiency is very good, and even if the heat generation amount per chip is about 50 W, it is possible to sufficiently cool the semiconductor chip to the operating temperature range of the semiconductor.
また、半導体チップに外力が加わらないため、半導体チ
ップと基板のはんだ接続部の寿命が伸び、この点での信
頼性は増す。しかし、ベローズ自体は肉厚が非常に薄い
こと、ハウジングとベローズ及びベローズと中間熱伝達
体は異種の材料が接する接合構造をとること等のために
、腐食によって水冷構造体に穴の開く可能性が高く、も
し水もれが発生した場合は、漏洩電流や絶縁破壊等によ
る半導体チップの破損のため半導体装置が故障するとい
う問題がある。Furthermore, since no external force is applied to the semiconductor chip, the life of the solder connection between the semiconductor chip and the substrate is extended, and reliability in this respect is increased. However, because the bellows itself has a very thin wall thickness, and because the housing and bellows and the bellows and the intermediate heat transfer body have a joint structure in which dissimilar materials are in contact, there is a possibility that holes will form in the water cooling structure due to corrosion. If water leakage occurs, there is a problem that the semiconductor device may malfunction due to damage to the semiconductor chip due to leakage current or dielectric breakdown.
次に、第７図にパーフロロカーボンやフロリナート等の
誘電性冷媒を用いた浸漬沸騰冷却の従来案を示す。図に
おいて、セラミック製の多層配線基板６４上に多数はん
だ接続された半導体チップ２ｏ全体を、水冷孔５６と冷
却フィン６１を設けたハウジング５５で気密封止し、そ
の気密空間に半導体チップ２０が完全に浸漬されかつ上
部に空間ができる程度の量の誘電性冷媒６２を封止して
いる。この従来案では、冷却体となるハウジングの構造
が簡単で容易に製造できるという利点があるが、誘電性
冷媒が直接半導体チップや基板に接触しているため、以
下の問題がある。すなわち１一つは、誘電性冷媒が完全
には安定でなく、わずかな水分によってパーフロロカー
ボンやフロリナートからＨＦやＨＣｆｌの分解物質を生
成し、これが配線やＬＳＩチップそのものを腐食してし
まうこと、他の１つは、誘電性冷媒が有機基板に膨潤し
変形を起すため多層配線基板にセラミック基板に比べ性
能の高い有機基板を用いることができないという問題が
ある。Next, FIG. 7 shows a conventional method of immersion boiling cooling using a dielectric refrigerant such as perfluorocarbon or fluorinert. In the figure, the entire semiconductor chip 2o, which is soldered in large numbers on a ceramic multilayer wiring board 64, is hermetically sealed with a housing 55 provided with water cooling holes 56 and cooling fins 61, and the semiconductor chip 20 is completely placed in the airtight space. The dielectric refrigerant 62 is sealed in an amount sufficient to leave a space above the dielectric refrigerant 62. This conventional method has the advantage that the structure of the housing serving as the cooling body is simple and can be manufactured easily, but since the dielectric coolant is in direct contact with the semiconductor chip or substrate, there are the following problems. First, the dielectric refrigerant is not completely stable, and a small amount of moisture will generate decomposed substances such as HF and HCfl from perfluorocarbon and fluorinate, which will corrode the wiring and the LSI chip itself. One of the problems is that the dielectric coolant swells and deforms the organic substrate, making it impossible to use an organic substrate with higher performance than a ceramic substrate for the multilayer wiring board.
本発明の目的は、多層配線基板上に裸の半導体チップを
複数個フェイスダウンして搭載したマルチチップ半導体
モジュールに対して、半導体チップに外力が加わらずか
つ冷却性能が最も高い直接液体冷却が可能な構造をとり
、しかも冷却構造体の腐食等による冷媒もれの元配がな
く長期に渡る優れた信頼性を有する冷却装置を提供する
ことにある。The purpose of the present invention is to enable direct liquid cooling, which does not apply external force to the semiconductor chips and has the highest cooling performance, for multichip semiconductor modules in which multiple bare semiconductor chips are mounted face down on a multilayer wiring board. It is an object of the present invention to provide a cooling device which has an excellent structure and has excellent reliability over a long period of time without causing refrigerant leakage due to corrosion of a cooling structure or the like.
本発明は、直接水冷却構造体の欠点であるベローズや継
手部の水による腐食損傷を防止するため、冷却媒体を２
種類使用し、特に腐食が問題となる半導体チップ近傍の
冷却部の冷媒にパーフロロカーボンやフロリナートなど
腐食性が小さくかつ冷却効率の高い低沸点冷媒を用い、
腐食による水もれ等の可能性が小さい部分には冷却効率
の高い水を冷媒として用いる複合冷却方式とした点に基
本的な特徴がある。以下、本方式を具体化した冷却構造
の特徴について述べる。In order to prevent water-induced corrosion damage to bellows and joints, which is a disadvantage of direct water cooling structures, the present invention uses two cooling mediums.
We use low-boiling point refrigerants that are less corrosive and have high cooling efficiency, such as perfluorocarbon and fluorinate, as refrigerants in cooling parts near semiconductor chips where corrosion is a problem.
The basic feature is that a composite cooling system is used that uses water, which has high cooling efficiency, as a refrigerant in areas where the possibility of water leakage due to corrosion is small. The features of the cooling structure that embodies this method will be described below.
本発明による冷却構造の特徴は、第１に、水冷通路を設
けたハウジングと半導体チップ上に接合された中間熱伝
達体を柔軟性の高いベローズで接続し、ベローズ内部に
低融点の誘電性冷媒を封入した点にある。ベローズでハ
ウジングと中間熱伝達体を接続したことにより、基板と
ハウジングの熱膨張差による歪や、基板のそ、りあるい
は半導体チップの基板へのはんだ付のばらつきによる高
さく６）
や傾きのばらつきをベローズ部で吸収できるため、半導
体チップに加わる外力を小さくでき、半導体チップと基
板のはんだ付部の寿命を大幅に向上できる。また、肉厚
が薄く継手部が存在するベローズ内に腐食作用の非常に
小さい低沸点の誘電性冷媒を封入したことにより、中間
熱伝達体からハウジングまでの熱伝達率を大幅に向上す
ることができかつ冷却構造体から冷媒が半導体モジュー
ル上にもれ出す可能性がほとんどなくなるため、半導体
装置としての信頼性を大幅に向上することができる。The cooling structure according to the present invention has the following features: Firstly, a housing provided with a water cooling passage and an intermediate heat transfer body bonded on a semiconductor chip are connected by a highly flexible bellows, and a low melting point dielectric coolant is inside the bellows. The point is that it has been enclosed. By connecting the housing and the intermediate heat transfer body with bellows, there is distortion due to the difference in thermal expansion between the board and housing, and variations in height6) and tilt due to variations in board warpage or soldering of semiconductor chips to the board. Since this can be absorbed by the bellows part, the external force applied to the semiconductor chip can be reduced, and the life of the soldered part between the semiconductor chip and the board can be greatly improved. In addition, by sealing a low-boiling dielectric refrigerant with very little corrosive action into the bellows, which has a thin wall and joints, it is possible to significantly improve the heat transfer coefficient from the intermediate heat transfer body to the housing. Moreover, since there is almost no possibility that the coolant leaks from the cooling structure onto the semiconductor module, the reliability of the semiconductor device can be greatly improved.
本発明による冷却構造の第２の特徴は、低沸点の誘電性
冷媒を封入する各ベローズ内空間が上部でつながった構
造とし、ハウジング外部に上記空間とつながったベロー
ズを設けた点にある。このことにより、半導体チップ上
のベローズ内圧をハウジング外部に設けたベローズによ
って一定に調節できるため、半導体チップと基板とのは
んだ付部の寿命をさらに向上することができる。A second feature of the cooling structure according to the present invention is that the internal spaces of each bellows, which enclose a low boiling point dielectric refrigerant, are connected at the upper part, and the bellows that are connected to the spaces are provided outside the housing. As a result, the internal pressure of the bellows on the semiconductor chip can be adjusted to a constant level by the bellows provided outside the housing, so that the life of the soldered portion between the semiconductor chip and the board can be further improved.
本発明による冷却構造の第３の特徴は、中間熱伝達体に
沸騰伝熱面を有する熱伝導性のよい搭を直接接合し、水
冷通路と気化した誘電性冷媒の凝縮面の間を熱伝導性の
よい材料で構成した点にある。このことにより、中間熱
伝達体から冷却水までの熱伝達率を向」二できるため、
冷却装置としての冷却効率を大幅に向上できる。The third feature of the cooling structure according to the present invention is that a highly thermally conductive tower having a boiling heat transfer surface is directly connected to the intermediate heat transfer body, and heat is conducted between the water cooling passage and the condensation surface of the vaporized dielectric refrigerant. The reason is that it is made of durable materials. This makes it possible to improve the heat transfer coefficient from the intermediate heat transfer body to the cooling water.
The cooling efficiency of the cooling device can be greatly improved.
以下本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は、本発明による冷却装置の一実施例で１個の半
導体チップに対応する部分の断面構造を示す。図におい
て、ハウジング１には冷却水を流す通路１３が設けられ
ており、沸騰冷却空間１２に接する冷媒の凝縮面は表面
積を増して熱伝達効率を増すためにフィン２が設けられ
ている。沸騰冷却空間１２を形成する底板４は端部でハ
ウジング１と一体になるよう接合されており、その底部
４には半導体チップの配置に対応してベローズ５と中間
熱伝達体１−１から成る冷却分岐体］４が接合されてい
る。中間熱伝達体１１は、半導体チップが接合される側
に電気絶縁性でしかも熱伝達性の良いセラミック板８が
接合用合金７で接合されており、セラミック板８上には
、はんだ付するためのメタライズ層９が形成されている
。熱伝導性の良い金属でつくられた容器６内には、表面
積が大きく熱伝導性のよい材質でつくられた沸騰伝熱面
を有する搭１０が容器６の底部に接合されて設けられて
いる。そして、沸騰冷却空間１２内には、液面が底板４
の上にくるような量のフロリナートやパーフロロカーボ
ン等の誘電性冷媒３が封入されている。また第２図は、
第１図で示した冷却装置を半導体モジュールに実装した
適用例を示す。FIG. 1 shows a cross-sectional structure of a portion corresponding to one semiconductor chip in an embodiment of a cooling device according to the present invention. In the figure, a housing 1 is provided with a passage 13 through which cooling water flows, and a refrigerant condensing surface in contact with a boiling cooling space 12 is provided with fins 2 to increase the surface area and heat transfer efficiency. A bottom plate 4 forming a boiling cooling space 12 is integrally joined to the housing 1 at its end, and the bottom plate 4 is provided with a bellows 5 and an intermediate heat transfer body 1-1 corresponding to the arrangement of semiconductor chips. cooling branch] 4 are joined. In the intermediate heat transfer body 11, a ceramic plate 8 which is electrically insulating and has good heat conductivity is bonded to the side to which the semiconductor chip is bonded using a bonding alloy 7, and on the ceramic plate 8 there is a plate for soldering. A metallized layer 9 is formed. Inside the container 6 made of a metal with good thermal conductivity, a tower 10 having a large surface area and a boiling heat transfer surface made of a material with good thermal conductivity is attached to the bottom of the container 6. . In the boiling cooling space 12, the liquid level is at the bottom plate 4.
A dielectric refrigerant 3 such as Fluorinert or perfluorocarbon is sealed in an amount equal to the amount above the refrigerant. Also, Figure 2 shows
An application example in which the cooling device shown in FIG. 1 is mounted on a semiconductor module is shown.
図において、半導体チップ２０は、チップ上に形成され
た電極パッド２６と基板２４上の配線パッド２２間をは
んだ２］によって接合されている。In the figure, a semiconductor chip 20 is bonded between electrode pads 26 formed on the chip and wiring pads 22 on a substrate 24 with solder 2].
また、半導体チップ２０と冷却構造体の中間熱伝達体１
１とはメタライズ層９，１９を介して低融点はんだ１８
により接合されている。Further, the intermediate heat transfer body 1 between the semiconductor chip 20 and the cooling structure
1 means low melting point solder 18 via metallized layers 9 and 19.
It is joined by
本実施例によれば、水による電気的腐食や隙間腐食の可
能性が高い接合部１５，１６．１７やベローズ５には腐
食性の小さい誘電性冷媒しか接触しないため、それらの
部分から腐食等により冷媒が漏れる可能性が非常に小さ
くなり、半導体モジュールとしての信頼性が向上する。According to this embodiment, since only the dielectric refrigerant with low corrosiveness comes into contact with the joints 15, 16, 17 and the bellows 5, which are likely to suffer from electrical corrosion or crevice corrosion due to water, corrosion can occur from these parts. This greatly reduces the possibility of refrigerant leakage, improving the reliability of the semiconductor module.
また、また熱伝導性の良い材質で中間熱伝達体を構成し
、かつ効率の良い沸騰伝熱面や凝縮面を設けているので
、冷却効率を高くすることができる。Furthermore, since the intermediate heat transfer body is made of a material with good thermal conductivity and is provided with an efficient boiling heat transfer surface and a condensation surface, cooling efficiency can be increased.
第３図は、本発明による冷却装置の他の実施例を半導体
モジュールに適用した状態で示す。図の冷却装置におい
て、ハウジング２６と底抜３０は熱膨張率がセラミック
の配線基板４２に近いコバール材を用いている。また中
間熱伝達体は、コバールの容器３３とベリリアを焼結助
剤に用いた高熱伝導率を有するＳｉＣセ）ミンク（ヒタ
セラム５ＣＩＯＩ）の絶縁板３４から構成されている。FIG. 3 shows another embodiment of the cooling device according to the present invention applied to a semiconductor module. In the illustrated cooling device, the housing 26 and the bottom hole 30 are made of Kovar material, which has a coefficient of thermal expansion close to that of the ceramic wiring board 42. The intermediate heat transfer body is composed of a container 33 made of Kovar and an insulating plate 34 made of SiC mink (Hitaceram 5CIOI), which has high thermal conductivity and uses beryllia as a sintering aid.
また、微細な冷却水路２７を設けた熱交換体２８は、フ
ォトエツチング等により溝加工を施した銅の薄板を、そ
の表面に形成した低融点合金薄膜により多数枚積層接合
することによってつくられている。構造としてハウジン
グ２６の外部には、沸騰冷却空間４５と通じる伸縮容量
の大きいベローズ４４を設けている。ハウジング２６の
内部の沸騰冷却空間４５内には、微細な冷却水路２７と
凝縮表面積を広げたフィン構造により熱交換効率を高め
た熱交換体２８を設けている。沸騰冷却空間４５を形成
する底部３０は、端部がハウジング２６と一体に接合さ
れており、また、半導体チップ３７に対応する位置に設
けられた開口部には、内部が空洞で一端が閉じ一端が開
放となっている冷却分岐体４６が接合され、気密空間が
形成されている。冷却分岐体４６は、柔軟性のあるベロ
ーズ３１と冷却ブロック５０及び沸騰伝熱面積を広げた
構造の塔３２から構成されている。気密空間内には、低
沸点で腐食作用の小さいＦＣ系の誘電性冷媒２９を封入
している。半導体チップ３７は配線基板４２上の配線パ
ッド４０に電極パッド３８を位置合せしてはんだ接続さ
れている。半導体チップ３７と中間熱伝達体５０は、メ
タライズ層３５を介して低融点はんだ３６により金属的
に接続されている。また、ハウジング２６は配線基板４
２上のメタライズ膜４１に、低融点はんだ３６を用いて
気密封止されている。その封止空間５１内には、Ｈｅガ
スが充填されている。The heat exchanger 28 provided with the fine cooling channels 27 is made by laminating and bonding a large number of thin copper plates that have been grooved by photoetching or the like with a thin film of a low-melting alloy formed on the surface. There is. As a structure, a bellows 44 having a large expansion and contraction capacity and communicating with the boiling cooling space 45 is provided on the outside of the housing 26. In the boiling cooling space 45 inside the housing 26, a heat exchange body 28 is provided which has improved heat exchange efficiency by means of fine cooling channels 27 and a fin structure with a widened condensing surface area. The bottom part 30 forming the boiling cooling space 45 has an end integrally joined to the housing 26, and an opening provided at a position corresponding to the semiconductor chip 37 has a hollow interior and a closed end. The cooling branch body 46, which is open, is joined to form an airtight space. The cooling branch body 46 is composed of a flexible bellows 31, a cooling block 50, and a tower 32 having a structure with an expanded boiling heat transfer area. The airtight space is filled with an FC-based dielectric refrigerant 29 that has a low boiling point and little corrosive action. The semiconductor chip 37 is connected to the wiring pads 40 on the wiring board 42 by aligning the electrode pads 38 with solder. The semiconductor chip 37 and the intermediate heat transfer body 50 are metallically connected by a low melting point solder 36 via a metallized layer 35. Further, the housing 26 is connected to the wiring board 4
The metallized film 41 on the metallized film 2 is hermetically sealed using a low melting point solder 36. The sealed space 51 is filled with He gas.
本実施例によれば、第１図及び第２図の実施例と同様に
、接合部４７，４８，４．９や薄肉のベローズ３１が腐
食して封止空間５１内に冷媒が洩れ出すことがなくなり
、半導体チップや配線を冷媒によって損傷する故障がな
くなる。また、中間熱伝達体及び熱交換体を熱伝導性の
よい材料で構成したこと、沸騰伝熱面と凝縮面及び水冷
部での熱伝達効率を表面積の増加によって高めたこと、
等により冷却性能を高くでき、数十Ｗ級の大集積・大電
力ＬＳＩを用いた半導体モジュールをＬＳＩの動作可能
な温度範囲内に冷却することができる。According to this embodiment, as in the embodiments shown in FIGS. 1 and 2, the joints 47, 48, 4.9 and the thin bellows 31 corrode and the refrigerant does not leak into the sealed space 51. This eliminates malfunctions where semiconductor chips and wiring are damaged by refrigerant. In addition, the intermediate heat transfer body and the heat exchange body are made of materials with good thermal conductivity, and the heat transfer efficiency at the boiling heat transfer surface, condensation surface, and water cooling section is increased by increasing the surface area.
As a result, cooling performance can be improved, and a semiconductor module using a large-scale integration and high-power LSI of several tens of watts can be cooled to within the operating temperature range of the LSI.
さらに、ハウジングと配線基板の熱膨張差を小さくして
いること、冷却分岐体に柔軟性のあるベローズを用いて
いること、沸騰冷却空間内の圧力が変動しないようにハ
ウジングの外部に大容量のベローズを用いていること等
の効果によって、半導体チップに加わる外力を小さくで
きるため、配線基板とのはんだ接続部の疲労寿命を大幅
に向−４ニすることができる。これらの結果、半導体装
置として長期に渡る信頼性を確保することが可能となる
。Furthermore, the difference in thermal expansion between the housing and the wiring board is minimized, flexible bellows are used for the cooling branch, and a large capacity is installed outside the housing to prevent pressure fluctuations in the boiling cooling space. As a result of the use of bellows, etc., the external force applied to the semiconductor chip can be reduced, so that the fatigue life of the solder connection with the wiring board can be significantly increased by -4. As a result, it becomes possible to ensure long-term reliability as a semiconductor device.
第４図は、本発明による冷却装置の他の実施例を示す断
面図である。図において、配線基板２４上に実装した半
導体チップ２０上に、沸騰冷却空間１２を個別に有する
ベローズ５と高熱伝導・電気絶縁性のセラミック８から
構成された冷却分岐体１４が、セラミック８の部分でメ
タライズ膜９゜１９を介してはんだ接続されている。ま
た、冷却分岐体１４を構成するベローズ５の上端は、内
部に水冷通路１３を有するハウジング１に気密に接合さ
れている。沸騰冷却空間１２への低沸点の誘電性冷媒３
の封入は、すべての組立てが終った後で封入口５２より
行い、最後にそこを低融点はんだ５３で封止している。FIG. 4 is a sectional view showing another embodiment of the cooling device according to the present invention. In the figure, on a semiconductor chip 20 mounted on a wiring board 24, a cooling branch body 14 composed of a bellows 5 having an individual boiling cooling space 12 and a highly thermally conductive/electrically insulating ceramic 8 is placed on a semiconductor chip 20 mounted on a wiring board 24. They are connected by solder through the metallized film 9°19. Further, the upper end of the bellows 5 constituting the cooling branch body 14 is hermetically joined to the housing 1 having a water cooling passage 13 therein. Low boiling point dielectric refrigerant 3 to boiling cooling space 12
After all the assemblies are completed, the encapsulation is performed through the encapsulation port 52, and finally the encapsulation is sealed with a low melting point solder 53.
本実施例によれば、半導体チップを封止している気密空
間内に設けた冷却体に、冷媒として腐食性の小さい誘電
性冷媒を用いているため、冷却体り腐食損傷による気密
空間内への液洩れの心配がなく、このため、半導体チッ
プや配線の冷媒による損傷がなくなり半導体モジュール
の信頼性が増す。また、配線基板に誘電率の低い高性能
有機基板を用いることも可能となる。According to this embodiment, since a dielectric refrigerant with low corrosiveness is used as a refrigerant in the cooling body provided in the airtight space that seals the semiconductor chip, the cooling body may be damaged by corrosion inside the airtight space. There is no need to worry about liquid leakage, which eliminates damage to semiconductor chips and wiring caused by refrigerant, increasing the reliability of the semiconductor module. Furthermore, it is also possible to use a high-performance organic substrate with a low dielectric constant for the wiring board.
第５図は、本発明による冷却装置の他の実施例を示す断
面図である。第４図に比較して、本実施例では、各冷却
分岐体１４の沸騰冷却空間１２を上部で共通にし、水冷
したハウジング］、と接する沸騰冷媒の凝縮面を広くし
ている。FIG. 5 is a sectional view showing another embodiment of the cooling device according to the present invention. Compared to FIG. 4, in this embodiment, the boiling cooling space 12 of each cooling branch body 14 is shared at the top, and the condensing surface of the boiling refrigerant in contact with the water-cooled housing is widened.
本実施例によれば、第４図の実施例と同様に、半導体モ
ジュールの信頼性を向上できる。According to this embodiment, the reliability of the semiconductor module can be improved as in the embodiment shown in FIG.
以上詳述したように、本発明によれば、多層配線基板上
に裸の半導体チップを複数個フェイスダウンして搭載し
たマルチチップ半導体モジュールに対して、半導体チッ
プに外力が加わらずかつ冷却性能が最も高い直接液体冷
却が可能な構造でしかも冷却構造体に腐食による損傷の
起らない信頼性の高い冷却装置を提供できるため、半導
体装置の長期に渡る信頼性を確保することができる。As detailed above, according to the present invention, for a multi-chip semiconductor module in which a plurality of bare semiconductor chips are mounted face down on a multilayer wiring board, no external force is applied to the semiconductor chips and the cooling performance is improved. Since it is possible to provide a highly reliable cooling device that has a structure that allows the highest level of direct liquid cooling and that does not cause damage to the cooling structure due to corrosion, it is possible to ensure the long-term reliability of semiconductor devices.
第１図は本発明しこよる冷却装置の１個の半導体チップ
に対応する部分の断面構造図、第２図は第１図の冷却装
置を半導体モジュールに適用した実施例を示す図、第３
図、第４図、第５図は本発明による冷却装置の他の実施
例を示す図、第６図は従来の直接水冷構造図、第７図は
従来の浸漬沸騰冷却構造図である。
１・・・ハウジング、２・・・フィン、３・・・誘電性
冷媒、４・・・底板、５・・・ベローズ、６・・・容器
、７・・・接合用合金、８・・・セラミック板、９・・
・メタライズ層、１６．１７・・・接合部、１８・・・
低融点はんだ、］９・・・メタライズ層、２０・・・半
導体チップ、２１・・・はんだ、２２・・・配線パッド
、２３・・・メタライズ層、２４・・・配線基板、２５
・・・ピン、２６・・・電極パッド、２７・・・水冷孔
、２８・・・熱交換体、２９・・・誘電性冷媒、３０・
・・底板、３１・・・ベローズ、３２・・・塔、３３・
・・容器、３・４・・・セラミック板、３５・・・メタ
ライズ、３６・・・低融点はんだ、３７・・・半導体チ
ップ、３８・・・電極パッド、３９・・・はんだ、４０
・・・配線パッド、４１・・・メタライズ層、４２・・
・配線基板、４３・・・ピン、４４・・・ベローズ、４
５・・・沸騰冷却空間、４６・・・冷却分岐体、４７，
４．８．４９・・・接合部、５０・・・中間熱伝達体、
５１・・・気密空間、５２・・・封止口、５３・・・低
融点はんだ、５５・・・ハウジング、５６・・・水冷孔
、５７・・・ベローズ、５８・・・中間熱伝達体、５９
・・・流入口、６ｏ・・・流出口、６１・・・フィン、
６２・・・誘電性冷媒、６３・・・沸騰冷却空間、６４
・・・セラミック配線基板。FIG. 1 is a cross-sectional structural diagram of a portion of a cooling device according to the present invention corresponding to one semiconductor chip, FIG. 2 is a diagram showing an embodiment in which the cooling device of FIG. 1 is applied to a semiconductor module, and FIG.
4 and 5 are views showing other embodiments of the cooling device according to the present invention, FIG. 6 is a diagram of a conventional direct water cooling structure, and FIG. 7 is a diagram of a conventional immersion boiling cooling structure. DESCRIPTION OF SYMBOLS 1... Housing, 2... Fin, 3... Dielectric refrigerant, 4... Bottom plate, 5... Bellows, 6... Container, 7... Joining alloy, 8... Ceramic plate, 9...
・Metallized layer, 16.17...Joint part, 18...
Low melting point solder,]9...Metallized layer, 20...Semiconductor chip, 21...Solder, 22...Wiring pad, 23...Metallized layer, 24...Wiring board, 25
... pin, 26 ... electrode pad, 27 ... water cooling hole, 28 ... heat exchanger, 29 ... dielectric refrigerant, 30.
...Bottom plate, 31...Bellows, 32...Tower, 33.
... Container, 3.4... Ceramic plate, 35... Metallization, 36... Low melting point solder, 37... Semiconductor chip, 38... Electrode pad, 39... Solder, 40
...Wiring pad, 41...Metallization layer, 42...
・Wiring board, 43...pin, 44...bellows, 4
5... Boiling cooling space, 46... Cooling branch body, 47,
4.8.49...Joint part, 50...Intermediate heat transfer body,
51... Airtight space, 52... Sealing port, 53... Low melting point solder, 55... Housing, 56... Water cooling hole, 57... Bellows, 58... Intermediate heat transfer body , 59
...Inlet, 6o...Outlet, 61...Fin,
62... Dielectric refrigerant, 63... Boiling cooling space, 64
...Ceramic wiring board.
Claims (1)
ダウンして搭載し、その多層配線基板をハウジングで封
止して用いる半導体装置において、前記ハウジングに水
冷通路を設け、半導体チップの背面に電気絶縁性でかつ
熱伝導の良好なセラミックと熱伝導の良好な金属とより
構成された中間熱伝達体を接合し、その中間熱伝達体と
前記ハウジングとを柔軟性の高いベローズで結合し、ベ
ローズの内部に低沸点の冷却媒体を封入したことを特徴
とする半導体装置の冷却装置。 ２、特許請求の範囲第１項において、水冷通路を設けた
ハウジングに接して気密室を設け、気密室と各ベローズ
を結合し、気密室と水冷通路を隔てる壁の両面に突起を
設けたことを特徴とする半導体装置の冷却装置。 ３、特許請求の範囲第２項において、低沸点の冷却媒体
を封入する気密室につなげて内圧によつて自由に伸縮可
能なベローズを設けたことを特徴とする半導体装置の冷
却装置。 ４、特許請求の範囲第１項において、ハウジングに設け
る水冷通路の１本の断面を１ｍｍ＾２以下とし、それを
多数形成したハウジングを、微細な溝を多数設けた薄板
を多数積層接合して組立てたことを特徴とする半導体装
置の冷却装置。 ５、特許請求の範囲第１項において、ハウジングを構成
する材料を複数化し、気密封止するための外壁を熱膨張
の小さいコバールでつくり、水冷通路を設けた熱交換体
を熱伝導性の良い材料例えばＣｕやＡｌでつくつたこと
を特徴とする半導体装置の冷却装置。 ６、特許請求の範囲第１項において、中間熱伝導体をベ
ローズの内部に柱状に突出する構造とし、その表面に凸
凹を設け沸騰伝熱面を形成したことを特徴とする半導体
装置の冷却装置。[Claims] 1. A semiconductor device in which a complex number of bare semiconductor chips are mounted face down on a multilayer wiring board, and the multilayer wiring board is sealed with a housing, in which a water cooling passage is provided in the housing; An intermediate heat transfer body made of electrically insulating ceramic with good heat conduction and metal with good heat conduction is bonded to the back of the semiconductor chip, and the intermediate heat transfer body and the housing are connected to each other with high flexibility. A cooling device for a semiconductor device, which is connected by a bellows and has a low boiling point cooling medium sealed inside the bellows. 2. In claim 1, an airtight chamber is provided in contact with the housing provided with the water cooling passage, the airtight chamber and each bellows are connected, and projections are provided on both sides of the wall separating the airtight chamber and the water cooling passage. A semiconductor device cooling device characterized by: 3. A cooling device for a semiconductor device according to claim 2, characterized in that a bellows is provided which is connected to an airtight chamber in which a low-boiling point cooling medium is sealed and can be freely expanded and contracted by internal pressure. 4. In claim 1, the cross section of one of the water cooling passages provided in the housing is 1 mm^2 or less, and a housing in which a large number of water cooling passages are formed is formed by laminating and bonding a large number of thin plates provided with a large number of fine grooves. A cooling device for a semiconductor device characterized by being assembled. 5. In claim 1, the housing is made of a plurality of materials, the outer wall for airtight sealing is made of Kovar with low thermal expansion, and the heat exchanger provided with water cooling passages is made of a material with good thermal conductivity. A cooling device for a semiconductor device characterized by being made of a material such as Cu or Al. 6. A cooling device for a semiconductor device according to claim 1, characterized in that the intermediate heat conductor has a structure in which it projects in a columnar manner inside the bellows, and its surface is provided with irregularities to form a boiling heat transfer surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12049385A JPS61279157A (en) | 1985-06-05 | 1985-06-05 | Cooling apparatus for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12049385A JPS61279157A (en) | 1985-06-05 | 1985-06-05 | Cooling apparatus for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61279157A true JPS61279157A (en) | 1986-12-09 |
Family
ID=14787556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12049385A Pending JPS61279157A (en) | 1985-06-05 | 1985-06-05 | Cooling apparatus for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61279157A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4977443A (en) * | 1988-09-21 | 1990-12-11 | Hitachi, Ltd. | Semiconductor module and an electronic computer using the semiconductor module |
| EP0411119A1 (en) * | 1988-04-08 | 1991-02-06 | Hitachi, Ltd. | Semiconductor module, its cooling system and computer using the cooling system |
| US5006924A (en) * | 1989-12-29 | 1991-04-09 | International Business Machines Corporation | Heat sink for utilization with high density integrated circuit substrates |
| JPH0359645U (en) * | 1989-10-13 | 1991-06-12 | ||
| WO2007145741A2 (en) * | 2006-06-07 | 2007-12-21 | The Boeing Company | Encapsulated multi-phase electronics heat sink |
| WO2024030671A1 (en) * | 2022-08-05 | 2024-02-08 | Transport Phenomena Technologies, Llc | Compliant cooling plates |
-
1985
- 1985-06-05 JP JP12049385A patent/JPS61279157A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0411119A1 (en) * | 1988-04-08 | 1991-02-06 | Hitachi, Ltd. | Semiconductor module, its cooling system and computer using the cooling system |
| US4977443A (en) * | 1988-09-21 | 1990-12-11 | Hitachi, Ltd. | Semiconductor module and an electronic computer using the semiconductor module |
| JPH0359645U (en) * | 1989-10-13 | 1991-06-12 | ||
| US5006924A (en) * | 1989-12-29 | 1991-04-09 | International Business Machines Corporation | Heat sink for utilization with high density integrated circuit substrates |
| WO2007145741A2 (en) * | 2006-06-07 | 2007-12-21 | The Boeing Company | Encapsulated multi-phase electronics heat sink |
| WO2007145741A3 (en) * | 2006-06-07 | 2008-02-14 | Boeing Co | Encapsulated multi-phase electronics heat sink |
| US7561425B2 (en) | 2006-06-07 | 2009-07-14 | The Boeing Company | Encapsulated multi-phase electronics heat-sink |
| WO2024030671A1 (en) * | 2022-08-05 | 2024-02-08 | Transport Phenomena Technologies, Llc | Compliant cooling plates |
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