JPS612331A - 半導体素子の樹脂封止方式 - Google Patents

半導体素子の樹脂封止方式

Info

Publication number
JPS612331A
JPS612331A JP12421484A JP12421484A JPS612331A JP S612331 A JPS612331 A JP S612331A JP 12421484 A JP12421484 A JP 12421484A JP 12421484 A JP12421484 A JP 12421484A JP S612331 A JPS612331 A JP S612331A
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
sealing resin
disk
thinner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12421484A
Other languages
English (en)
Inventor
Shin Tada
多田　伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP12421484A priority Critical patent/JPS612331A/ja
Publication of JPS612331A publication Critical patent/JPS612331A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 く技術分野〉 本発明は、半導体素子の樹脂封止方式に関するものであ
る。
〈従来技術〉 従来の半導体素子の樹脂封止方式は、第２図（イ）〜（
ニ）に示すように、配線基板１と配線基板１にフリップ
チップボンティングされた半導体素子２の間に樹脂吐出
ノズル３を使用して、浸透樹脂４を注入しくイ）、注入
後半導体素子２の上に封止樹脂５を滴下したのも（ロ）
、（ハ）、該封止樹脂５は、加熱。
硬化する際温度上昇とともに粘度か下かり形状が不揃に
なるので、これを防ぐために封止樹脂５の」−をディス
ク６で押し利は加熱硬化させている。
しかしながらこの樹脂封止方式によれば、半導体素子２
とディスク６との間の封止樹脂層が５０〜１００μｍ１
デイスク６自体か＋５０−２５０μｍ程度となり、どう
しても薄型化することか出来なかった。
そこで薄型化のためには、たとえばディスク６の薄型化
か考えられるか、この場合封止樹脂の表面張力により、
ディスク板の中央部か盛り−Ｌかってしまいかえって厚
くなってしまう。
また加圧を充分に加えてディスク６と半導体素子２の間
の樹脂層を薄くさせることが考えられるが、この場合加
圧装置の操作等に手間がかかると共に、封止樹脂にスト
レスがたまりひび割れの原因となってしまう。
〈目　的〉 本発明はかかる従来の欠点に鑑みて成されたもので、半
導体素子の側壁を囲むように、配線基板−にに封止樹脂
を設け、かつ半導体素子の上面に直接フィルムディスク
を接着することにより厚みを薄くし、形状を揃わせた半
導体素子の樹脂封止方式を提供することを目的とする。
〈実施例〉 以下図にもとづいて本発明の詳細な説明する。
第１図（イ）〜に）は本発明方式を説明する図である。
本発明の半導体素子の樹脂封止方式は、配線基板ｌと配
線基板１にフリップチップボンディングされた半導体素
子２の間に、従来例と同じように浸透樹脂４を毛細管現
象を利用して注入しく１′）、注入後半導体素子２の側
壁を囲むように従来例よりもやや高粘度の封止樹脂７を
ノズルにて図示の如く滴ドする（口）、（ハ）。次に樹
脂を滴下していない半導体素子の」−面に接着剤９イ」
フィルムディスク８（例えば、利質としてポリエステル
フィルム、接着剤としてつ１〜タン系接着剤を用いる。
）を接着させて、半導体素子２の側壁を囲んでいる封止
樹脂７をフィルムディスク８にすいよせるに）。そして
この状態で加熱硬化させる。
かかる樹脂封止方式によれば、封止樹脂を半導体素子２
の周囲に滴下し、樹脂のない素子の上面に直接フィルム
ディスク８を貼付けるようにしたので、たとえば接着剤
層９が２０〜３０μｍとしても、従来のこの部分の樹脂
層１００μｍよりも薄くできる。さらにフィルムディス
ク８を半導体素子２の上面に直接貼付けるので、該ディ
スク８が非常に簿くても中央部がふくらむおそれかない
。したかって従来のディスク６の厚さは約１５０μｍで
あるのに対して、本発明方式では２０μｍ程度にするこ
とかでき、カード電卓等のより薄型を要求するものに対
しては、特に有用である。
〈効　果〉 以上の様に、本発明の樹脂封止方式は、半導体素子の側
壁を囲むように配線基板上に封止樹脂を設け、互生導体
素子の上面に直接フィルムディスクを接着して成るから
、半導体素子とフィルムディスクとの間から封止樹脂が
なくなり、フィルムディスク、接着剤の厚みも従来例の
ディスクの厚めよりもかなり薄くなったため、電子部品
の薄型化に大いに有用である。
【図面の簡単な説明】
第１図（イ）乃至に）は本発明方式を説明する図、第２
図（イ）乃至に）Ｇ」従来方式を説明する図である。 ４　浸透樹脂　５゛封止樹脂　６　ディスク７　やや高
粘度な封止樹脂

Claims (1)

  1. 【特許請求の範囲】 １、回路パターンを有する配線基板上に、半導体素子を
    載置し、前記半導体素子を樹脂で封止する半導体素子の
    封止方式において、 前記半導体素子の側壁を囲むように配線基板上に封止樹
    脂を設け、且前記半導体素子の上面に直接フィルムディ
    スクを接着して成ることを特徴とする半導体素子の樹脂
    封止方式。
JP12421484A 1984-06-14 1984-06-14 半導体素子の樹脂封止方式 Pending JPS612331A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12421484A JPS612331A (ja) 1984-06-14 1984-06-14 半導体素子の樹脂封止方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12421484A JPS612331A (ja) 1984-06-14 1984-06-14 半導体素子の樹脂封止方式

Publications (1)

Publication Number Publication Date
JPS612331A true JPS612331A (ja) 1986-01-08

Family

ID=14879815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12421484A Pending JPS612331A (ja) 1984-06-14 1984-06-14 半導体素子の樹脂封止方式

Country Status (1)

Country Link
JP (1) JPS612331A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999009592A1 (fr) * 1997-08-13 1999-02-25 Citizen Watch Co., Ltd. Assemblage semi-conducteur du type flip et son procede de fabrication
US6459152B1 (en) * 1999-10-27 2002-10-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999009592A1 (fr) * 1997-08-13 1999-02-25 Citizen Watch Co., Ltd. Assemblage semi-conducteur du type flip et son procede de fabrication
US6459152B1 (en) * 1999-10-27 2002-10-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface
US7094630B2 (en) 1999-10-27 2006-08-22 Renesas Technology Corp. Method of fabricating semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface

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