JPS62137863A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS62137863A JPS62137863A JP60279559A JP27955985A JPS62137863A JP S62137863 A JPS62137863 A JP S62137863A JP 60279559 A JP60279559 A JP 60279559A JP 27955985 A JP27955985 A JP 27955985A JP S62137863 A JPS62137863 A JP S62137863A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- memory cell
- capacitor
- electrode
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体メモリ装置の構成要素とじて広く利用
されるＤＲＡＭセルに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to DRAM cells that are widely used as components of semiconductor memory devices.
従来の技術
近年、半導体メモリ装置の高密度化が進み、特にＤＲＡ
Ｍの高集積化、大量答化は著しい。このようなりＲＡＭ
の発展はそのチップサイズの半分以上の面積を占めるメ
モリセルの高密度化技術の発展に負う所が大きい。現在
、一層の高密度化を 。2. Description of the Related Art In recent years, semiconductor memory devices have become more densely packed, especially DRA.
The high integration and mass response of M is remarkable. RAM like this
The development of the chip is largely due to the development of high-density technology for memory cells, which occupy more than half the area of the chip. Currently, we are working on further densification.
目的として種々の立体構造ＤＲＡＭセルが提案されて来
ている。従来、この種の立体構造ＤＲＡＭセルは、−例
として第２図に示す様な構成であった。第２図において
、１はビットラインを形成するドレイン、２は信号読み
出し用トランスファゲートを構成するＭＯＳ）ランジス
タのゲー） ３１化膜、３はワード線を構成する、例え
ば、ポリシリコンで形成されたゲート電極、４はメモリ
セルのソース拡散部、５はメモリセルのキャパシタを構
成する絶縁薄膜、６はセルプレートと称される例えばポ
リシリコンを用いたキャパシタ用プレート電極、７はセ
ル間分離用厚膜、８は基板、１０は層間絶縁膜である。Various three-dimensional DRAM cells have been proposed for this purpose. Conventionally, this type of three-dimensional structured DRAM cell has had a configuration as shown in FIG. 2, for example. In Fig. 2, 1 is a drain that forms a bit line, 2 is a gate of a MOS transistor that forms a transfer gate for signal readout, and 3 is a film made of polysilicon that forms a word line. 4 is a gate electrode, 4 is a source diffusion part of a memory cell, 5 is an insulating thin film constituting a capacitor of a memory cell, 6 is a capacitor plate electrode called a cell plate made of polysilicon, for example, and 7 is a thickness for separating cells. 8 is a substrate, and 10 is an interlayer insulating film.
これはいわゆるトレンチ構造と言われるメモリセル構造
の一例である。この構造は、トレンチを基板８の深さ方
向に形成するため、トレンチ深さの制御により蓄積用容
量もメモリセルとして必要とされる値（ｓｏｆＦ以上と
一般にいわれている。）を充分確保できる。また、この
構造においては、トレンチを単に信号蓄積キャパシタと
してだけでなく素子分離にも利用しており、セル間分離
用厚膜７を厚くとることによりセル間リーク電流を充分
低くとることができる。This is an example of a memory cell structure called a so-called trench structure. In this structure, since the trench is formed in the depth direction of the substrate 8, by controlling the depth of the trench, the storage capacitance can be sufficiently secured to a value required for the memory cell (generally said to be more than sofF). Furthermore, in this structure, the trench is used not only as a signal storage capacitor but also for element isolation, and by making the inter-cell isolation thick film 7 thick, the inter-cell leakage current can be kept sufficiently low.
立体化構造セルの別の一例として、スタックド構造があ
り、これは第３図に示す様な構成である。Another example of a three-dimensional structure cell is a stacked structure, which has a configuration as shown in FIG.
（例えば、１９８５・６・３・日経エレクトロニクスＰ
２Ｏ９〜２３１）、第３図において、１はビットライン
を形成するドレイン、２は信号読み出し用トランスファ
ゲートとなるＭＯＳ）ランジスタのゲート酸化嘆、３は
ワード線を構成する、例えば、ポリシリコンで形成され
たゲート電極、４はメモリセルのソース拡散部、６はメ
モリセルのキャパシタを構成する絶縁膜、６はセルプレ
ートを形成する、例えば、ポリシリコンを用いたプレー
ト電極、７はセル間分離用厚膜、８は屑板、９はメモリ
セルのソース部を構成する・ｎ電性電極、１ｏは層間絶
縁膜である。キャパシタなま、プレート電極らとメモリ
セルのソース部を形成する４ ’ＡＣ性電極電極９間に
形成され、同電極９のワード線上の部分や側面部をキャ
パシタとして利用できることにより、セル容量の増加が
得られる。ａ線ソ７）エラーハメモリセルのソース部下
のｐｎ接合領域に形成される空乏層をα粒子が通過する
ととにより生ずるが、このスタックド構造では、メモリ
セルのソース拡散部と基板との間のｐｎ接合領域が、従
来の平面型や前述のトレンチ構成メモリセルに比べて非
常に小さく、そのためα線ソフトエラーに対して極めて
強くなる。(For example, 1985.6.3 Nikkei Electronics P.
2O9-231), In Fig. 3, 1 is a drain forming a bit line, 2 is a gate oxidation layer of a MOS transistor which is a transfer gate for signal reading, and 3 is a word line, made of polysilicon, for example. 4 is a source diffusion part of the memory cell, 6 is an insulating film forming a capacitor of the memory cell, 6 is a plate electrode that forms a cell plate, for example, using polysilicon, and 7 is for isolation between cells. A thick film, 8 a scrap plate, 9 an n-electrode constituting the source portion of the memory cell, and 1o an interlayer insulating film. A capacitor is formed between the plate electrode and the 4' AC electrode 9 that forms the source part of the memory cell, and the cell capacitance is increased by using the part on the word line and the side part of the electrode 9 as a capacitor. is obtained. 7) Error occurs when alpha particles pass through the depletion layer formed in the pn junction region below the source of the memory cell. The pn junction region is much smaller than that of the conventional planar type or the trench-structured memory cell described above, making it extremely resistant to α-ray soft errors.
発明が解決しようとする問題点
このような従来の構成では、トレンチ構造、スタックド
構造のそれぞれについて次の様な間噴があった。Problems to be Solved by the Invention In such conventional configurations, there are the following intermittent injections in each of the trench structure and stacked structure.
まずトレンチ構造のメモリセルは、蓄積容量については
トレンチを所定の深さに選べば必要な大きさの値が得ら
れるが、基板深部にトレンチを埋込んでいるため、プレ
ート電極下の基板中の空乏層が大きくなり、α線ソフト
エラー率が同一容量の平面型セルに比べて一桁以上も大
きくなる。そのため、α線ソフトエラー率を低くするに
は平面上のキャパシタセル面積部分を大きくしたりする
必要があり、高集積化には不利となる。First, in trench-structured memory cells, the required storage capacity can be obtained by selecting the trench to a predetermined depth, but since the trench is buried deep in the substrate, The depletion layer becomes larger, and the α-ray soft error rate increases by more than an order of magnitude compared to a planar cell with the same capacity. Therefore, in order to reduce the α-ray soft error rate, it is necessary to increase the area of the capacitor cell on the plane, which is disadvantageous for high integration.
これに対し、トレンチの側面あるいは底面にイオンを打
ち込む事により、いわゆるＨ ｉ −Ｃ構造を形成して
空乏層の伸びを押える事もできるが、高濃度注入の結果
としてリーク電流の増大や、プロセスの複雑化などが生
じ、実用上問題がある。On the other hand, by implanting ions into the sides or bottom of the trench, it is possible to form a so-called H i -C structure and suppress the growth of the depletion layer, but as a result of high-concentration implantation, leakage current increases and process This poses a practical problem as it complicates the process.
またトレンチの面にそって、薄い絶縁膜を形成する必要
があるが、トレンチの面の結晶軸に対する方位によって
、絶縁膜（例えばＳｌ ０２ ）の酸化レートが異なり
、一様な厚さの絶縁膜を成長させることが難しく、絶縁
耐圧のバラツキと低下が生じ実用上問題となっている。Also, it is necessary to form a thin insulating film along the trench surface, but the oxidation rate of the insulating film (for example, Sl 02 ) varies depending on the orientation of the trench surface with respect to the crystal axis, so that the insulating film has a uniform thickness. It is difficult to grow the dielectric strength, and the dielectric strength varies and decreases, which is a practical problem.
また、メモリセルのキャパシタを構成する絶縁膜の誘電
率の増大と絶縁耐圧の増大の両立のために、前記絶縁膜
にＳｉ３Ｎ４とＳ ｔ Ｏ２との多層構造を用いる必要
があるが、トレンチ内壁を構成する基板の単結晶シリコ
ンに、 Ｓ ｌ ２ Ｎ ３のストレスによる影響が発
生し、基板シリコンに欠陥等が形成されリーク電流が大
きくなり実用上問題となる。Furthermore, in order to both increase the dielectric constant and increase the dielectric strength of the insulating film constituting the capacitor of the memory cell, it is necessary to use a multilayer structure of Si3N4 and S t O2 for the insulating film. The single crystal silicon of the constituent substrate is affected by the stress of S 1 2 N 3 , defects etc. are formed in the substrate silicon, and leakage current increases, which poses a practical problem.
これらの問題は、高集積化大容量化を更に推し進める際
には、一層重大な障害となることは明らかである。It is clear that these problems will become even more serious obstacles when further promoting higher integration and larger capacity.
一方、スタックド構造は、メモリセルのソース拡散部と
基板とのｐｎ接合部の領域が小さく、そのためンフトエ
ラーに強いという利点をもつ。また素子分離幅が平面型
セルに比べて大きくとれ、素子間リークを容易に押える
ことができる。しかし、その構造上メモリセル容量の増
大に限界があり、素子の微細化高集積化に伴ってメモリ
セル容量が不足する。On the other hand, the stacked structure has the advantage that the region of the pn junction between the source diffusion part of the memory cell and the substrate is small, and is therefore resistant to amplifier errors. Furthermore, the element isolation width can be made larger than that of a planar cell, and leakage between elements can be easily suppressed. However, due to its structure, there is a limit to the increase in memory cell capacity, and as elements become smaller and more highly integrated, the memory cell capacity becomes insufficient.
本発明はこのような問題点を解決するもので、蓄積容量
の増大を実現し、高集積化、大容量化が可能で、ソフト
エラー率、リーク電流が大幅に低域し、キャパシタを構
成する絶縁膜の形成が容易なメモリセル構造を備えた半
導体メモリ装置を提供することを目的と（〜だものであ
る。The present invention solves these problems by realizing an increase in storage capacity, enabling high integration and large capacity, and significantly lowering soft error rate and leakage current, thereby forming a capacitor. An object of the present invention is to provide a semiconductor memory device having a memory cell structure in which an insulating film can be easily formed.
問題点を解決するだめの手段
この問題点を解決するために本発明は、ＦＣＣセルをは
じめとするトレンチ構造とスタックド構造の長所を共に
有する新規な構造のメモリセルを有する半導体メモリ装
置を提供するものである。Means for Solving the Problem In order to solve this problem, the present invention provides a semiconductor memory device having a memory cell of a new structure that has both the advantages of a trench structure and a stacked structure, including an FCC cell. It is something.
本発明は、メモリセル上の２本のワード線間にトレンチ
を形成し、ワード線上及びトレンチ内壁に層間絶縁膜を
形成し、スタックド構造のキャパシタを前記層間絶縁膜
上及びフィールド酸化膜上に形成し、メモリセルのソー
ス部接触リードを構成する導電性電極とメモリセルのソ
ース拡散部との電気的コンタクト部をトレンチ内部で形
成するものである。The present invention forms a trench between two word lines on a memory cell, forms an interlayer insulating film on the word line and on the inner wall of the trench, and forms a stacked structure capacitor on the interlayer insulating film and the field oxide film. However, an electrical contact portion between the conductive electrode constituting the source portion contact lead of the memory cell and the source diffusion portion of the memory cell is formed inside the trench.
作 用
本発明によると、トレンチ構造内でソース拡散部と接触
し、かつ、 同トレンチ内部からワード線上に絶縁的に
延在する導電性電極をキャパシタ用の第１の電極とし、
この上に、誘電体を介して、第２の電トンを形成した立
体構造のメモリ用ギャパシタが得らね５、ソフトエラー
、リーク電流特性の高性能のものが得られる。According to the present invention, a conductive electrode that contacts the source diffusion part within the trench structure and extends insulatively from inside the trench onto the word line is used as the first electrode for the capacitor,
Moreover, a memory gapacitor having a three-dimensional structure in which a second electron is formed through a dielectric material can be obtained, and one with high performance in soft error and leakage current characteristics can be obtained.
実施例
第１図は本発明の一実施例による半導体メ千り装置のメ
モリセル部の要部側断面（刈である。第１図において、
１はビットラインを形成するドレイン、２は信号読み出
し用トランスファゲートを構成スるＭＯＳトランジスタ
のゲート酸化膜、３はワード線を構成する、ポリシリコ
ンで形成されたゲート電極、４はトレンチ内の側面に拡
がるメモリセルのソース拡散部、５はメモリセルのキャ
パシタを構成する５１０２絶縁嘆、６は、ソース拡散部
６とトレンチ内面で接触し、セルプレートを形成するポ
リシリコンを用いたプレート電極、７はセル間分離用厚
膜、８は基板、９はメモリセルのソース部を形成するポ
リシリコンを用いた導電性電極、１０は層間絶縁膜であ
る。キャパシタは、プレート電極６とメモリセルのソー
ス部を形成する導電性電極９との間に形成される。Embodiment FIG. 1 is a side cross-sectional view of a main part of a memory cell portion of a semiconductor manufacturing device according to an embodiment of the present invention.
1 is a drain forming a bit line, 2 is a gate oxide film of a MOS transistor forming a signal readout transfer gate, 3 is a gate electrode made of polysilicon forming a word line, and 4 is a side surface inside the trench. 5 is a 5102 insulation layer forming a capacitor of the memory cell; 6 is a plate electrode made of polysilicon that is in contact with the source diffusion portion 6 on the inner surface of the trench and forms a cell plate; 7 8 is a thick film for cell isolation, 8 is a substrate, 9 is a conductive electrode made of polysilicon forming a source portion of a memory cell, and 10 is an interlayer insulating film. A capacitor is formed between the plate electrode 6 and a conductive electrode 9 forming the source part of the memory cell.
この構成により、次の様な作用がある。This configuration has the following effects.
蓄積容量がトレンチ内に埋め込捷れた部分とそれ以外の
平面上の部分から成っており、さらにトレンチ内の部分
は、第３電極の側面のすべてがセルキャパシタとなるた
めに容量が極めて増大する。The storage capacitor consists of the part buried in the trench and the other part on the plane, and the capacitance of the part inside the trench is extremely increased because all the sides of the third electrode become cell capacitors. do.
同じセル面積、同じトレンチ深さの従来形トレンチ構造
と比較してもセル容量は倍以上となる。検討によれば、
セル面積が８μｍ′の場合、トレンチ深さを３μｍとる
ことによりセル容量を１６ｏｆＦとることができ、セル
面積が６μｍ′の場合には、同じくトレンチ深さを３μ
ｍとして、セル容量を１１０ｆＦとることができ、１つ
のメモリセルに最低必要とされる容量の５０ｆＦを充分
に満たすことができる。Compared to a conventional trench structure with the same cell area and the same trench depth, the cell capacity is more than double. According to the study,
When the cell area is 8 μm', the cell capacitance can be set to 16 of F by setting the trench depth to 3 μm, and when the cell area is 6 μm', the trench depth is also set to 3 μm.
As m, the cell capacitance can be set to 110 fF, which can fully satisfy the minimum required capacitance of 50 fF for one memory cell.
またソース部の面積を設計上、あるいはプロセス技術上
許容できる限り小さくすることにより、メモリセルのソ
ース拡散部と基板との間のｐｎ接合領域を小さくするこ
とができるため、メモリセルのリーク電流を極めて小さ
くとることができる。Furthermore, by reducing the area of the source region to the smallest possible design or process technology, it is possible to reduce the pn junction region between the source diffusion region of the memory cell and the substrate, thereby reducing the leakage current of the memory cell. It can be made extremely small.
また前記ｐｎ接合領域が小さいだめ、それに伴う空乏層
も非常に小さくなり、これによりα線ソフトエラーを抜
本的に低減させることができる。加えてキャパシタとな
る薄い絶縁膜を形成する場合、ポリシリコンの酸化ンー
トは方位に依存せず一様な厚さの絶縁膜を成長させるこ
とができ、絶縁耐圧のばらつきと低下を押えることがで
きる。Furthermore, since the pn junction region is small, the accompanying depletion layer also becomes very small, thereby making it possible to drastically reduce α-ray soft errors. In addition, when forming a thin insulating film to serve as a capacitor, polysilicon oxidation can grow an insulating film with a uniform thickness regardless of orientation, which can suppress variations and decreases in dielectric strength voltage. .
さらにメモリセルのキャパシタを構成する絶縁膜として
Ｓｉ３Ｎ４と３１０２ との多層構造を用いた場合で
も、メモリセルのキャパシタを構成する吸収できること
になり多層絶縁膜の安定形成にも極めて有利となる。Furthermore, even when a multilayer structure of Si3N4 and 3102 is used as the insulating film constituting the capacitor of the memory cell, it is possible to absorb the components constituting the capacitor of the memory cell, which is extremely advantageous for stable formation of the multilayer insulating film.
発明の効果
以上の様に、本発明によれば、半導体メモＩＪ Ｗ置は
蓄積容量を極めて大きくできるばかりでなく、ソフトエ
ラー率及びリーク電流を抜本的に低減でき、プロセス上
絶縁薄膜の形成も容易となる。従って本発明は半導体メ
モリ装置の一層の高集積化、大容量化を極めて容易に実
現さするという効果が得られる。Effects of the Invention As described above, according to the present invention, the semiconductor memory IJW device not only can have an extremely large storage capacity, but also can drastically reduce the soft error rate and leakage current, and can also reduce the formation of an insulating thin film during the process. It becomes easier. Therefore, the present invention has the effect of extremely easily realizing even higher integration and larger capacity of a semiconductor memory device.
第１図は本発明の一実施例による半導体メモリセル部を
示す要部側断面図、第２図は従来のトレンチ構造の１例
であるＦＣＣ構造メモリセルを示す要部側断面図、第３
図は従来のスタソクト構造メモリセルを示す要部側断面
図である。
１・・・・・・ビットラインを形成するドレイン、２・
・・・・・ゲート絶縁膜、３・・・・・・ワードライン
を形成するゲート電極、４・・・・・・メモリセルのソ
ース拡散部、６・・・・・・メモリセルのキャパシタを
構成する絶縁膜、６・・・・・・プレート電極、７・・
・・・・分離用厚膜、８・・・・・・基板、９・・・・
・・メモリセルのソース部を構成する導電性電極、１Ｑ
・・・・・層間絶縁膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名ｌ０
−−−ノｖ ７’４ ＄ｕ！Ｍ笑第１図
第２図
第３図FIG. 1 is a side cross-sectional view of a main part showing a semiconductor memory cell section according to an embodiment of the present invention, FIG. 2 is a side cross-sectional view of a main part showing an FCC structure memory cell which is an example of a conventional trench structure, and FIG.
The figure is a sectional side view of a main part of a conventional star socket structure memory cell. 1... Drain forming a bit line, 2...
... Gate insulating film, 3 ... Gate electrode forming word line, 4 ... Source diffusion part of memory cell, 6 ... Capacitor of memory cell. Constituent insulating film, 6... Plate electrode, 7...
... Thick film for separation, 8 ... Substrate, 9 ...
...Conductive electrode that constitutes the source part of the memory cell, 1Q
...Interlayer insulating film. Name of agent: Patent attorney Toshio Nakao and 1 other person
---Nov 7'4 $u! M lolFigure 1Figure 2Figure 3
Claims (2)
ランジスタ、同トランジスタのソース領域に接触するト
レンチ構造部および前記トレンチ構造部を介した位置に
素子分離領域を有するとともに、前記ソース領域に対し
て前記トレンチ構造部の内面で接触し、同トレンチ内部
で前記半導体基板と絶縁されて、前記素子分離領域上に
延在された第１の電極および誘電体を介して前記第１の
電極に対向する第２の電極をそなえた半導体メモリ装置
。(1) An insulated gate field effect transistor is provided in a predetermined region of a semiconductor substrate, a trench structure is in contact with the source region of the transistor, and an element isolation region is provided at a position via the trench structure, and A first electrode that is in contact with the inner surface of the trench structure, is insulated from the semiconductor substrate inside the trench, and extends over the element isolation region, and faces the first electrode via a dielectric. A semiconductor memory device including a second electrode.
界効果トランジスタのゲート電極上に延在された構成の
特許請求の範囲第１項記載の半導体メモリ装置。(2) The semiconductor memory device according to claim 1, wherein the first electrode extends over the gate electrode of the insulated gate field effect transistor via an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60279559A JPH0795566B2 (en) | 1985-12-12 | 1985-12-12 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60279559A JPH0795566B2 (en) | 1985-12-12 | 1985-12-12 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62137863A true JPS62137863A (en) | 1987-06-20 |
| JPH0795566B2 JPH0795566B2 (en) | 1995-10-11 |
Family
ID=17612658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60279559A Expired - Lifetime JPH0795566B2 (en) | 1985-12-12 | 1985-12-12 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0795566B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6447068A (en) * | 1987-08-18 | 1989-02-21 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| JPS6451251A (en) * | 1987-08-18 | 1989-02-27 | Hitachi Seiki Kk | Pallet provided with index device |
| JPH02234466A (en) * | 1989-03-07 | 1990-09-17 | Nec Corp | Semiconductor memory cell and manufacture thereof |
| US5124765A (en) * | 1990-08-14 | 1992-06-23 | Samsung Electronics Co., Ltd. | Highly integrated semiconductor memory device with trench capacitors and stacked capacitors |
| US5156993A (en) * | 1990-08-17 | 1992-10-20 | Industrial Technology Research Institute | Fabricating a memory cell with an improved capacitor |
| US5675163A (en) * | 1994-10-26 | 1997-10-07 | Nec Corporation | Non-volatile semiconductor memory device with thin insulation layer below erase gate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62136069A (en) * | 1985-12-10 | 1987-06-19 | Hitachi Ltd | Semiconductor device and manufacture of the same |
-
1985
- 1985-12-12 JP JP60279559A patent/JPH0795566B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62136069A (en) * | 1985-12-10 | 1987-06-19 | Hitachi Ltd | Semiconductor device and manufacture of the same |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6447068A (en) * | 1987-08-18 | 1989-02-21 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| JPS6451251A (en) * | 1987-08-18 | 1989-02-27 | Hitachi Seiki Kk | Pallet provided with index device |
| JPH0661672B2 (en) * | 1987-08-18 | 1994-08-17 | 日立精機株式会社 | Pallet with indexing device |
| JPH02234466A (en) * | 1989-03-07 | 1990-09-17 | Nec Corp | Semiconductor memory cell and manufacture thereof |
| US5124765A (en) * | 1990-08-14 | 1992-06-23 | Samsung Electronics Co., Ltd. | Highly integrated semiconductor memory device with trench capacitors and stacked capacitors |
| US5156993A (en) * | 1990-08-17 | 1992-10-20 | Industrial Technology Research Institute | Fabricating a memory cell with an improved capacitor |
| US5675163A (en) * | 1994-10-26 | 1997-10-07 | Nec Corporation | Non-volatile semiconductor memory device with thin insulation layer below erase gate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0795566B2 (en) | 1995-10-11 |
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