JPS61224333A - Molding method for semiconductor device - Google Patents
Molding method for semiconductor deviceInfo
- Publication number
- JPS61224333A JPS61224333A JP60064928A JP6492885A JPS61224333A JP S61224333 A JPS61224333 A JP S61224333A JP 60064928 A JP60064928 A JP 60064928A JP 6492885 A JP6492885 A JP 6492885A JP S61224333 A JPS61224333 A JP S61224333A
- Authority
- JP
- Japan
- Prior art keywords
- protective film
- pad
- semiconductor device
- wiring
- jcr
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000000465 moulding Methods 0.000 title claims description 19
- 230000001681 protective effect Effects 0.000 claims abstract description 37
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229920001296 polysiloxane Polymers 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 239000007888 film coating Substances 0.000 abstract 1
- 238000009501 film coating Methods 0.000 abstract 1
- 238000002161 passivation Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 35
- 239000003795 chemical substances by application Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 8
- 239000004033 plastic Substances 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000005336 cracking Methods 0.000 description 5
- 230000006872 improvement Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000008065 acid anhydrides Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000003431 cross linking reagent Substances 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 239000010680 novolac-type phenolic resin Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
１１ユｐ困ユ公１
本発明は半導体素子のモールド方法、特にモールド剤の
ストレスによる難点を解決し得るジャンクションコート
レジン保護膜を該素子表面に選択的に適用する方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of molding a semiconductor device, and particularly a method of selectively applying a junction coat resin protective film to the surface of the device, which can solve the problems caused by the stress of the molding agent. Regarding.
従来の技術
半導体装置または素子は、一般に所定の機能付与がなさ
れた後、適当な方法でパッケージングされて実際の使用
に付されることになる。このパッケージングの種類とし
ては、その構造からセラミックス、メタル、ガラス、プ
ラスチックパッケージなどに分類されているが、最近で
はこれらを組合せるなどして更に一層複雑な構造並びに
材料のものが、特に素子の大型化、高集積化などの要求
に伴って出現してきた。これらは夫々固有の利点を有し
、パッケージングすべき半導体素子の種類、特性に応じ
て使いわけられている。2. Description of the Related Art Semiconductor devices or elements are generally provided with predetermined functions and then packaged in an appropriate manner before being put into actual use. Types of packaging are classified into ceramic, metal, glass, plastic packages, etc. based on their structure, but in recent years, even more complex structures and materials have been created by combining these packages, especially for elements. They have emerged in response to demands for larger size and higher integration. Each of these has its own advantages and is used depending on the type and characteristics of the semiconductor element to be packaged.
これらパッケージは、その信頼性の面からみると、周囲
環境からチップ等を隔離しあるいは保護し、該チップが
その回路機能を正常に果し得る雰囲気を提供し、放熱性
を改善する上で重要な機能を有している。即ち、回路設
計やチップ等の製造工程が完全であったとしても、パッ
ケージが不完全であったり不適当であったりする場合に
は、素子の破壊、品質の低下等をもたらし、半導体装置
とは無関係の不良モードを与えることになる。From the standpoint of reliability, these packages are important in isolating or protecting chips from the surrounding environment, providing an atmosphere in which the chips can properly perform their circuit functions, and improving heat dissipation. It has many functions. In other words, even if the circuit design and manufacturing process of chips, etc. are perfect, if the package is incomplete or inappropriate, it may lead to element destruction or quality deterioration, and the semiconductor device is no longer suitable. This would give an irrelevant failure mode.
更にいえば、半導体装置の所期の特性値を十分に維持し
、熱的、電気的導出、電極間の絶縁距離の確保などはも
とより、運搬、取扱い上の便宜のためにパフケージング
が施され、上記のように半導体装置の大型化、高集積化
、高性能化を更に進めるために、特に該装置と外部環境
との整合性を維持する上で重要な役割を演じている。こ
のような観点から、パッケージング技術ならびにその関
連技術の改良は、半導体装置作製技術において、半導体
素子自体の性能改善と共に解決されなければならない重
要な問題である。Furthermore, puff casing is applied not only to sufficiently maintain the desired characteristic values of semiconductor devices, to ensure thermal and electrical conduction, and insulation distance between electrodes, but also to facilitate transportation and handling. As described above, in order to further increase the size, high integration, and performance of semiconductor devices, they play an important role, especially in maintaining the compatibility between the devices and the external environment. From this point of view, improvements in packaging technology and related technologies are important issues that must be solved in semiconductor device manufacturing technology along with performance improvements of semiconductor elements themselves.
ところで、半導体装置のパッケージ方法としては金属、
セラミックス等と比較して取扱いが容易であり、量産性
に優れると共に低価格であることから、プラスチックモ
ールドによるパフケージング法が広く利用され、また様
々な改良が加えられて信頼性の面でも向上しており、実
用性の高いものとされている。By the way, as a packaging method for semiconductor devices, metal,
Compared to ceramics, it is easy to handle, has excellent mass productivity, and is inexpensive, so the puff caging method using plastic molds is widely used, and various improvements have been made to improve reliability. It is considered highly practical.
しかしながら、いまだ完全とはいえず、改善すべき余地
は多分に残されている。例えば半導体素子のプラスチッ
クモールドの際に問題となる大きな不都合としては、モ
ールド自体の割れあるいは素子割れ、表面保護膜の割れ
、断線等が知られている。特にモールド自体の割れ、表
面保護膜の割れ等は、パッケージ本来の周囲環境からの
素子の保護という機能を果し得す、パッケージ内への水
分の浸入や不純物の浸入などにより、配線の腐食、オー
プンなどの原因となる。また、モールド剤中に残留する
α−線による素子の損傷、ソフトエラー等の可能性があ
ることも知られて、いる。−そこで、上記のような各種
不都合を排除するために多くの研究がなされており、例
えばその１つとして、素子表面にシリコーン、ポリイミ
ド等のジャンクションコートレジン（以下ＪＣＲという
）をプレコートし、モールド剤によるストレスが素子に
直接作用しないように保護する方法が提案されている。However, it is still far from perfect and there is still much room for improvement. For example, major inconveniences that occur when plastic molding semiconductor elements are known include cracks in the mold itself or elements, cracks in the surface protective film, and disconnections. In particular, cracks in the mold itself, cracks in the surface protective film, etc., which can fulfill the original function of the package to protect the elements from the surrounding environment, may cause corrosion of the wiring due to the intrusion of moisture or impurities into the package. This may cause an open etc. It is also known that there is a possibility of element damage, soft errors, etc. due to α-rays remaining in the molding agent. -Therefore, many studies have been conducted to eliminate the various inconveniences mentioned above. For example, one of them is to pre-coat the element surface with junction coat resin (hereinafter referred to as JCR) such as silicone or polyimide, and to apply a molding agent. A method has been proposed to protect the device from direct stress caused by the stress.
しかしながら、この方法ではモールドとＪＣＲ保護膜と
の界面を貫いて配線用のアルミ、金線等の極細線が配置
される為に、応力が該界面部に集中し、素子のパッドと
パッケージの電極との電気的導通を保証している該配線
が断線される恐れがあった。However, in this method, because ultrafine wires such as aluminum or gold wires for wiring are placed through the interface between the mold and the JCR protective film, stress is concentrated at the interface, and the electrodes of the device pad and package There was a risk that the wiring, which guarantees electrical continuity with the terminal, would be disconnected.
この点につき添付第３図を参照しつつ更に詳しく述べる
と、例えばＳ１素子１上に設けられたＡＩなどのワイヤ
ボンディング用パッド２から伸びている層などの極細線
３はＪＣＲ層４とモールド５との間の界面６を貫いた状
態で存在している。従って、該界面６に応力が集中した
場合、その部分で配線３は大きな剪断力等の作用を受け
ることになり、しかも該配線は極めて細いので断線し易
い状況にあることがわかる。尚、参照番号７は表面保護
膜である。To explain this point in more detail with reference to the attached FIG. It exists in a state where it penetrates the interface 6 between. Therefore, when stress is concentrated at the interface 6, the wiring 3 will be subjected to a large shearing force or the like at that portion, and since the wiring is extremely thin, it will be easy to break. Note that reference number 7 is a surface protective film.
発明が解ゝしようとする問題点
以上述べたように、パフケージング技術は半導体素子の
進歩と共により高度化されかつ高信頼度が要求される傾
向にあり、半導体素子の改良と共に開発を進めなければ
ならない重要な技術である。Problems to be Solved by the Invention As stated above, puff caging technology tends to become more sophisticated and require higher reliability as semiconductor devices progress, and development must proceed with the improvement of semiconductor devices. This is an important technology that cannot be ignored.
プラスチックモールドによる半導体装置のパッケージン
グにおいて、特に解決すべき課題としてモールド剤の及
ぼすストレスによる素子割れ、保護膜の割れ等の欠点が
あり、その１解決策としてＪＣＲ保護膜のプレコート技
術が提案されたがいまだ完全とはいえず、モールド−Ｊ
ＣＲ保護膜界面部での応力集中による配線の断線の問題
が新たに提示されたにすぎない。In the packaging of semiconductor devices using plastic molds, there are problems that need to be solved in particular, such as cracking of the element and cracking of the protective film due to the stress exerted by the molding agent, and JCR protective film pre-coating technology was proposed as one solution. However, it is still not perfect, and Mold-J
This merely presents a new problem of wire breakage due to stress concentration at the CR protective film interface.
そこで、このような問題を解決し、プラスチックモール
ド技術の信頼性を高めることは、その実用化を促進し、
利用範囲を拡大すると共に、半導体素子パッケージの作
製歩留りを向上させるために極めて大きな意義を有する
。本発明の目的もこのような点にあり、新規な半導体装
置のモールド方法、特にＪＣＲ保護膜の改良製造方法を
提供することにあり、また素子割れ、表面保護膜の割れ
等の不良はもとより、配線金属線の断線等の問題を生じ
ることのない、高信頼度の半導体パッケージを提供する
ことも本発明の目的の１つである。Therefore, solving these problems and increasing the reliability of plastic mold technology will promote its practical application.
It has great significance in expanding the scope of use and improving the manufacturing yield of semiconductor device packages. The purpose of the present invention is to provide a new method for molding semiconductor devices, especially an improved manufacturing method for JCR protective films, and to prevent defects such as element cracks and cracks in the surface protective film. Another object of the present invention is to provide a highly reliable semiconductor package that does not cause problems such as disconnection of metal wiring lines.
問題点を解決するための手段
本発明者等は従来のプラスチックモールドによる半導体
素子の上記のような現状に鑑みて、上記欠点を解決し得
る技術を開発すべく種々検討した結果、パッケージング
の際に配線用の金属細線がＪＣＲ−モールド剤界面を通
らないように該ＪＣＲ保護膜を形成することが有利であ
るという着想の下に、ＪＣＲ保護膜を素子表面に選択的
に適用することにより上記目的が達成し得ることを見出
した。本発明はかかる新規知見に基き完成されたもので
ある。Means for Solving the Problems In view of the above-mentioned current state of semiconductor devices using conventional plastic molds, the inventors have conducted various studies to develop a technology that can solve the above-mentioned drawbacks. Based on the idea that it is advantageous to form the JCR protective film so that the thin metal wire for wiring does not pass through the JCR-molding agent interface, by selectively applying the JCR protective film to the element surface, the above I found that the purpose could be achieved. The present invention was completed based on this new knowledge.
即ち、本発明の半導体装置の、モールド方法は、完成さ
れた半導体装置表面に表面保護膜を形成し、フォトエツ
チングにより該半導体装置のパッド上部分に配線金属接
続用窓を設け、次いでＪＣＲを塗布し、マスクを介して
露光し、現像するフォトリソグラフィーにより該ＪＣＲ
保護膜のパッド上部分を除き、該ＪＣＲ保護膜を硬化し
、所定の配線を行い、モールド剤で封止することを特徴
とする。That is, the molding method of the semiconductor device of the present invention involves forming a surface protective film on the surface of the completed semiconductor device, forming a window for wiring metal connection on the upper part of the pad of the semiconductor device by photoetching, and then applying JCR. The JCR is then exposed to light through a mask and developed by photolithography.
The JCR protective film is cured except for the upper part of the pad, followed by predetermined wiring and sealed with a molding agent.
本発明の方法によって得られる半導体装置のパッケージ
は、例えば第２図に示すように、パッド２上にはＪＣＲ
保護膜はなく、ボンディングワイヤー４はＪＣＲとは全
く接触しない構成となっている。In the semiconductor device package obtained by the method of the present invention, for example, as shown in FIG.
There is no protective film, and the bonding wire 4 is configured not to come into contact with the JCR at all.
以下、本発明の方法を添付第１図に従って更に詳しく説
明する。Hereinafter, the method of the present invention will be explained in more detail with reference to the attached FIG. 1.
第１図（ａ）に従って、完成された半導体装置にはまず
パフシペーション膜としての表面保護膜７が形成される
。この保護膜材料としては従来公知の各種材料が使用で
き、典型的な例として、リンガラス（Ｐ Ｓ Ｇ）、５
１０２、ＳｉＮなどが例示でき、これらは化学蒸着法（
ＣＶＤ法）、プラズマＣＶＤ法、スパッタリング法、塗
布法などの各種薄膜形成法の中から各材料に応じて最適
の手段を選一び構成することができる。According to FIG. 1(a), a surface protection film 7 as a puffipation film is first formed on the completed semiconductor device. Various conventionally known materials can be used as this protective film material, and typical examples include phosphorus glass (PSG), 5
Examples include 102, SiN, etc., which are processed by chemical vapor deposition (
The optimum means can be selected from among various thin film forming methods such as CVD method), plasma CVD method, sputtering method, coating method, etc. according to each material.
次いで、該表面保護膜には、その半導体装置のパッド上
部分に、配線用の窓が形成される。これはフォトエツチ
ングにより実施でき、より詳しくいえば、フォトレジス
トを表面保護膜上に塗布し、マスクを通して露光し、次
いで現像することにより表面保護膜エツチング用窓を形
成し、次いでプラズマエツチング、スパッタエツチング
、イオンビームエツチングなどのドライエツチングの他
化学エツチングなどによりエツチングして形成すること
ができる。Next, a wiring window is formed in the surface protection film above the pad of the semiconductor device. This can be done by photo-etching, and more specifically, a photoresist is applied onto the surface protective film, exposed through a mask, and then developed to form a window for surface protective film etching, followed by plasma etching and sputter etching. It can be formed by dry etching such as ion beam etching or chemical etching.
ここで、フォトレジストとしては各種公知のポリケイ皮
酸系樹脂、シスイソプレンとアリルジアジド架橋剤とを
組合せたもの、ノボラック型フェノール樹脂と０−キノ
ンアジドとのエステルなどの他、電子線レジストを使用
することも可能である。この場合、特にドライエツチン
グを利用する際にはレジストとしては表面保護膜よりも
エツチング速度が遅いもの、即ち選択比の高いものを選
択して使用する必要がある。Here, as the photoresist, in addition to various known polycinnamic acid resins, combinations of cis-isoprene and allyldiazide crosslinking agents, esters of novolac type phenolic resin and 0-quinone azide, and electron beam resists may be used. is also possible. In this case, especially when dry etching is used, it is necessary to select and use a resist that has a slower etching rate than the surface protective film, that is, one that has a high selectivity.
かくして、表面保護膜を形成した後、レジストを除去し
、第１図（６）に従ってＪＣＲを塗布する。After forming the surface protective film in this way, the resist is removed and JCR is applied according to FIG. 1 (6).
このＪＣＲとしては感光性ＪＣＲを用いることが好まし
く、典型的な例としてはメタクリレート化シリコーンを
主体とするネガレジスト（ｍｅｔｈａｃｒｙｌａｔｅｄ
ｓｉｌｉｃｏｎｅ ｂａｓｅｄ ｎｅｇａｔｉｖｅ ｒ
ｅｓｉｓｔ ；以下ＭＳＮＲという）、東しのフォトニ
ース、日立化成のＰＩＱ（ポリイミド系）などを挙げる
ことができる。表面の平坦化を確保するためには、例え
ばレジスト濃度を調整して粘度を下げたり、厚めに塗布
することが有利である。It is preferable to use photosensitive JCR as this JCR, and a typical example is a negative resist mainly composed of methacrylated silicone.
silicone based negative r
esist (hereinafter referred to as MSNR), Toshin's Photonice, and Hitachi Chemical's PIQ (polyimide type). In order to ensure flattening of the surface, it is advantageous to lower the viscosity by adjusting the resist concentration, for example, or to apply it thicker.
ＪＣＲ保護膜層の形成後、そのパッド上部分を除去する
。これは、ＪＣＲとして感光性ＪＣＲを用いた場合には
マスクを通して露光し、次いで現像（第１図（ｄ）参照
）し、硬化（第１図（ｅ）参照）し、第１図（ｆ）に示
したように配線を完了した後、モールド剤で封止されて
パッケージが完成される。上記ＭＳＮＲ，フォトニース
、ＰＩＱ等の現像液、エツチング液としては夫々専用の
市販品があり、それらを使用できる。After forming the JCR protective film layer, the portion above the pad is removed. When a photosensitive JCR is used as the JCR, it is exposed through a mask, then developed (see Figure 1(d)), hardened (see Figure 1(e)), and as shown in Figure 1(f). After completing the wiring as shown in Figure 2, the package is sealed with a molding agent. As developing solutions and etching solutions for the above-mentioned MSNR, Photonice, PIQ, etc., there are commercially available products dedicated to each, and these can be used.
第１図（Ｃ）の工程において、感光性ＪＣＲがネガ型の
場合にはマスクパターン１０によってマスクされたパッ
ド２上の部分のみが現像液に対して可溶性であり、一方
ポジ型のＪＣＲの場合には逆となる。この工程は必ずし
も上記のように行う必要はなく、例えばＪＣＲの硬化後
、さらにレジストを設け、エツチング窓を形成した後、
プラズマエツチング、スパッタエツチング、イオンビー
ムエツチングなどでパッド２上部分の窓明けを行うこと
も可能であり、当然本発明の範囲内にはいる。更にこの
ＪＣＲ保護膜の厚さは従来のものと同様であり１μｍ程
度である。In the process shown in FIG. 1(C), when the photosensitive JCR is negative type, only the portion on the pad 2 masked by the mask pattern 10 is soluble in the developer, whereas when the photosensitive JCR is positive type The opposite is true. This step does not necessarily need to be carried out as described above; for example, after curing JCR, further providing a resist and forming an etching window,
It is also possible to open the window in the upper part of the pad 2 by plasma etching, sputter etching, ion beam etching, etc., which is naturally within the scope of the present invention. Furthermore, the thickness of this JCR protective film is about 1 μm, which is the same as that of the conventional one.
また、第１図（ｅ）の工程における硬化工程は一般的な
フォトリソグラフィーにおけるレジストのポストベーク
処理と同様に行うことができ、従って加熱、紫外線等の
光照射などによって行うことができる。Further, the curing step in the step of FIG. 1(e) can be performed in the same manner as the post-baking treatment of the resist in general photolithography, and therefore can be performed by heating, irradiation with light such as ultraviolet rays, etc.
配線についても従来と同様であり、Ａ１、Ａｕなどの極
細線を公知のワイヤボンディング技術、例えば熱圧着法
、超音波ボンディング法などによってパッドと接合する
ことで実施される。The wiring is also the same as the conventional one, and is carried out by bonding ultrafine wires of A1, Au, etc. to pads using known wire bonding techniques, such as thermocompression bonding or ultrasonic bonding.
モールド剤としては各種公知のエポキシ系、シリコーン
系、フェノール系の樹脂などが、また硬化剤としては酸
無水物系、アミン系あるいはフェノール系の公知の物質
がいずれも使用でき、特に制限はない。また、封止法と
しては、封止すべき半導体装置の種類、特性等に応じて
、ポツティング法、キャスティング法、ディッピング法
、トランスファーモールド法などをいずれも利用できる
。As the molding agent, various known epoxy, silicone, and phenol resins can be used, and as the curing agent, any of the known acid anhydride, amine, or phenol substances can be used, and there are no particular limitations. Further, as the sealing method, potting method, casting method, dipping method, transfer molding method, etc. can be used depending on the type, characteristics, etc. of the semiconductor device to be sealed.
本発明の方法は各種半導体装置、特にプラスチックモー
ルド型パッケージに適した半導体装置全般のパッケージ
方法として有利に利用できる。The method of the present invention can be advantageously used as a packaging method for various semiconductor devices, particularly semiconductor devices in general that are suitable for plastic mold packages.
−作月
プラスチックモールド型の半導体装置のパッケージング
法において問題となっていた、ＪＣＲ保護膜とモールド
剤との間の界面における応力集中に基く配線用ワイヤー
の断線が、本発明の方法によってほぼ解決できた。即ち
、本発明の方法ではＪＣＲ保護膜を選択的に半導体装置
のワイヤボンディング用パッド上部分を除いて形成して
、配線用ワイヤーの通る空間部分にはＪＣＲ−モールド
界面が存在しないように工夫することによって断線の可
能性を著しく低下させることができた。- The method of the present invention has almost solved the problem of wire breakage due to stress concentration at the interface between the JCR protective film and the molding agent, which was a problem in the packaging method of plastic mold type semiconductor devices. did it. That is, in the method of the present invention, the JCR protective film is selectively formed except for the upper part of the wire bonding pad of the semiconductor device, so that there is no JCR-mold interface in the space where the wiring wire passes. This made it possible to significantly reduce the possibility of wire breakage.
一方、本発明の方法によりＪＣＲの選択的適用を行って
も、ＪＣＲ保護膜を利用する技術の開発前においてみら
れたモールド剤のストレスに起因する素子割れ、表面保
護膜の割れなどの不備も当然生じることはない。On the other hand, even if JCR is selectively applied by the method of the present invention, defects such as element cracking and cracking of the surface protective film caused by the stress of the molding agent, which were observed before the development of the technology using the JCR protective film, still occur. Of course it won't happen.
更に、本発明の方法は極めて簡単な工程で実施でき、配
線後の１素子毎へのＪＣＲ塗布が不要である。というの
は、本発明の方法によればウェハ状態でチップ全体にプ
リコートできるからである。Furthermore, the method of the present invention can be implemented through extremely simple steps, and there is no need to apply JCR to each element after wiring. This is because, according to the method of the present invention, the entire chip can be precoated in the wafer state.
１ｊ
Ｓｉウェハ上に多数の半導体チップを形成して得たＳｉ
半導体装置に対して、第１図（ａ）〜（ｆ）の各工程に
従って半導体装置のパッケージングを行った。1j Si obtained by forming a large number of semiconductor chips on a Si wafer
The semiconductor device was packaged according to the steps shown in FIGS. 1(a) to 1(f).
表面保護膜としてはＳｉＯ２膜を、ＪＣＲとしては前記
ＭＳＮＲを、配線ワイヤーとしてはＡＩ線を夫々用いた
。また、モールド剤としてはエポキシ系のものを用いた
。A SiO2 film was used as the surface protective film, the above-mentioned MSNR was used as the JCR, and an AI wire was used as the wiring wire. Furthermore, an epoxy-based molding agent was used.
同様にしてＪＣＲ保護膜を配線用ワイヤー接続後素子全
面に形成した従来のパッケージも比較のために作製した
。Similarly, a conventional package in which a JCR protective film was formed over the entire surface of the element after wiring wires were connected was also fabricated for comparison.
これら装置を実際に動作させて、配線用ＡＩワイヤーの
断線の有無を調べた。供試ウェハ中のチップにつき、断
線の発生頻度は本発明の方法で得たパッケージにおいて
は調べた範囲内では０であり、一方従来のものでは２％
程度の断線発生頻度を示した。These devices were actually operated to check for disconnections in the wiring AI wires. Regarding the chips in the test wafer, the frequency of occurrence of disconnection was 0 within the investigated range in the package obtained by the method of the present invention, while it was 2% in the conventional package.
The frequency of occurrence of wire breakage is shown below.
発明の効果
以上詳しく説明したように、本発明の方法により半導体
装置をパッケージソゲすることによって、ＪＣＲを用い
ない場合にみられた表面保護膜の割れ等の問題はもとよ
り、半導体装置全面に亘りＪＣＲ保護膜を設けた従来の
パッケージの有していた配線ワイヤーの断線の問題をほ
ぼ解決することが可能となった。Effects of the Invention As explained in detail above, by packaging a semiconductor device using the method of the present invention, problems such as cracks in the surface protective film that were observed when JCR is not used, as well as problems such as cracking of the surface protection film, can be solved, and the JCR can be removed over the entire surface of the semiconductor device. It has become possible to almost solve the problem of disconnection of wiring wires, which existed in conventional packages provided with a protective film.
従って、プラスチックモールドによる半導体装置のパフ
ケージングの信頼性が大巾に改善されるので、樹脂封止
法の応用範囲の拡大を図ることが可能となり、パッケー
ジングの歩留りも一段と向上することになる。Therefore, the reliability of puff casing of semiconductor devices using plastic molds is greatly improved, making it possible to expand the range of applications of the resin encapsulation method, and further improving the packaging yield.
更に、本発明の方法は簡単であり、ウェハ状態でチップ
全体にＪＣＲのプリコートを適用できるので、配線後の
１素子毎にＪＣＲを塗布するといった面倒な作業が不要
となる。Furthermore, the method of the present invention is simple and can pre-coat the entire chip in the wafer state with JCR, eliminating the need for the troublesome work of applying JCR to each element after wiring.
第１図（ａ）〜（ｆ）は、本発明の方法を実施する際の
各工程を模式的に図示したものであり、第２図は半導体
装置を本発明の方法に従ってパッケージングした状態で
模式的に示した図であり、第３図は従来のＪＣＲをチッ
プ全面に適用した半導体装置のパッケージを模式的に示
した図である。
（主な参照番号）
１・・半導体装置、 ２・・パッド、Figures 1(a) to (f) schematically illustrate each step in carrying out the method of the present invention, and Figure 2 shows a semiconductor device packaged according to the method of the present invention. FIG. 3 is a diagram schematically showing a package of a semiconductor device in which a conventional JCR is applied to the entire surface of the chip. (Main reference numbers) 1. Semiconductor device, 2. Pad,
Claims (3)
、フォトエッチングにより該半導体装置のパッド上部分
に配線金属接続用窓を設け、次いでジャンクションコー
トレジンの保護膜を形成し、露光、現像により該レジン
保護膜に配線用の窓を設け、次いで硬化処理した後、所
定の配線を施し、モールド剤で封止することを特徴とす
る半導体装置のモールド方法。(1) A surface protective film is formed on the surface of the completed semiconductor device, a window for wiring metal connection is provided above the pad of the semiconductor device by photo-etching, a protective film of junction coat resin is formed, and exposed and developed. A method for molding a semiconductor device, characterized in that a window for wiring is provided in the resin protective film, followed by curing treatment, predetermined wiring is applied, and the resin protective film is sealed with a molding agent.
であることを特徴とする特許請求の範囲第１項記載のモ
ールド方法。(2) The molding method according to claim 1, wherein the junction coat resin is photosensitive.
クリレート化シリコーンを主体とするネガレジストであ
ることを特徴とする特許請求の範囲第２項記載のモール
ド方法。(3) The molding method according to claim 2, wherein the photosensitive junction coat resin is a negative resist mainly composed of methacrylated silicone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60064928A JPS61224333A (en) | 1985-03-28 | 1985-03-28 | Molding method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60064928A JPS61224333A (en) | 1985-03-28 | 1985-03-28 | Molding method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61224333A true JPS61224333A (en) | 1986-10-06 |
Family
ID=13272190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60064928A Pending JPS61224333A (en) | 1985-03-28 | 1985-03-28 | Molding method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61224333A (en) |
-
1985
- 1985-03-28 JP JP60064928A patent/JPS61224333A/en active Pending
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